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ItC/l 



COSMOS Integrated Circuits 



Guide / Data / Application Notes 


Compliments of 

cramer 

CRAMER ELECTRONICS, INC. 

San Francisco (408) 739 3011 Seattle (206) 762-5755 








SSD-203C 

1975 


TOQBZ/D18S 


SSD-203C 

1975 DATABOOK Series 



A New Approach To Data Service . . . 

1975 RCA Solid State DATABOOKS 


Seven textbook-size volumes covering all current commercial 
RCA solid-state devices (through January 1, 1975) 

Linear Integrated Circuits and DMOS Devices 


(Data only) SSD-201C 

Linear Integrated Circuits and DMOS Devices 

(Application Notes only) SSD-202C 

COS/MOS Digital Integrated Circuits SSD-203C 

Power Transistors SSD-204C 

RF/Microwave Devices SSD-205C 

Thyristors, Rectifiers, and Diacs .SSD-206C 

High-Reliability Devices SSD-207C 


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Availabe FREE to all DATABOOK users. 

"Bingo-type Response-Card Service" included with News- 
letter Available FREE to all DATABOOK users. 

Update Mailing Service available by subscription. 

Indexed Binder available for Update Filing. 

NOTE: See pages 3 and 4 for additional information on this 
total data service. To qualify for Newsletter mailing, 
use the form on page 4 (unless you received your 
DATABOOK directly from RCA). You must qualify 
annually since a new mailing list is started for each 
edition of the DATABOOKS. 



VtC/1 

COSMOS Integrated Circuits 


This DATABOOK contains complete data and 
related application notes on COS/MOS digital 
integrated circuits presently available from RCA 
Solid State Division as standard products. For ease 
of type selection, functional diagrams are shown 
on pages 8-18. Data sheets are then included in 
type-number sequence, followed by output-drive- 
current test-circuit connections, terminal- 
assignment diagrams, and dimensional outlines for 
all types, by application notes in numerical order, 
and finally by a comprehensive subject index. 

To simplify data reference, data sheets are arranged 
as nearly as possible in numerical sequence of 
device type numbers. Because some data sheets 
include more than one type number, however, 
some types may be out of sequence. If you don't 
find the type you're looking for where you expect 
it to be, please consult the Index to Devices on 
page 7. 




Trade Mark(s) Registered® 
Marca(s) Registrada(s) 


Copyright 1974 by RCA Corporation 

(All rights reserved under Pan-American Copyright Convention) 


Printed in USA/11-74 


Information furnished by RCA is believed to be accurate and reliable. However, no responsibility is assumed 
by RCA for its use; nor for any infringements of patents or other rights of third parties which may result from 
its use. No license is granted by implication or otherwise under any patent or patent rights of RCA. 


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RCA Limited | Sunbury-on-Thames | Middlesex TW16 7HW, England 
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2 



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more than one is marked) 


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Linear IC's 

Digital IC's, COS/MOS 
Digital IC's, Bipolar 
Thyristors/ Rectifiers 
Liquid Crystals 
Semiconductor Diodes 
RF Power Semiconductors 
MOSFETS 
Power Transistors 
Power Hybrid Circuits 










Table of Contents 


Page 

Index 4 .o Application Notes 6 

Index to Devices 7 

Functional Diagrams: 

Gates 8 

Multivibrators 10 

Flip-Flops . 11 

Latches 11 

Shift Registers 12 

Counters 13 

Display Counters/Decoders/Drivers/Encoders .15 

Multiplexers . .16 

Arithmetic Circuits 17 

Phase-Locked Loop 17 

Schmitt Trigger .17 

Memories 18 

Rate Multipliers 18 

New Products Program 19 

Design and Operating Considerations . .21 

COS/MOS Family Characteristics 25 

Ordering Information 30 

1C Packages and Lead Forms . . .30 

Technical Data 31 

Appendix: 

Output-Drive-Current Test-Circuit Connections 42g 

Terminal-Assignment Diagrams 428 

Dimensional Outlines 435 

Application Notes 441 

Subject Index 461 


5 



Index to Application Notes 


Number Title 

ICE-402 "Operating Considerations for RCA Solid State Devices" 

ICAN-6000 "Handling Considerations for MOS Integrated Circuits" 

ICAN-6080 Digital-to-Analog Conversion Using the 

RCA-CD4007A COS/MOS 1C" 

ICAN-6086 "Timekeeping Advances Through COS/MOS Technology" 

1C AN-61 01 "The RCA COS/MOS Phase-Locked Loop — A Versatile Building 

Block for Micro-Power Digital and Analog Applications" 

ICAN-6166 "COS/MOS MSI Counter and Register Design 

and Applications" 

1C AN-61 76 "Noise Immunity of COS/MOS Integrated -Circuit Logic Gates" . 

ICAN-6210 "A Typical Data-Gathering and Processing System 

Using CD4000A-Series COS/MOS Parts" 

ICAN-6218 "Gate-Oxide Protection Circuit in RCA COS/MOS 

Digital Integrated Circuits" 

1C AN -6224 "Radiation Resistance of the COS/MOS CD4000A Series" 

ICAN-6230 "Using the CD4047A in COS/MOS Timing 

Applications" 

1 CAN -6267 "Astable and Monostable Oscillators Using RCA COS/MOS 

Digital Integrated Circuits" 

1C AN -6289 "A COS/MOS PCM Telemetry and Remote Data 

Acquisition Design" 

ICAN-6304 "Power Supplies for COS/MOS Systems" 

ICAN-6498 "Design of Fixed and Programmable Counters Using the 

RCA-CD4018A COS/MOS Presettable Divide-by-"N" Counter" . 

ICAN-6576 "Power-Supply Considerations for COS/MOS Devices" 

ICAN-6600 "Arithmetic Arrays Using Standard COS/MOS Building Blocks . . 

ICAN-6601 "Transmission and Multiplexing of Analog or Digital Signals 

Utilizing the CD4016A Quad Bilateral Switch" 

I CAN -6602 "Interfacing COS/MOS With Other Logic Families" 

ICAN-6716 "Low-Power Digital Frequency Synthesizers 

Utilizing COS/MOS IC's" 

ICAN-6733 "Battery-Powered Digital-Display Clock/Timer and 

Metering Applications Utilizing the RCA-CD4026A and 
CD4033A Decade Counters - 7-Segment Output Types" 

ICAN-6739 "COS/MOS Rate Multipliers — Versatile Circuits 

for Synthesizing Digital Functions" 


Page 

442 

447 

453 

459 

471 

479 

495 

503 

514 

516 

518 

531 

539 

551 

556 

562 

568 

574 

586 

598 


613 

629 


6 



Index to COS/MOS Integrated Circuits 

(Circuits marked with an asterisk (*) are also available in chip form. 

A data sheet on COS/MOS 1C chips. File No. 517, is available on request.) 


Type No. 

Description 

Page No. 

Type No. 

Description 

Page No. 

* CD4000A 

Dual 3-input NOR gate plus inverter 

32 

* CD4054A 

4-line liquid-crystal display driver 

267 

* CD4001A 

Quad 2-input NOR gate 

32 

* CD4055A 

BCD-7 -segment decoder/driver 

267 

* CD4002A 

Dual 4-input NOR gate 

32 

* CD4056A 

BCD-7-segment decoder/driver 

267 

* CD4004A 

Replaced by CD4024A Series 

- 

* CD4057A 

LSI 4-bit arithmetic logic unit 

273 

* CD4006A 

18-stage static shift register 

39 

CD4059A 

Programmable divide-by-N counter 

285 

* CD4007A 

Dual complementary pair plus inverter 

44 

* CD4060A 

14-stage ripple-carry binary counter/divider 


* CD4008A 

4-bit full adder with parallel carry 

50 


and oscillator 

291 

* CD4009A 

Hex buffer/converter (inverting) 

56 

* CD4061A 

256-word x 1-bit static RAM 

298 

. CD4010A 

Hex buffer/converter (non-inverting) 

56 

* CD4062A 

200-stage dynamic shift register 

305 

* CD4011A 

Quad 2-input NAND gate 

63 

* CD4063B 

4-bit magnitude comparator 

313 

* CD4012A 

Dual 4-input NAND gate 

63 

* CD4066A 

Quad bilateral switch 

319 

* CD4013A 

Dual "D" flip-flop with set/reset 

70 

CD4067B 

16-channel multiplexer/demultiplexer 

326 

* CD4014A 

8-stage static shift register 

76 

* CD4068B 

8-input NAND gate 

329 

* CD4015A 

Dual 4-stage static shift register 

81 

* CD4069B 

Hex Inverter 

334 

* CD4016A 

Quad bilateral switch 

86 

CD4070B 

Quad exclusive-0 R gate 

340 

* CD4017A 

Decade counter/divider 

94 

* CD4071B 

Quad 2-input OR gate 

342 

* CD4018A 

Presettable divide-by''N" counter 

99 

* CD4072B 

Dual 4-input OR gate 

342 

* CD4019A 

Quad AND-OR select gate 

104 

* CD4073B 

Triple 3-input AND gate 

348 

* CD4020A 

14-stage binary/ripple counter 

109 

* CD4075B 

Triple 3-input OR gate 

342 

* CD4021A 

8-stage static shift register 

114 

CD4076B 

4-bit D-Type register with 3 state outputs 

354 

* CD4022A 

Divide-by-8 counter/divider 

119 

CD4077B 

Quad exclusive NOR gate 

340 

* CD4023A 

Triple 3-input NAND gate 

63 

* CD4078B 

8-input NOR gate 

357 

* CD4024A 

7-stage binary counter 

124 

* CD4081B 

Quad 2-input AND gate 

348 

* CD4025A 

Triple 3-input NOR gate 

32 

* CD4082B 

Dual 4-input AND gate 

348 

* CD4026A 

Decade counter/divider 

130 

* CD4085B 

Dual 2-wide 2-input AND-OR-INVERT gate 

362 

* CD4027A 

Dual J-K master-slave flip-flop 

139 

* CD4086B 

Expandable 4-wide 2-input 


* CD4028A 

BCD-to-decimal decoder 

145 


AND-OR-INVERT gate 

368 

* CD4029A 

Presettable up/down counter 

150 

CD4089B 

Binary rate multiplier 

374 

* CD4030A 

Quad exclusive-0 R gate 

157 

* CD4093B 

Quad 2-input NAND Schmitt Triggers 

378 

* CD4031A 

64-stage static shift register 

162 

CD4094B 

8-stage shift -and-store bus register 

384 

* CD4032A 

Triple serial adder (positive logic) 

168 

CD4095B 

Gated J-K M-S Flip-Flop 


* CD4033A 

Decade counter/divider 

130 


(non-inverting J&K inputs) 

386 

* CD4034A 

MSI 8-stage static shift register 

173 

CD4096B 

Gated J-K M-S Flip-Flop 


* CD4035A 

4-stage parallel in/out shift register 

181 


(inverting & non-inverting J&K inputs) 

386 

* CD4036A 

4-word x 8-bit RAM (binary addressing) 

188 

CD4097B 

Differential 8-channel multiplexer/ 


* CD4037A 

Triple AND-OR bi-phase pairs 

195 


demultiplexer 

326 

* CD4038A 

Triple serial adder (negative logic) 

168 

CD4098B 

Dual monostable multivibrator 

388 

* CD4039A 

4-word x 8-bit RAM (word-line addressing) 

188 

CD4099B 

8-bit addressable latch 

392 

* CD4040A 

12-stage binary /ripple counter 

200 

CD4502B 

Strobed hex inverter /buffer 

394 

* CD4041A 

Quad true/complement buffer 

205 

CD451 1 B 

BCD to 7-segment latch decoder driver 

398 

* CD4042A 

Quad clocked "D" latch 

212 

* CD4514B 

4-bit latch/4-to-1 6 line decoder 


* CD4043A 

Quad 3-state NOR R/S latch 

216 


(high on select) 

401 

* CD4044A 

Quad 3-state NAND R/S latch 

216 

* CD4515B 

4-bit latch/4-to-16 line decoder 


* CD4045A 

21 -stage counter 

222 


(low on select) 

401 

* CD4046A 

Micropower phase-locked loop 

227 

* CD4518B 

Dual BCD up counter 

407 

* CD4047A 

Monostable/astable multivibrator 

234 

* CD4520B 

Dual binary up counter 

407 

* CD4048A 

Expandable 8-input gate 

245 

CD4527B 

BCD rate multiplier 

413 

* CD4049A 

Hex buffer/converter (inverting) 

252 

CD4532B 

8-input priorty encoder 

417 

* CD4050A 

Hex buffer/converter (non-inverting) 

252 

* CD4555B 

Dual binary to 1 of 4 decoder/ 


CD4051A 

Single 8-channel multiplexer 

259 


demultiplexer (high on select) 

419 

CD4052A 

Differential 4-channel multiplexer 

259 

* CD4556B 

Dual binary to 1-of-4 decoder/ 


CD4053A 

Triple 2-channel multiplexer 

259 


demultiplexer (low on select) 

419 


7 



GATES 

NOR/NAND, OR/AND 



Vss 

92CS-24766 


CD4072B 
Dual 4-Input 
OR Gate 
File No. 807 



92CS-24768 


CD4082B 
Dual 4-Input 
AND Gate 
File No. 806 



CD4075B 
Triple 3-Input 
OR Gate 
File No. 807 



CD4073B 
Triple 3-Input 
AND Gate 
File No. 806 



CD4071B 
Quad 2-Input 
OR Gate 
File No. 807 


V.DD 

Jli. 



92CS- 24769 


CD4081B 
Quad 2-Input 
AND Gate 
File No. 806 



v SS = 7 

92CS-23877RI 

CD4078B 
8-Input 
NOR Gate 
File No. 810 



V SS =7 

92CS-2 3874 

CD4068B 
8-Input 
NAND Gate 
File No. 809 



CD4002A 
Dual 4-Input 
NOR Gate 
File No. 479 



CD4012A 
Dual 4-Input 
NAND Gate 
File No. 479 



CD4000A 

Dual 3-Input NOR Gate 
Plus Inverter 
File No. 479 


8 








GATES 

NOR/NAND (Cont'd) 



CD4025A 
Triple 3-Input 
NOR Gate 
File No. 479 



92CS- 24761 


CD4023A 
Triple 3-Input 
NAND Gate 
File No. 479 



CD4001A 
Quad 2-Input 
NOR Gate 
File No. 479 



92CS-24763 

CD4011A 
Quad 2-Input 
NAND Gate 
File No. 479 


MULTI- LEVEL/FUNCTIONAL 



CD4070B 
Quad Exclusive- 
OR Gate 
Preliminary 


J*A©B L= E©F 
K S C©D M= G©H 

CD4030A 
Quad Exclusive- 
OR Gate 
File No. 503 



CD4077B 
Quad Exclusive- 
NOR Gate 
Preliminary 


92CS-25036 

CD4019A 
Quad AND/OR 
Select Gate 
File No. 479 


E * INHIBIT + AB+CD 
LOGIC I s HIGH 
LOGIC Os LOW 


CD4085B 
Dual 2-Wide, 2-Input 
AND-OR Invert (AOI) Gate 
File No. 811 


92CS-23890RI 


V DD * 14 


BINARY CONTROL INPUTS 
FUNCTION CONTROL 



92CS- 236 70RI J z INH + ENABLE + AB+CDF EF4- GH 


92CS-22249 



CD4086B 

Expandable 4-Wide, 2-Input 
AND- OR Invert (AOI) Gate 
File No. 812 


CD4048A 

Multifunctional Expandable 
8-Input Gate (3 Output States) 
File No. 636 


CD4037A 

Triple AND-OR Bi-Phase Pairs 
File No. 576 


9 







GATES 

Buffers & Inverters 


MULTIVIBRATORS 





V SS *7 

92CS- 2503 

V DD *I4 

CD4007A 

Dual Complementary 
Pair Plus Inverter 
File No. 479 


CD4069B 

Hex 

Inverter 
File No. 804 




CD4009A, CD4049A CD4010A, CD4050A 

File No. 479 File No. 599 File No. 479 File No. 599 


Hex Buffer/Converter 
Non-Inverting Type 


Hex Buffer/Converter 
Inverting Type 



CD4047A 
Monostable/Astable 
Multivibrator 
File No. 623 



C X 2 r X2 

92CS-24253 

CD4098B 

Dual Monostable Multivibrator 
Preliminary 


v ss =7 

V DD =, 4 92CS-20034RI 

CD4041A 

Quad True/Complement 
Buffer 
File No. 572 


THREE-STATE 
OUTPUT 4 
DISABLE 
INHIBIT — 



CD4502B 

Strobed 

Hex Inverter/Buffer 
Preliminary 


10 








FLIP- FLOPS 


LATCHES 




92CS- 25046 


92CS — 1 7I87RI 


CD4013A 
Dual "D" with 
Set/Reset Capability 
File No. 479 


CD4027A 
Dual "J-K" with 
Set Reset Capability 
File No. 503 



File No. 589 


DATA INPUT OUTPUT 

DISABLE DISABLE 



RESET 


92CS- 24885 


CD4076B 

4-Bit "D"-Type with 
3-State Outputs 
Preliminary 



Vss 

CD4043A 
Quad NOR R/S Latch 
(3 Output States) 
File No. 590 


92CS-2022IRI 



92CS-20222 

CD4044A 

Quad NAND R/S Latch 
(3 Output States) 

File No. 590 





CD4095B 

Gated J-K M-S Type 
Non-Inverting Inputs 
Preliminary 


CD4096B 

Gated J-K Nl-S Type 
Inverting and 
Non-Inverting Inputs 
Preliminary 


CD4099B 
8-Bit Addressable 
Latch 

Preliminary 


11 









SHIFT REGISTERS 



Vss 

92CS- Z5048 


CD4015A 

D(ial 4-Stage with Serial 
Input/Parallel Output 
File No. 479 



CD4006A 
18-Stage 
File No. 479 


PAR. IN- DD 
I 2 34 56 7 8 

tLUaUJisIiI 16 



Q|/0| Q3/O3 Q4/Q4 

T/c' OUT 

92CS-I9966 

CD4035A 

4-Stage Parallel-1 n/Parallel-Out 
with J-K Input 

and True/Complement Output 
File No. 568 


"A" DATA LINES 

2 3 4 5 6 7 8 V DI 


1 16 1 17 1 1 8 1 19 1 20 I 21 22 23 24 


7 6 5 4 3 2 I .2 


►DELAYED 
CLOCK T 

OUT- V S S 


CD4031A 
64-Stage 
File No. 569 



PARALLEL OUTPUTS QI-Q8 
92CS— 24564 

CD4094B 

8-Stage Shift-and-Store 
Bus Register 
Preliminary 


CD4014A 

Synchronous Parallel or 
Serial Input/Serial Output 

CD4021A 
Asynchronous 
Parallel Input/Serial Output 
Synchronous 
Serial Input/Serial Output 
File No. 479 


2 3 4 5 6 7 8, Vg, 

"b" data lines 


CD4034A 

8-Stage Bidirectional 
Parallel or Serial Input/Parallel Output 
File No. 575 


GENERATOR J— CL2D 


CD4062A 
200-Stage Dynamic 
File No. 816 


12 








COUNTERS 

Binary/Ripple 



7-Stage 
File No. 503 



92CS-23762RI 


CD4060A 

14-Stage Counter/Oivider 
and Oscillator 
File No. 813 




12 BUFFERED OUTPUTS 


V SS -8 

VdD**6 92CS-20522 

CD4040A 
12-Stage 
File No. 624 

Synchronous 




CD4017A CD4022A CD4018A CD4029A 

Decade Counter/Divider Divide-by-8 Counter/Divider Presettable Divide-by-"N" Counter Presettalbe Up/Down Counter 

Plus 10 Decoded Decimal Outputs with 8 Decimal Outputs Fixed or Programmable Binary or BCD-Decade 

File No. 479 File No. 479 File No. 479 Fi,e No - 503 


13 









COUNTERS 
Synchronous (Cont'd) 


PROGRAM JAM INPUTS (BCD) 



CD4059A 


92CM-222I3 


Programmable Divlde-by-"N" Counter 
Preliminary 



v ss 

92CS— 22916 


CD4518B 
Dual BCD 
Up-Counter 


CD4520B 
Dual Binary 
Up-Counter 


File No. 808 


Clock-Timer 




V DD 




4 , 5 , 6 , 9 . 10 , 11 , 12 , 13 * 
NO CONNECTION 



92CS- 20943 


CD4045A 
21 -Stage 
File No. 614 


14 










DISPLAY COUNTERS/DECODERS/DRIVERS/ENCODERS 




Vss 

92CS-2SOT6 



CD4026A 

Decade Counter/Divider with 7-Segment 
Display Outputs and Display Enable 
File No. 503 


CD4033A 

Decode Counter/Divider with 7-Segment 
Display Outputs and Ripple Blanking 
File No. 503 


CD4514B CD4515B 

4-Bit Latch/4-to-16 Line Decoders 
(High on Select) (Low on Select) 
File No. 814 



CD4511B 

BCD-to-7-Segment Latch 
Decoder Driver 
Preliminary 



CD4532B 

8-Input Priority Encoder 
Preliminary 


CD4054A 

4-Line Liquid-Crystal Display Driver 
File No. 634 





CD4055A 

Liquid Crystal BCD to 7-Segment Decoder/Driver 
with "Display-Frequency" Output 
File No. 634 


c^ ss ^ Vdd 



— 02) d [“SEGMENT 
| OUTPUTS 


92CS-2009I 

CD4056A 

Liquid Crystal BCD to 7-Segment Decoder/Driver 
with Strobed-Latch Function 
File No. 634 


15 









MULTIPLEXERS 


IN /OUT - 
SI6 A 
OUT/IN -i 

OUT/IN - 
SIG B 
IN/OUT - 

CONT 

B" 

CONT 

C 

v S s - 

92CS-2I627 



CD4016A CD4066A 

Quad Bilateral Switch 
File No. 479 File No. 769 



92CS- 24924 


CD4067B 

16-Channel 

Multiplexer/Demultiplexer 

Preliminary 



92CS-24980 


CD4097B 

Differential 8-Channel 
Multiplexer/Demultiplexer 
Preliminary 



CD4051A 
Single 8-Channel 
Preliminary 



CD4052A 

Differential 4-Channel 
Preliminary 



CD4053A 
Triple 2-Channel 
Preliminary 


92CS-2 2708 



Yss V SS 


92CS-229I9 

CD4555B CD4556B 

Dual 1-of-4 Decoder/Demultiplexers 
Output High Fj|eNo 858 Output Low 


TRUTH TABLE 



16 


i8 lo lo 18 (S lo lo 18 











MEMORIES 

Word-Organized 




CD4036A 

4-Word x 8-Bit (Binary Addressing) 
File No. 613 


CD4039A 

4-Word x 8-Bit (Direct Word-Line Addressing) 
File No. 613 


Bit-Organized 


v ss 

V DD 

N.C. 


A4 


a 5 


A 6 


a 7 



CD4061A 

256-Word by 1-Bit Static Random Access 
File No. 768 

RATE MULTIPLIERS 




92CS-229I4 


CD4527B 

BCD Rate Multiplier 
Preliminary 


CD4089B 

Binary Rate Multiplier 
Preliminary 


18 





NEW PRODUCTS PROGRAM 


The CD Preliminary COS/MOS types listed below are some of the devices scheduled for introduction during 1975. 
Logic diagrams and terminal assignment diagrams are shown following the listing. 

Additional types will also be announced throughout the year. For information concerning announcement dates and 
product availability*, contact your RCA representative or supplier, or watch for announcement in the RCA Solid State 
Announcement Newsletter "What's New In Solid State" referred to on the inside front cover of this DATABOOK. 


Preliminary 

CD Type 

Circuit Description 

Similar 

Industry 

Type 

CD4508B 

Dual 4-Bit Latch 

MCI 4508 

CD4510B 

4-Bit BCD Up/Down Counter 

MC14510 

CD4516B 

4-Bit Binary Up/Down Counter 

MC14516 

CD40100B 

32-Bit Left/Right Shift Register 

- 

CD40101 B 

9-Bit Parity Generator & Checker 

- 

CD40102B 

Presettable 8-Bit BCD Down Counter 

- 

CD40103B 

Presettable 8-Bit Binary Down Counter 

- 

CD40104B 

Three State 4-Bit Left/Right Shift Register 

- 

CD40105B 

4-Word X 4-Bit FIFO Buffer 

- 

CD40106B 

Hex Schmitt Trigger Inverter 

- 

CD40107B 

Dual 2-Input NAND Buffer/Driver 

- 

CD40108B 

4X4 Multiport Register 

- 

CD40181 B 

4-Bit Arithmetic Logic Unit 

- 

CD40182B 

Look-Ahead Carry Block 

- 

CD40192B 

Synchronous 4-Bit BCD Up/Down Counter (Dual Clock) 

- 

CD40193B 

Synchronous 4-Bit Binary Up/Down Counter (Dual Clock) 

- 

CD40194B 

4-Bit Left/Right Shift Register 

— 

: the wide interest in COS/MOS parts, RCA reserves the right to limit sample quantities. 



SHIFT 

REGISTERS 





CD40105B 

4-Word x 4-Bit FIFO Buffer 



Vdd = 16 
V SS =8 


92CS- 24822 


CD40108B 

4x4 Multiport Register 


SHIFT 

LEFT/RIGHT 

RECIRCULATE SELECT 


I, 5, 7, 10, 14, 15 : NC 
V DD= 16 '. V SS = 8 

CD40100B 

32-Bit Left/Right Shift Register 



92CS- 24813 



CD40194B 

4-Bit Left/Right Shift Register 


CD40104B 

3-State 4-Bit Left/Right 
Shift Register 


19 









4-Bit Up/Down Counters 


COUNT UP 
COUNT DOWN 



CARRY OUT 
BORROW OUT 


CD40192B CD40193B 

BCD Binary 

Synchronous 4-Bit Up/Down Counters 


LATCHES 

3— STATE — 1 



V DD =24 
— 1 V SS -12 

92CS-24823 


CD4508B 
Dual 4-Bit Latch 


BUFFERS AND INVERTERS 


PO PI P2 P3 P4 P5 P6 P 7 


14 CARRY OUT/ 

ZERO DETECT IN I 4 


CD40102B 

BCD 


CD40103B 

Binary 


Presettable 8-Bit Down Counters 



I, 2, 6, 8, 9,13 : NC 92CS-! 

CD40107B 

Dual 2-Input NAND Buffer/Driver 


— J V SS = 7 

92CS-24820 



V D D s|4 

Vg S »7 92CS-248I8 

CD40106B 
Hex Schmitt- 
Trigger Inverter 


ARITHMETIC 

CIRCUITS 


PARITY GENERATOR 



CD40182B 

Look-Ahead-Carry Block 


SO SI S2 S3 
6 5 4 3 


a! 


A? 

Jin 

A3 

I9_ 

r bo u 

bT 

_22 n 

B2 


R3 

.8 

Cl 

7 

M 

8 

V D D ! 

= 24 

Vss ! 

= 12 


-JO 

FT 

-JL 

F2 

-J! 

F3 

14 

A S B ' 


I6C i+ 4 RIPPLE 

± 22 - CARRY 

OUT 


CD40181B 

4-Bit Arithmetic Logic Unit 



CD40101B 

9-Bit Parity Generator 
and Checker 


20 












COS/MOS Design and Operating Considerations 


The information on the following pages serves as a brief 
introduction to COS/MOS specifications, ratings, and perform- 
ance characteristics. This information is included to help the 
user avoid problems in connection with over-all systems 
design. COS/MOS operation, design, and layout fundamentals 
are discussed in detail in the RCA COS/MOS Integrated 
Circuits Manual, CMS-27 1 . 

Maximum Ratings 

The maximum ratings for all the COS/MOS devices included 
in this book are as follows: 


Characteristic 

Symbol 

“A” Series “B” Series 

Unit 

Supply Voltage 

V DD- 

+ 15 to -0.5 +18 to -0.5 

Vdc 

Input Voltage, 

All Inputs 

V SS 

V 1 

V SS < V I< V DD 

Vdc 

Device Power 
Dissipation per 
package 

P D 

200 

mW 

Operating-Temperature 
Range: T 

Ceramic Packages 

-55 to + 125 

°C 

Plastic Package 


-40 to +85 

°C 

Storage-Temperature 

Range: T stg 

-65 to +150 

°c 

Lead Temperature 
(during soldering) 
at a distance of 

1/1 6± 1/32 inch 
(1.59±0.79 mm) 
from case for 

10 sec. 

^lead 

+265 

°c 


Operating Supply-Voltage Range 

COS/MOS integrated circuits are specified in one of two 
supply-voltage ranges: “ A”-series devices operate from 3 to 1 5 
volts, and “B”-series devices from 3 to 18 volts. Logic systems 
occasionally experience transient conditions on the power- 
supply line which, when added to the nominal power-bus 
voltage, could exceed the safe limits of circuits connected to 
the power bus. Recommended supply-voltage ranges which 
realistically assess these conditions are 4 to 12 volts for 
“A”-series devices, and 4 to 15 volts for “B”-series devices. 

The recommended maximum power-supply limit is substan- 
tially below the minimum primary breakdown limit for the 
devices to allow for limited power-supply transient and 
regulation limits. The minimum recommended supply voltage 
of 4 volts also takes into account transient and regulation 


limits. In addition, circuits that operate in a linear mode over a 
portion of the voltage range, such as RC or crystal oscillators, 
often require a supply voltage of at least 4 volts. 

Power Dissipation 

Power dissipation in a COS/MOS device is composed of two 
terms, quiescent (dc) dissipation and dynamic (ac) dissipation, 
Pq and P ac respectively. Quiescent dissipation, generally 
varying from a few nanowatts for small devices to tens of 
microwatts for large devices, is due to a combination of 
leakage effects comprising parasitic junction diodes (normally 
reverse-biased) and surface effects. Dynamic dissipation is 
comprised of two elements: (1) “through”-current that exists 
during the transition from one logic level to the other, when 
both N-MOS and P-MOS devices are momentarily conducting 
simultaneously, and (2) power-supply current required to 
charge the node and output capacitance during switching. 

The first component (internal switching) of dynamic 
dissipation is usually negligible compared to the component 
associated with charging capacitance, particularly for systems 
with fast rise and fall times. As transition times increase, 
however, through-current increases appreciably and the total 
current is a complex function of the transition times and 
capacitance. 

In most circuits, the ac dissipation (P ac ) in watts is equal to 
C 0 f # where Cq is the effective output capacitance 

(including load capacitance) in farads, Vpp is the supply 
voltage in volts, and f is the frequency in Hz. Because the 
output capacitance must be charged from Vgg to once 
each period, dynamic dissipation increases linearly with 
frequency and load capacitance, and as the square of the 
supply voltage V^. Each COS/MOS data sheet includes a 
curve showing dynamic power dissipation as a function of 
frequency. Fig. 1 shows switching current and voltage 
waveforms for different values of load capacitance and input 
rise and fall times. 

System Noise Considerations 

In general, COS/MOS devices are much less sensitive to 
noise on power and ground lines than bipolar logic families 
(such as TTL or DTL). However, this sensitivity varies as a 
function of the power-supply voltage, and more importantly as 
a function of synchronism between noise spikes and input 
transitions. Good power distribution in digital systems 
requires that the power bus have a low dynamic impedance; 
for this purpose, discrete decoupling capacitors should be 
distributed across the power bus. 

Power-Source Rules 

The safe operating procedures listed below can easily be 
understood by reference to the basic COS/MOS inverter and 
its gate-oxide protection network plus inherent diodes, as 
shown in Fig. 2. 

1 . When separate power supplies are used for the COS/MOS 


21 



COS/MOS Design and Operating Considerations 



0^ * 15 pF 



Y 


~~r 



1 




— 





— 

f\ 




— 





— 



-A 



(b) INPUT t r , tf “400 ns 
C L =I5 pF 


V DD 
V 0 UT 

v ss 

5.0 
IqD 25 
0 
5.0 
ISS 2 -5 
0 

92CM -25118 

Fig. 1— Switching-current waveforms. 


Y 

f 

r 

■ j 

V 


J 

_ i 


r 

— 



\ 



:_A 


J \ 


Zl 


a 


n 

tfi 

L - 

A 


__L 


(c) INPUT t r , tf “40 ns 
C L = 65 pF 


device and for the device inputs, the device power supply 
should always be turned on before the independent input 
signal sources, and the input signals should be turned off 
before the power supply is turned off (Vgg <V I < V DD as 
a maximum limit). This rule will prevent over-dissipation and 
possible damage of the D2 input-protection diode when the 
device power supply is grounded. When the device power 
supply is an open circuit, violation of this rule can result in 
undesired circuit operation although device damage should not 
result; ac inputs can be rectified by diode D2 to act as a power 
supply. 

2. The power-supply operating voltage should be kept safely 
below the absolute maximum supply rating, as indicated 
previously. 


3. The power-supply polarity for COS/MOS circuits should 
not be reversed. The data sheets state that the positive (Vqjj) 
terminal should never be more than 0.5 volt negative with 
respect to the negative (Vg§) terminal - V SS >-0.5V). 



This absolute maximum rating means that reversal of polarity 
will forward-bias and short the structural and protection diodes 
between Vj)j) and Vgg. 

4. should be equal to or greater than for 

COS/MOS buffers which have two power supplies (in 
particular, for CD4009A and CD4010A COS/MOS-to-TTL 
“down”-conversion devices). 

5. Power-source current capability should be limited to as 
low a value as reasonable to assure good logic operation. 

6. Large values of resistors in series with VjQj) or Vgg 
should be avoided; transient turn-on of input protection 
diodes can result from drops across such resistors during 
switching. 

Gate-Oxide Protection Networks 

A problem occasionally encountered in handling and testing 
low-power semiconductor devices, including MOS and small- 
geometry bipolar devices, has been damage to gate oxide 
and/or p-n junctions. Fig. 3 shows the gate-oxide protection 
circuits used to protect COS/MOS circuits from static 
electricity damage. ICAN-6218 gives further information on 
protection circuits. Although these circuits are included in all 
COS/MOS devices, the handling precautions discussed in 
ICAN-6218 and in IC AN-6000 should be observed. 

Input Signals and Ratings 

1. Input signals should be maintained within the power- 
supply voltage range, Vgg < Vj < * n a PPli cat i° ns such 
as astable and monostable multivibrators, input current can 
flow and should be limited to the microampere level by use of 
a resistor in series with the input terminal affected. 

2. All COS/MOS inputs should be terminated. When 
COS/MOS inputs are wired to edge card connectors with 
COS/MOS drive coming from another PC board, a shunt 
resistor should be connected to or Vg§ in case the inputs 
become unterminated with the power supply on. 


22 





COS/MOS Design and Operating Considerations 



92CS-22087 

(a) 



GATES 

Vss 


D3-25V 


92CS-22888 


(b) 


GATE 2^ 



n+ D2* 1 
I-* - J 

Ip- WELL 

■ 

n+ 

INPUT 

0 — < 

W 1 

v ss 

Dl* 

a, 

#- 

OUTPUT 

— O 


P + J 

-n-SUB 

' Dl > 

P+ 02 ' 


GATE ll 


( c ) 92CS-22883 


V DD 

_L 




(d) "ss 


irDi 

(MOST 

OUTPUTS) 


92CS- 22884 


01 * 25 V 
D2 » 50 V 


* THESE DIODES ARE 
INHERENTLY PART OF 
THE MANUFACTURING 
PROCESS 


Fig. 3— Protection circuits used in COS/MOS devices: (a) normal gate 
input protection ; (b) CD4059A and CD4050A gate input 
protection; (c) transmission-gate input-output protection; (d) 
active (inverter) output protection. 


3. When COS/MOS circuits are driven by TTL logic, a 
“pull-up” resistor should be connected from the COS/MOS 
input to 5 volts (further information is given in ICAN6602). 

4. Input signals should be maintained within the recom- 
mended input-signal-swing range. 

Output Rules 

l v . The power dissipation in a COS/MOS package should not 
exceed 200 milliwatts. The actual dissipation should be 
calculated when (a) shorting outputs directly to Vpj) or Vgg, 
(b) driving low-impedance loads, or (c) directly driving the 
base of a p-n-p or n-p-n bipolar transistor. 

2. Output short circuits often result from testing errors or 
improper board assembly. Shorts on buffer outputs or across 
power supplies greater than 5 volts can damage COS/MOS 
devices. 

3. COS/MOS, like active pull-up TTL, cannot be connected 
in the “wire-OR” configuration because an “on” P-MOS and 
an “on” N-MOS transistor could be directly shorted across the 
power-supply rails. 

4. Paralleling inputs and outputs of gates is recommended 
only when the gates are within the same IC package. 

5. Output loads should return "to a voltage within the 
supply-voltage range (Vj)j) to Vgg). 

6. Large capacitive loads (greater than 5000 pF) on 
COS/MOS buffers or high-current drivers act like short circuits 
and may over-dissipate output transistors. 

7. Output transistors may be over-dissipated by operating 
buffers as linear amplifiers or using these types as one-shot or 
astable multivibrators. 

Noise Immunity 

The complementary structure of the inverter, common to 
all COS/MOS logic devices, results in a near-ideal input-output 
transfer characteristic, with switching point midway (45% to 
55%) between the 0 and 1 output logic levels. The result is 
high dc noise immunity. 

Fig. 4 illustrates minimum and maximum transfer character- 
istics useful for defining noise immunity for an inverter and a. 


non-inverter. The noise-immunity voltage (V^, V^) is that 
noise voltage at any one input which will not propagate 
through the system. Minimum noise immunity is 30% of the 
supply voltage (20% for some buffer types). Some noise- 
immunity definitions are given below: 

V IL max = the maximum input voltage at low-level input 
for which the output logic level does not change state. 

Vih min = the minimum input voltage at high-level input 
for which the output logic level does not change state. 

V NL = V IL 

V NH ~ V DD -V IH 

Vqh min = minimum high-level output voltage (logic 1 
level) for rated (for an inverting logic function) or V NH 
(for a non-inverting logic function). 

VqL max = maximum low-level output voltage for rated 
V NH (f° r an inverting logic function) or (for a 

non-inverting logic function). 

Noise immunity . increases as the input noise pulse width 
becomes less than the propagation delay of the circuit. This 
condition is often described as ac noise immunity. (Further 
information on noise immunity is given in ICAN-6176.) 



(a) (b) 

92CS-25I03 


Fig. 4— Minimum and maximum transfer characteristics for (a) inverting 
logic function, and (b) non-inverting logic function. 


23 




COS/MOS Design and Operating Considerations 


Clock Rise- and Fall-Time Requirements 

All COS/MOS clocked devices have maximum clock rise- 
and fall-time ratings (normally 5 to 15 microseconds). With 
longer rise or fall times, a device may not function properly 
because of data ripple-through, false triggering problems, etc. 
Long rise and fall times on COS/MOS buffer-type inputs cause 
increased power dissipation which may exceed device capa- 
bility for power supplies above 5 volts. 

Parallel Clocking 

Process variations leading to differences in input threshold 
voltage among random device samples can cause loss of data 
between certain synchronously clocked sequential circuits, as 


shown in Fig. 5. This problem can be avoided if the clock rise 
time (t r CL) is made less than the total of the fixed 
propagation delay plus the output transition time of the first 
stage, as determined from the device data for the specific 
loading condition in effect. Schmitt Trigger circuits such as the 
CD4093B are an ideal solution to applications requiring 
wave-shaping. 

Three-State Logic 

Three-state logic can be easily implemented by use of a 
transmission gate in the output circuit; this technique provides 
a solution to the wire-OR problem in many cases. 


CASCADING WITH SLOW CLOCK 
CAN CAUSE ERROR 



0 Q| 

— 

a 

o 

— 










CL- 



Fig. 5— Error effect that results from a slow dock in cascaded circuits. 





COS/MOS Family Characteristics 


Overview 

CD4000A Series — RCA COS/MOS types designed for 
3-to-l 5-volt operation; all package styles 

CD4000B Series — RCA COS/MOS types designed for 
3-to-l 8-volt operation; all package styles 

CD4500B Series — RCA COS/MOS types similar to industry 
4500-series types designed for 3-to-l 8-volt operation; all 
package styles 

Packages 

Dual-in-line Plastic — suffix AE or BE (-40°C to +85°C 
operation) 

Dual-in-line Ceramic — suffix AF or BF (-55°C to +125°C 
operation) 

Dual-in-line Welded-Seal Ceramic - suffix AD or BD (-55°C 
to +125°C operation) 

Flat-Pack Ceramic - suffix AK or BK (-55°C to +125°C 
operation) 

Chip Form — suffix AH or BH (*55°C to + 125°C operation) 

Features 

Ultra-Low Quiescent Power: 

0.005 to 0.05 juW typical for SSI at V DD = 5 V 
0.1 to 0.5 pW typical for MSI at V DD = 5 V 
Wide Output- Voltage Swing when Driving COS/MOS: 
High-level output — typically Vqq 
L ow-level output — typically Vgg 
High Noise Immunity: 

45% of Vj) D typical 

30% of Vj)j) guaranteed on most devices 
High Fan-Qut Driving COS/MOS: greater than 50 
Input Current: ±10 pA typical 

Standard Input-Protection Circuit: double diode clamps 
plus series resistor 

Low Input Capacitance: 5 pF typical 


Static Electrical Characteristics 

Quiescent Device Current (1^). The quiescent current is the 
device current drawn by an IC in the steady-state condition 
with no load on the output. The IC inputs are tied either to 
the positive (V DD ) terminal or the negative (Vg S ) terminal 
when quiescent current is measured. 

Most devices exhibiting typical or “low” leakage currents at 
room temperature (25°C) are dominated by p-n junction 
leakage. For these devices, 1^ doubles approximately every 
ll°C. Devices exhibiting leakage currents close to the 
maximum rating are dominated by surface leakage and will not 
generally follow an exponential characteristic, i.e., surface 
leakage current will usually increase at a considerably slower 
rate than junction leakage as the temperature is increased. 

Typical and minimum values for I L are given on individual 
30S/MOS data sheets. For “B”-series devices, these values are 
standardized for SSI types and for MSI types. Quiescent- 


device-current test circuits are also shown on the individual 
data sheets. 

Output Voltage Levels (Vq^ and Vqjj). Vq^ is the 
logic-“0” or low-level output voltage. Vqjj is the logic-“l” or 
high-level output voltage. Vq^ and Vq^j are specified under 
no load with inputs set at V DD or Vgg (i.e., noise-free input 
conditions). Values for both “A”-series and “B”-series devices 


are as follows: 

Low-Level Output (Vqj ): 

Typical value at +25 u Ground (Vg S ) 

Maximum value at -40°C/-55°C 0.01V 

Maximum value at +85°C/+125°C 0.05V 

High-Level Output (Vqjj): 

Typical value at 25°C ^DD 

Minimum value at -40°C/-55°C (^DD — 0.01 ^ 

Minimum value at +85°C/+125°C O^DD _ 0-05 V) 


Voltage and Current Transfer Characteristics. Curves of 
voltage and current input/output characteristics are given in 
the individual data sheets for inverter, gate, and buffer devices. 

DC Noise Immunity (V^ and Noise-immunity 

definitions were covered previously. Values for both “A” -series 
and “B”-series devices are given below: 


II 

1 

^OH 

V NL (at 25°C) 


Inverting Inverting 

SSI Devices MSI Devices 

Typ. 

Max. 

5 

3.6 

4.2 

2.25 

1.5 

10 

7.2 

9.0 

4.5 

3.0 

15* 

10.8 

13.5 

6.75 

- 

V NH 

V DD 

V OL < max ) 


V NH (at 25° C) 


Inverting Inverting 

SSI Devices MSI Devices 

Typ. 

Max. 


“A” Series “B” Series 




5 

0.95 1 .4 

0.8 

2.25 

1.5 

10 

2.9 2.8 

1.0 

4.5 

3.0 

15* 

4.2 

1.5 

6.75 

- 


*Specified for “B” series only. 


Noise-immunity test circuits are shown on individual device 
data sheets. 

Output Drive Current (IpN and I{)P). IqN is the output 
sink current (existing in the N-MOS device) when the P-MOS 
device is “off’ and the N-MOS device is “on”, i.e., logic “0” 
state. IpP is the output source current (existing in the P-MOS 
device) when the N-MOS device is “off’ and the P-MOS device 
is “on”, i.e., logic “1” state. Output-drive-current values are 
given in the individual data sheets. For CD4000B- series 
devices, these values are standardized as follows: 


25 



COS/MOS Family Characteristics 


CHARAC- 

TERISTIC 

SYMBOL 

Vo 

Volts 




125°C 

UNITS 

my 

IBS 


[2221 

Typ. 

U2S 

U22I 

BBS 

1221 

Output Drive 
Current: 

N-Channel 

(Sink) 

i d n 

0.4 

H 

0.5 

■ 

■ 

0.4 

0.8 

■ 


■ 

■ 

mA 


mm 

msa 

- 

- 


■Oi 

- 

n 

- 

- 

mm 

mm 

- 

- 

- 

3 

6 

- 

- 

- 

- 

P-Channel 

(Source) 


mm 

5 

-2 

- 

- 

BO 

WMM 

- 

BE 

- 

- 

mA 

Ea 

5 

BiJEl 

- 

- 

fated 

belb 

- 

ESI 

- 

- 

BEEI 

10 

-1.1 

- 

- 

EH 

mm 

- 


- 

- 

BES3 

mm 

- 

- 

- 

-3 

-6 

- 

- 

- 


Output Drive 
Current: 

N-Channel 

(Sink) 

IdN 

0.4 

5 

0.45 

■ 

■ 

0.4 

0.8 

■ 

0.36 

■ 

■ 

mA 


WltW 

1 

- 

- 

QS 

1.8 

- 

EE9 

- , 

- 

mm 

mm 

- 

- 

- 

3 

6 

- 

- 

- 

- 




5 

BH 

- 

- 

BH 

BESS 

HI 

BH 

_ 

- 

mA 

mm 

5 

B3B1 

- 

- 

BiEW 

ESS 

■ 

BSE1 

- 

- 


mm 

-1 

- 

- 

Brikil 

-1.8 

- 

BSSl 

- 

- 

im 

mm 

- 

- 

- 

BM 

-6 

- 

- 

- 

- 


These charts show that at +25°C drive-current limits are the 
same for all package styles, i.e., they are standardized for all 
packages. “B”-series drive-current characteristics curves are 
also standardized. CD4500B-series devices have the same Ij)N 
characteristics, but in some devices the Ij)P capability differs 
from standard CD4000B-series standards, although it is 
identical with similar 4500-series industry types. Figs. 6 and 7 
show the normalized variation of output currents (source and 
sink currents) with respect to temperature and voltage for 
typical “B”-series devices. 


Fig. 8 shows a typical test setup for output drive current. 
The input switches SI, S2, S3. . S^ are set to positions (or, in 
sequential logic, sequenced to positions) which will cause the 
output terminal under test to be at the desired logic level (“0” 
for Ij)N, “1” for Ij)P). Output switch S4 is positioned to 
connect an ammeter from the output terminal under test to a 
separate power source which is to be set to the V 0 value 
specified in the applicable data sheet. Drive current is 
measured by means of meter Ml. Test-circuit connections for 
individual COS/MOS devices are given in the Appendix. 




92CS-25III 


Fig. 6— Variation of normalized sink current (IqN) and source current 
(l D P) with temperature. 


26 






























COS/MOS Family Characteristics 




Fig. 7— Variations of normalized sink current (IqN) and source 
current (IqP) with supply voltage. 



Fig. 8— Output-drive-current test circuit. 


Input Current (Ij). Input current Ij is the current measured 
in an input pin with the input voltage at Vqq or Vgg; it 
consists only of leakage current existing primarily in 
protection-circuit diodes. 

Ij (tyP-) = ± 10 pA for “A” and “B” series COS/MOS 
Ir (max.) = ± 1 pA for “B” series COS/MOS at T* = 25° C, 
V DD =15V 

Fig. 9 shows a typical test setup for input current. Switches 
SI, S2, S3. . . Sjsj are set to positions which connect the input 



Fig. 9— Input-current test circuit. 


terminal under test through current meter M 1 to either V^ 
or Vgg (determined by position of S4). Input terminals not 
under test are connected to v ss- Output terminals are open. 
Input current is indicated by meter Ml. 

Threshold Voltage. Threshold voltages of n- and p-channel 
devices generally range from 0.7 to 2.8 volts, centered around 
1.5 volts. Noise-immunity specifications, which are shown on 
all COS/MOS data sheets, provide the necessary controls on 
device thresholds and are generally useful for commercial 
applications purposes. Values of threshold voltage are specified 
for high-reliability COS/MOS devices, and are shown in the 
High-Reliability Devices DATABOOK, SSD-207. Detailed 
circuits and connections for threshold-voltage tests are also 
shown in SSD-207. 

Dynamic Electrical Characteristics 

For “A”-series COS/MOS devices, dynamic electrical charac- 
teristics are measured at V DD = 5 V and 10 V, T^ = 25°C, 

= 1 5 pF and input t f and t^ = 20 ns. Typical temperature 
coefficient for dynamic characteristics is | 0.3%/°C | (negative 
for maximum clock frequency, positive for other time 
parameters). “B”-series devices are measured at V D p = 5 V, 10 
V, and 1 5 V, T^ = 25°C, C^ = 50 pF, and input t r and tf = 20 
ns. Figs. 10-12 show the normalized variation of transition 
time (tTLfl anc * ^HL) propagation delay time (tpjjL 
and tpLH) with respect to temperature and voltage for 
“B”-series devices. 


27 










COS/MOS Family Characteristics 



SUPPLY VOLTAGE (V 0D ) — VOLTS 


92CS-25II4 

Fig. 12-Variation of normalized propagation delay time (tp HL and 
tpL/-^ Wl *h supply voltage. 

Waveforms for measurement of dynamic characteristics are 
shown at right. Typical curves of dynamic characteristics are 
given in the individual data sheets. For CD4000B-series 
devices, values for transition time (tjHL anc * tTLH) are 
standardized, as shown below: 


V DD 

Typ. 

Max. 

Units 

5 

100 

200 

ns 

10 

50 

100 

ns 

15 

40 

80 

ns 


Curves of transition time ds a function of are also 
standardized for these devices, as shown in Fig. 13. 


AMB 

IENT TEMPERATU 

RE (T a )*25°C 

1 


I 

“ j 

ill 

Till 

1 


I 











56. ^ H Wf 


H 







2 100 fj-j-j- 


id - * 

Jifj-H. -f 

±: 


1: tt5 

Inr Vtffiffliii 


TtTTTl : # 

|: 

p§ 

1 g# 



TWTT# 


M 

'■*- 50 44# 

mm 



m 

Sr 

ililBliiii 


mm 

§§ 


O 20 40 60 80 100 

LOAD CAPACITANCE (C L I — pF 

92CS-24322 


Fig. 13— Variation of transition time ft-pHL and t TLH^ w,th load 
capacitances at three levels of supply voltage. 



CLOCK PULSE RISE AND FALL TIMES 


CLOCK 

k-‘r ct - 

#4 

- _l|CL 

S7-—.2 

*WL 

V D0 

9014 J - 

k— 50 * 

l 

• 'WL * 

> 

r * — 'wh — - 

0 


92CS -20070 


Transition Times and Propagation Delay Times for 
Combinational Logic Circuits 



Set-Up Times, Transition Times, and Propagation Delay Times 
for Positive-Edge-Triggered Sequential Logic Circuits 



92CS- 20068 

Set-Up Times, Transition Times, and Propagation Delay Times 
for Negative-Edge-Triggered Sequential Logic Circuits 


29 





ORDERING 

INFORMATION 

COS/MOS IC's are available in a wide 
variety of package designs. These pack- 
ages are identified by Suffix Letters indi- 
cated in the chart shown at right. When 
ordering COS/MOS devices, it is impor- 
tant that the appropriate suffix letter be 
affixed to the type number of the device 
required. 


CD4000A and CD4000B Series 


PACKAGE 

Suffix Letters 

Welded-Seal Ceramic Dual-ln-Line 

D 

Plastic Dual-ln-Line 

E 

Ceramic Dual-ln-Line 

F 

Ceramic Flat Pack 

K 

Chip 

H 

TO-5 Style 

T 


COS/MOS PACKAGES AND LEAD FORMS 




H-1703 



H-1803 


14- Lead 
Flat Pack "K" 


16- Lead 
Flat Pack "K" 


24-Lead 
Flat Pack "K" 


28- Lead 
Flat Pack "K" 


14-Lead Welded-Seal 
Dual-in-Line 
Ceramic "D" 


16-Lead Welded-Seal 
Dual-in-Line 
Ceramic "D" 




16-Lead Welded-Seal 
Dual-in-Line 
Ceramic "D" 


16-Lead Welded-Seal 
Dual-in-Line Side- 
Brazed Ceramic "D" 






24- Lead Welded-Seal 
Dual-in-Line 
Ceramic "D" 



14-Lead Dual-in- 
Line Plastic "E” 



28- Lead Welded-Seal 
Dual-in-Line 
Ceramic "D" 



14- Lead 

Dual-in-Line Ceramic "F" 



16- Lead 

Dual-in-Line Ceramic "F" 



H-1463 

12- Lead 
TO-5 "T" 



16-Lead Dual-in- 
Line Plastic "E" 


30 




Technical Data 


31 



File No. 479 

Digital Integrated Circuits 

Monolithic Silicon 

CD4000A,CD4001A 
CD4002 A ,CD4025A 

Types 



COS/MOS NOR Gates 
(Positive Logic) 

Special Features 

■ Medium speed operation. ..... tpuL = tpLH == 25 ns (typ.) 

at Cl = 15 pF 

■ Low "high"- and "low"-level output impedance 50012 

and 20012 (typ), respectively at Vqd — V SS = 10 V 

Dual 3 Input 

plus Inverter CD4000AD, CD4000AE, CD4000AF, CD4000AK 
Quad 2 Input CD4001AD, CD4001AE, CD4001AF, CD4001AK 
Dual 4 Input CD4002AD, CD4002AE, CD4002AF, CD4002AK 
Triple 3 Input CD4025AD, CD4025AE, CD4025AF, CD4025AK 


The combination of these devices and the RCA NAND can account for appreciable package-count savings in various 
positive logic gate types CD401 1 A, CD401 2A, and CD4023A logic function configurations. 






32 


9-74 







CD 4000 A, CD4001A, CD4002A, CD4025A 


File No. 479 


STATIC ELECTRICAL CHARACTERISTICS (All inputs Vss^V|<Vpp) 

(Recommended DC Supply Voltage (Vpp — Vg§) 3 to 15 V) 


TEST 

CONDITIONS 



CD4000AD,CD4001AD,CD4002AD,CD4025AD, 
CD4000AK ,CD4001 A K ,CD4002 A K ,CD 4025 A K , 
CD4000AF,CD4001AF,CD4002AF,CD4025AF 


25°C 125°C 
















File No. 479 


CD4000A, CD4001A, CD4002A, CD4025A 


STATIC ELECTRICAL CHARACTERISTICS (AH inputs Vss < V, < V DD ) 

(Recommended DC Supply Voltage (Vqq — Vjjg) 3 to 15 V) 


CD4000AE, CD4001AE. CD4002AE, CD4025AE 


CHARAC 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 



Maximum noise-free low-level Bipolar output voltage. 
^Minimum noise-free high-level Bipolar output voltage. 


AMBIENT TEMPERATURE (T A ) * 25°C 



7.5 10 12.5 15 

INPUT VOLTS (V T ) 


2.5 5 75 10 12.5 15 

DRAIN -TO -SOURCE VOLTS (V DS ) 


Fig. 1.7— Typ. current & voltage transfer 
characteristics. 


Fig. 1.8— Typ. n-channel drain characteristics. 




















CD4000A, CD4001A, CD4002A, CD4025A 


File No. 479 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, C L = 15pF,and input rise and fall times = 20 ns 
Typical Temperature Coefficient for all values of Vqq = 0.3%/°C. (See Appendix for Waveforms) 


CHARACTERISTIC 

■ 


LIMITS 

■ 

CHARAC- 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 
Fig. No. 

TEST 

CONDITIONS 

urn 

F, AK 

F,AK 

F, AK 

F. AK 

CD4000AE,CD4001AE 

CD4002AE.CD4025AE 


V DD 

(Volts) 


EH 


Min. 

Typ. 

Max. 

Propagation Delay Time: 
High-to-Low Level 



5 

- 



- 


■a 

D 

1.13 

10 

- 

B 

■a 

- 

25 

55 

Low-to-High Level 

tPLH 


5 

- 

35 

95 

- ■ 

35 

120 




- 

25 

45 

- 

25 

65 

Transition Time: 

High-to-Low Level 

tTHL 


5 

■- 

65 

125 


65 

200 

B 

1.14 

10 

- 

35 

70 

- 

35 


Low-to-High Level 



5 

- 

□ 


- 


£ 


1.14 

10 

- 



- 



Input Capacitance 


Any Input 

- 

B 


- 

5 

- 

pF 



DYNAMIC ELECTRICAL CHARACTERISTICS (Driving TTL,DTL) AT T A = 25°C, V DD“ V SS = 5V ' C L = 5pF 




TEST CONDITIONS 

LIMITS 


TYPICAL 

CHARACTERISTIC 

SYMBOL 


Driving 

CD4000AD, AF, AK 
CD4001 AD, AF, AK 
CD4002AD, AF, AK 
CD4025AD, AF, AK 

CD4000AE.CD4001 AE 
CD4002AE,CD4025AE 

UNITS 

CHARAC- 

TERISTICS 

CURVES 




TTL.DTL 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 


Fig. No. 

Propagation Delay Time: 


R l = 2kS2 

Med. 

Power 

- 

35 

- 

- 

35 

- 

ns 

1. 15 

High-To-Low Level 

tpHL 

R L = 20k S 2 

Low 

Power 

- 

35 

- 

- 

35 

- 

Low-To-High Level 


R l - 2kil 

Med. 

Power 

- 

15 

- 

- 

15 

- 

ns 

1.16 

l PLH 

R l ^ 20kS2 

Low 

Power 

- 

20 

- 

- 

20 


Transition Time 

l THL 

R l - 2k il 

Med. 

Power 

- 

40 

- 

- 

40 

- 

ns 


*TLH 

R l = 20k S 2 

Low 

Power 


40 

- 

- 

40 

- 



DRAIN -TO- SOURCE VOLTS (V os ) 




36 


Fig. 1.9— Typ. p-channef drain characteristics. 


Fig. 1. 10— Min. n-channel drain characteristics. 































92CS-I784 

Fig. 1. 11— Min. p-channel drain characteristics. 


AMBIENT TEMPERATURE (T A )-25 # C 
LOAD CAPACITANCE (C L ) - 15 pF 


!!!55!5!!!!5!-====== 


SUPPLY VOLTS (V DD ) 

92CS- I ! 

Fig. 1. 12-Typ. propagation delay time vs. Vqq. 


AMBIENT TEMPERATURE (T A ) = 25°C 

TYPICAL TEMPERATURE COEFFICIENT FOR ALL VALUES r 
OF V DD *0.3%/°C 


SUPPLY VOLTS IV DD ) * 5 


LOAD CAPACITANCE (C.)— pF 

92CS- 1778 

Fig. 1. 13—Typ. propagation delay time vs. C/_. 


AMBIENT TEMPERATURE (T A ) = 25°C 

TYPICAL TEMPERATURE COEFFICIENT FOR ALL VALUES 

OF Vnn = 0.3% /°C 


-SUPPLY VOLTS (Vool^Si" 


LOAD CAPACITANCE CC L )— pF 


Fig. 1. 14—Typ. transition time vs. Ci_. 


SUPPLY VOLTS (V DD )= 5 I 

AMBIENT TEMPERATURE (T A ) * 25 °C 
150 TIPICAL TEMPERATURE COEFFICIENT FOR- 
ALL VALUES OF V DD = 0.3%/«C h 



SUPPLY VOLTS (V DD ) * 5 
AMBIENT TEMPERATURE (T A ) * 25°C 
60 TYPICAL TEMPERATURE COEFFICIENT FOR ALL VALUES 
OF V dd «0.3%/»C , 



LOAD CAPACITANCE (C L )— pF 

92CS-I7783 

LOAD CAPACITANCE (C L )— pF 

92 

Fig. 1. 15— Typ./ow-level propagation delay 

time vs. C[_ — driving TTL & DTL. 

Fig. 1. 16-Typ. high-level propagation delay 
time vs. C{_ — driving TTL & DTL . 








CD4000A, CD4001A, CD4002A, CD4Q25A 


File No. 479 




I L PIN CONNECTIONS 

MEASUREMENT TO Vpp TO GND 

INPUTS I 3,11,8,14 4,5,7,12,13 

INPUTS 2 4,12,8,14 3,5,7,11,13 

INPUTS 3 5,13,8,14 3,4,7,11,12 

92CS-20729 



I L PIN CONNECTIONS 

MEASUREMENT TO V nn TO GND 

INPUTS I 1,5,8,12,14 2,6,7,9,13 

INPUTS 2 2,6,9,13,14 1,5,7,8,12 

92CS- 20730 


Fig. 1.17 — Typ. dissipation characteristics. 


Fig. 1. 18 - Quiescent device Fig. 1. 19 - Quiescent device 

current test circuit current test circuit 

for CD4000A. for CD4001A. 



MEASUREMENT 

TO Vpp 

TO GND 

INPUTS 1 

2,9, 14 

3, 4, 5, 7, 10,11,12 

INPUTS 2 

3,10,14 

2,4, 5,9,11,12 

INPUTS 3 

4,11, 14 

2,3,5,9,10,12 

INPUTS 4 

5,12,14 

2,3,4,9,10,11 


92CS- 20731 



INPUTS I 1,3,11,14 2,4,5,7,8,12,13 

INPUTS 2 2,4,12,14 1,3,5,7,8,11,13 

INPUTS 3 8,5,13,14 1,2,3,4,7,11,12 


92CS -20732 


VDD 5V 



92CS-20733 


Fig. 1.20 — Quiescent device 
current test circuit 
for CD4002A. 


Fig.1.21 — Quiescent device 
current test circuit 
for CD4025A. 


Fig. 1.22 — Noise immunity 
test circuit for CD4000A. 



92CS — 20734RI 92CS- 20735RI 92CS- 20736RI 


Fig. 1.23 — Noise immunity 
test circuit for CD4001 A. 


Fig. 1.24 — Noise immunity 
test circuit for CD4002A. 


Fig. 1.25 — Noise immunity 
test circuit for CD4025A. 


38 







File No. 479 


Digital Integrated Circuits 

Monolithic Silicon 

CD4006AD, CD4006AF 
CD4006AE, CD4006AK 



COSMOS 18-Stage 
Static Shift Register 

Special Features 

h Fully static operation 

■ Up to 5 MHz shifting rates 

■ Permanent register storage with clock line "high" or "low" — 
information recirculation required 

Applications 

■ Serial shift registers 

■ Time delay circuits ■ Frequency division 


no 


CD4006A types are comprised of 4 separate "shift register" 
sections; two sections of four stages and two sections of five 
stages with an output tap at the fourth stage. Each section 
has an independent "single rail" data path. 

A common clock signal is used for all stages. Data is shifted to 
the next stage on negative-going transitions of the clock. 


Through appropriate connections of inputs and outputs, 
multiple register sections of 4, 5, 8, and 9 stages or single 
register sections of 10, 12, 13, 14, 16, 17 and 18 can be 
implemented using one CD4006A package. Longer shift 
register sections can be assembled by using more than one 
CD4006A. 



TRUTH TABLE 

D 

FOR SHIFT 1 

cl a 

REGISTER STAGE 

D + l 

0 

\ 

0 

1 

\ 

1 

X 

I 

NC 


NC* NO CHANGE 
X * DON’T CARE 
a 3 LEVEL CHANGE 


92CS- J7887 


OUT 
IF 4th OR 
5th STAGE) 


FROM 
PREVIOUS 
STAGE 
(OR INPUT 
IF 1st 
STAGE) 


T‘ 



T 

1 

1 

1 

£. 

CL 


k„ " 

'.'.JL 

CL 



I f ^00 




J 

TT 

[>n 


j 

F 1 

V 

LtJ 

I] 

rW 

n±] 

n 

* v ss 


CL VdD 


NOTE: ALL V'-UNIT SUBSTRATES 
ARE CONNECTED TO V DD 
ALL "N"-UNIT SUBSTRATES 
ARE CONNECTED TO V ss 


92CS-I7894 


Fig. 3. 1— Logic diagram and truth table ( one register stage) 
for type CD4006A. 


Fig.3.2— Schematic diagram ( one register stage) 
for type CD4006A. 


10-73 


39 









CD4006A File No. 479 

STATIC ELECTRICAL CHARACTERISTICS (All inputs Vss < V , < V DD ) 

(Recommended DC Supply Voltage (Vqq — V 55) 3 to 15 V) 






LIMITS 


CHARAC 

CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 

CD4006AD, CD4006AK, CD4006AF 

UNITS 

TERISTIC 

CURVES 

& TEST 



. 

Vo 

V D d 

— 55°C 

25°C 

125°C 


CIRCUITS 




Volts 

Volts 

Min. 

■223 



B3TBB 



B2Z3 



Fig. No. 

Quiescent Device 



5 

- 

- 

■a 

- 

0.01 

0.5 


- 

m 



Current 

■l 


10 

- 

- 

- 

- 


1 

- 

- 

60 



Quiescent Device 

Pd 


5 

- 

_ 

B 

- 


m 

- 

- 

is 

pW 


Dissipation/Package 


10 

- 

- 

■a 

- 

EH 

10 

- 

- 



Output Voltage: 

VOL 


5 

- 

- 

HU 

- 

0 

0.01 

- 


m 

V 


Low-Level 


10 

- 

- 


- 

mm 


- 

- 

0.05 


High-Level 

v OH 


5 

EHI 

- 



5 

■■ 

HH3 

- 

- 




10 


- 

- 

yy 

10 




- 



Noise Immunity 

V N L 


0.8 

5 

15 

- 

- 

1.5 

2.25 

- 

1.4 

-- 

- 



(Any Input) 


1 

10 

3 

- 

- 

3 

4.5 

- 

2 9 

- 

- 


3.12 

For Definition, 

See Appendix 

VNH 


4.2 

5 

1.4 

- 

- 

1.5 

2.25 

- 

1.5 

- 

- 

y 


9 

10 

2.9 

- 

- 

3 

4.5 

- 

3 

- 

- 



Output Drive Current: 

idn 


0.5 

5 

0.155 

- 

- 

0.125 

0.25 

- 

0.085 

- 

- 


3.3 

N-Channel 


,0.5 

10 

0.31 

- 

- 

0.25 

0.5 

- 

0.175 

- 

- 


3.5* 


idp 


4.5 

5 

-0.125 

- 

- 

-0.1 

-0.15 

- 

-0.07 

- 

- 

mA 

3.4 

P-Channel 


9.5 

10 

-0.25 

- 

- 

-0.2 

-0.3 

- 

-0.14 

- 

- 

3.6* 

Input Current 

ll 


- 

- 

- 

- 

10 

- 

- 

- 


pA 

- 


♦See Appendix. 




Fig.3.3—Typ. n-channel drain characteristics. Fig.3.4—Typ. p-channel drain characteristics. 


40 






File No. 479 


CD4006A 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < V| < V DD ) 

(Recommended DC Supply Voltage (Vqq - Vss) 3 to 15 V) 






LIMITS 


CHARAC 















TERISTIC 

CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 




CD4006AE 




UNITS 

CURVES 

8i TEST 




v 0 

VDD 

-40°C 

25°C 

85° C 


CIRCUITS 




Volts 

Volts 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 


Fig. No. 

Quiescent Device 

Current 



5 

- 

- 

5 

- 

0.03 

5 

- 

- 

70 

pA 

3.11 



10 

- 

- 

10 

- 

0.05 

10 

- 

- 

140 

Quiescent Device 

Pd 


5 

_ 


25 

- 

0.15 

25 

- 

- 

350 



Dissipation/Package 


10 

- 

- 

100 

- 

0.5 

100 

- 

- 

1400 



Output Voltage: 

V 0L 


5 

_ 

_ 

0.01 

- 

0 

0.01 

- 

- 

0.05 



Low- Level 


10 

- 

- 

0.01 


0 

0.01 


- 

0.05 



High-Level 

V 0H 


5 

4 99 

- 

- 

4.99 

5 

- 

4 95 

- 

- 




10 

9.99 

- 

- 

9.99 

10 

- 

9.95 





Noise Immunity 

VNL 


0.8 

5 

15 

- 

- 

1.5 

2 25 

- 

14 

- 

- 

v 


(Any Input) 


1 

10 

3 

- 

- 

3 

4.5 


2.9 


~ 


3.12 

For Definition, 

See Appendix 

VNH 


4.2 

5 

14 

- 

- 

1.5 

2.25 

- 

1.5 

- 

- 

v 


9 

10 

2.9 


- 

3 

4.5 

- 

3 

- 

~ 



Output Drive Current: 

i d n 


0.5 

5 

0.072 

- 

- 

0.06 

0.25 


0.048 

- 

- 

mA 

3.3 

N-Channel 


,0.5 

10 

0 15 


- 

0.125 

0.5 


0.10 

_ 

~ 

3.5* 


l D p 


4.5 

5 

-0.06 

- 

- 

-0.05 

-0.15 

- 

-0.04 

- 

- 

m A 

3.4 

P-Channel 


9.5 

10 

-0.12 

- 

- 

-0.1 

-0.3 

- 

-0.08 

- 



3.6* 

Input Current 

ll 


- 

- 

- 

- 

10 

- 

" 



pA 

- 


*See Appendix. 


1 3C D 40( 


SATE -TO -SOURCE VOLTS 

(VGS)=I5 

HnUmm 


iiiiliiiiiiiiliiiiiiiiiii i 

illlll | 
Illllillllllllll i 

::::: 

iiiii 

::::: 

Hi 

iiiii 


:: ::::::::::::::: 
Ignllllll 

sHSslillllinilli: 

j^jjSgjjjjjjjjjg ■ 
iifiitnimnn^^ 1 

JHc: 

iiiii 

Hi 


0 5 io 15 

DRAIN -TO- SOURCE VOLTS (Vqs> 

92CS-I7840 


Fig.3.5—Min. n-channel drain characteristics. 


DRAIN -TO- SOURCE VOLTS (Vqs) 

-15 HO -5 0 


H 1 

11 HI 

MKftS 15555 

HI:: 

Illlll IIIII 

siiilllEiji 

jSiiilllllSlis 

illllliyil 

lllljlisislilil 

ill 

ill 

HI 

i 

illlll 

l! 

ill!!! 

is::: 

:::::::: 

11 

11 

••222222 

m 

11 

SiiSiig 

!ilf 

III 

p|I 

-0.5 

a 

-1 ~ 
CO 
UJ 
or 

UJ 

CL 

-1.5 | 

_i 

5 

-2 z 
< 
m 

-2.5 

-3 

CD4006AD.CD4006AK 

CD4006AE-- 

- 1 




■ 

III U 

:::::::::::: 

iiiiiiiiiiii 

mi 

ill 


A 

§■ 


92CS-1 7842 

Fig.3.6—Min. p-channel drain characteristics. 


41 








CD4006A File No. 479 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, C L = 15 pF,and input rise and fall times =20 ns except t r CL,tfCL 
Typipal Temperature Coefficient for all values of Vqq = 0.3%/°C (See Appendix for Waveforms) 


CHARACTERISTICS 

SYMBOLS 


LIMITS 


CHARAC- 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 
Fig. No. 

TEST 

CONDITIONS 

CD4006AD, CD4006AK 
CD4006AF 

CD4006AE 

B 


V DD 

(Volts) 







Propagation Delay Time 

tPHL= 

tPLH 


5 



lil 



500 


D 

10 

- 

125 

200 


125 

250 

Transition Time 

tTHL= 

tTLH 


5 

- 

250 

400 

- 

250 

500 

1 

3.8 

10 


125 

200 


125 

250 

Minimum Clock 

Pulse Width 

*\NL = 

" *WH 


5 


200 

500 

- 

200 

830 

ns 

- 

10 

- 

100 

200 

- 

100 

250 

Clock 

Rise & Fall Time 

*rCL = 

tfCL* 


5 

- 

- 

15 

- 

- 

15 

ps 

- 

10 

- 


5 


- 

5 

Set-Up Time 



5 

- 

50 

80 

- 

50 

100 

ns 

- 

10 

- 

25 

40 

- 

25 

50 

Maximum Clock 

Frequency 

fCL 


5 

1 

2.5 

- 

0.6 

2.5 

- 

MHz 

3.10 

10 

2.5 

5 

- 

2 

5 

- 

Input Capacitance 

C| 

Data Input 

Clock Input 

- 

5 

30 

- 

- 

5 

30 

- 

pF 

- 


* If more than one unit is cascaded tfCL should be made less than or 
equal to the sum of the fixed propagation delay at 15pF and the 
transition time of the output driving stage for the estimated capac- 
itive load. 




Fig.3.7-Typ. propagation delay time vs. Ci_. 


Fig.3.8-Typ. transition time vs. C(_. 


42 








POWER DISSIPATION /STAGE (P D ) 







File No. 479 


Digital Integrated Circuits 

Monolithic Silicon 

CD4007AD, CD4007AF 
CD4007AE, CD4007AK 



7 4 9 


COS/MOS Dual Complementary 
Pair Plus Inverter 

Special Features 

■ Medium speed operation. . . tpHL = *PLH = 20 ns (typ.) at C|_ = 15 pF 

■ Low "high"- and "low"-output impedance 500 £2 (typ.) 

at V DD - Vss = 10 V 


Terminal No. 14 = Vqq 
T erminal No. 7 = Vgs 


Applications 

■ Extremely high-input impedance amplifiers; inverters, shapers, linear 
amplifiers, threshold detector 


CD4007A types are comprised of three N-Channel and three 
P-Channel enhancement-type MOS transistors. The transistor 
elements are accessible through the package terminals to 
provide a convenient means for constructing the various 
typical circuits shown in Fig.4.1. 


More complex functions are possible using multiple packages. 
Numbers shown in parentheses indicate terminals that are 
connected together to form the various configurations listed. 
For proper operation Vgg — V| < Vqq must be satisfied. 


a) Triple Inverters 




13); 


92CS- 15350 


b) 3-Input NOR Gate v. 

92CS- 15349 

(13,2); (1,11); 
(12,5,8); (7,4,9) 

c) 3-lnput NAND Gate c O I ~N 

(1,12,13); (2,14,11); 
(4,8); (5,9) 

92CS-I5340 



d) Tree (Relay) Logic V 0D 

(-*— « 

1 1 Hr 


(13,12,5); (4,9,8); 
(14,2); (1,11) . 



'ALL P-UNIT SUBSTRATES 
ARE CONNECTED TO V 0 0 
ALL N-UNIT SUBSTRATES 
ARE CONNECTED TO V ss 


OOUT 


OUT (V 0 0>*C*AB 
OUT (Vgg)» CA + CB 


e) High Sink-Current Driver 


(6,3,10); (8,5, 12), 
(11,14); (7,4,9) 


©— 4 


'DU 


(OPTIONAL V 00 PULL-UP) 






V5S 92CS- 15330 


f) High Source-Current Driver 

(6,3,10); (13,1,12) v oo 

(14,2,11); (7,9) | 1 

TEt 


U 


^ ' 


OPTIONAL v ss pull-down) 

92CS-I5327 


Fig. 4. 1— Sample COS/MOS logic circuit arrangements using type CD4007A. 


44 


9-74 






CD4007A 


File No. 479 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < V, <V DD ) 

(Recommended DC Supply Voltage (Vqq — Vgg) 3 to 15 V) 


CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 

LIMITS 

UNITS 

CHARAC 

TERISTIC 

CURVES 

& TEST 
CIRCUITS 

Fig. No. 

CD4007AD, CD4007AK , CD4007AF 


Vo 

Volts 

V DD 

Volts 

-55°C 

25° C 

125°C 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Quiescent Device 

Current 

'L 


5 

- 

- 

0.05 

- 

0.001 

0.05 

- 

- 

3 

pA 

4.15 

10 

- 

- 

0.1 

- 

0.001 

0.1 

- 

- 

6 

Quiescent Device 
Dissipation/Package 

PD 


5 

_ 

- 

0.25 

- 

0.005 

0.25 

_ 

_ 

15 

pW 


10 

- 

" 

1 

- 

0.01 

1 



60 

Output Voltage: 

Low-Level 

V 0 L 


5 

- 

- 

0.01 

_ 

0 

0.01 

_ 

_ 

0.05 

V 

4.2 

4.3 

4.4 

1.5 

4.6 

10 

- 

- 

0.01 

- 

0~ 1 

0.01 

" 

“ 

0.05 

High-Level 

VOH 


5 

4 99 

- 

- 

4.99 ! 5 

- 

4.95 

j 

V 

10 

9.99 

- 

- 

9.99 10 ! - 

9.95 

" i ' 

Noise Immunity 

(Any Input) 

For Definition. 

See Appendix 

v NL 


3.6 

5 

1.5 

- 

- 

1.5 

2.25 1 - 

1.4 


V 

4.16 

7.2 

10 

3 

- 

- 

3 

« | - 

2.9 

_ 1 _ 

1 

Vnh 

0.95 

5 

1.4 

- 

- 

1.5 

2.25 | - 

1.5 


V 

2.9 

10 

2.9 

- 

- 

3 

r 4.5 

r- 

3 


Output Drive Current: 

N-Channel 

ID n 

V|=Vqd 

0.4* 

5 

0.75 

_ 

- 

0.6 

1 

- 

0.4 


- 

mA 

4 - 7 ♦ 

4.9 

0.5 

10 

1.6 

- 

- 

1.3 

2.5 

- 

0.95 

- 

- 

P-Channel 

idP 

8 

> 

> 

2.5^ 

5 

- 1.75 

- 

- 

-1.4 

-4 

- 

-1 


- 

4.S 

4.10 W 

9.5 

10 

- 1.35 

- 

_ 

- 1.1 

-2.5 


■ 0.75 

- 

- 

Input Current 



- 

- 

- 

- 

10 


- 

- 

- 

pA 

- 


A Maximum noise-free low-level Bipolar output voltage. 
"^Minimum noise-free high-level Bipolar output voltage. 


♦ See Appendix. 


g) High Sink- and Source-Current Driver 

(6,3,10); (14,2,11); 



h) Dual Bi-Directional Transmission Gating 



Fig.4. 1— Sample COS/MOS logic circuit arrangements using type CD4007A. 


45 






CD4007A 


File No. 479 


STATIC ELECTRICAL CHARACTERISTICS (All inputs 

(Recommended DC Supply Voltage (Vpp — V§s). 


V SS < v,<v DD ) 
3 to 15 V) 


CHARACTERISTIC 

SYMBOL 

Quiescent Device 

Current 

'L 

Quiescent Device 

D issi pation /Package 

p D 


TEST 

CONDITIONS 


LIMITS 


CD4007AE 





















File No. 479 


CD4007A 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, C L = 15 pF and input rise and fall times = 20 r 
Typical Temperature Coefficient for all values of Vqq = 0.3 %/°C (See Appendix for Waveforms) 


CHARACTERISTICS 




CD4007AD.CD4007AK 

CD4007AF 

CD4007AE 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max 


UNITS 

CHARAC- 

TERISTIC 

CURVES 
& TEST 

CIRCUITS 
•Fig. No. 

ns 

4.11 

ns 

4.13 
















e: 



]■■■ 


msmmmz 

BBEBgBs 



Fig.4.6—Typ. current and voltage transfer 
characteristics for inverter. 


DRAIN - TO - SOURCE VOLTS (V DS ) g 
Fig.4.7—Typ. n-channel drain characteristics. 


DRAIN - TO - SOURCE VOLTS (V D e) 


sssss 

{5S555:g555555555555^gr5 


■ 

ik>S 

■ 

■ 

j 

■ 

■ 

■ 

■ 

■ 

■ 

■ 

s 

■ 

■ 

■ 

HQMVSBKiHBHb ■ 

■■■■■1 

mm 

k'lim 

■.mil 

■^taai 

■■■wv^ 


■■■5 

PPW 


AMBIENT TEMPERATURE (T A ) = 25°C 

TYPICAL TEMPERATURE COEFFICIENT FOR I D * -0.3% 


■■ 

■■ 

■■ 

■■ 

■■ 

■■■ 

■■■ 

hi 

■M 

irfi Si 

■■■ ■■ 

■■■ ■■ 
■■■ ■■ 

pa 

85 5555 

55 5555 

ill 


555551 

555551 

■■ 

■■ 

■■ 

■■ 

!■■ 

■ ■■ 
IN 

■■■ 

■■■ 

uni 

UUU 

55 ” 55 

■■ ■■■■ 

■■ ■■■■11 

fart 

■■ ■■■■■ 


■■■■■ 

■■■■■ 

55555 

iisii 

■r, 

■'i 


■58 

H! 38 

■■ ■ ■■■■ 

555 

55555 

55555 

r/raara 

■■■ 





iiiail 

rmr.au a 
'ir.mumz 
ranuui 

lihrf 

■■■■ 

\ZZf[ 

■■■ ^sj 

■■■ ■■ 
■■■ ■■ 

■■■ ■■ 

■■ ■IIH 

■■ ■BB!*! 

■■ amm 


IB 




VTJ, 



s: 



■ 338 ' 


■■■■58 


■■ESS! 






TRANSITION TIME (t 



19 






File No. 479 


Digital Integrated Circuits 

Monolithic Silicon 

CD4008AD, CD4008AF 
CD4008AE, CD4008AK 



COS/MOS Four- Bit Full Adder 

With Parallel Carry Out 

Special Features 

■ MSI complexity on a single chip 4 Sum Outputs plus parallel 

Carry-Output 

■ High speed operation Carry-In to Carry-Out delay, tpnL» 

tpLH = 45 ns at C|_ = 15 pF 

Applications 

■ Binary addition/arithmetic units 


TRUTH TABLE 


CD4008A types consist of four full-adder stages with fast 
look-ahead carry provision from stage to stage. Circuitry is 
included to provide a fast "parallel-carry-out” bit to permit 
high-speed operation in arithmetic sections using several 
CD4008A's. CD4008A inputs include the four sets of bits to 
be added, Ai to A4 and Bi to B4, in addition to the "Carry 
In" bit from a previous section. CD4008A outputs include 
the four sum bits, Si and S4, in addition to the high-speed 
"parallel-cary-out" which may be utilized at a succeeding 
CD4008A section. 


AaO 1 


83 ^ 
A 3 0 1 


B 2CF~ 

A 2 o~ 


B|0— 

AlO 1 


(CARRY-OUT) 


OCq 


SUM 

=E5 






SUM 


CjO- 
(CARRY- IN) 

TERM INAL No. 16* V DD , TERMINAL N0 8 * V ss 

92CS-I5842 


Aj 

Bi 

Cj 

Co 

SUM 

0 

0 

0 

0 

0 

1 . 

0 

0 

0 

1 

0 

1 

0 

0 

1 

1 i 

1 

0 

1 

0 

0 

0 

1 

0 

1 

1 ;! 

0 

1 

1 

0 

0 

1 

1 

1 

0 

1 


A 1 3-16 
B|3-I6< 


a 9 -I 2 J 


a 5-8 

B5-8 


A 1-4 
B 1-4 


| Co * tpdlS r Co)^3tp d (Cj-C 0 255 
S|3- 


r — — 


1 

' 

— E 

CD4008D 



n 

Cj 



J 

Co 

tpd 


r 



jzg 

CD4008D 

= j 



C, 



i 

£o 

tpd 


tpd tSj— C q) 4- 2 tpd (Cj -C 0 )+ tpd (Cj-So)=530 


•pd^i-Co^^pdtCj-Co)* 


S5-8 tpd ( Sj-C 0 )4 » pd (Cj-S 0 ) s 445 


t Dd tSj-C o )*l20 


CD4008DLZ r s 1-4 tpd (Sj-S 0 )*325 


v ss 

NOTES 

ALL V a"B" INPUT BITS OCCUR AT t*0 
ALL SUMS SETTLED AT t * 530ns 

CL * 15 pF, TA* + 25*C,V D D-Vss ,+ ,0V 


Fig. 5. 1— Logic diagram for type CD4008A. 


Fig. 5. 2— T ypicai speed characteristics of a 1 6-bi t adder. 


50 


9-74 










File No. 479 


CD4008A 


STATIC ELECTRICAL CHARACTERISTICS (All inputs 

(Recommended DC Supply Voltage (Vqq — Vgg) 


Vss< v I < V DD) 
. . . . 3 to 15 V) 


CHARAC 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 





Carry 

Output 

4.5 

5 

-0.31 

- 

PChannel 

l n P 


9.5 

10 

>0.93 

- 


u 

Sum 

2 

s 

0 012 

- 




7 

|10 

-0.185 

- 

Input Current 

•l 



- 



LOAD CAPACITANCE (C L ) — pF 


LOAD CAPACITANCE (C L )— pF 


Fig. 5.3— Sum-in to carry out propagation 
delay time vs. C[_. 


Fig. 5. 4— Sum-in or carry -in to sum-out propa 
gation delay time vs. C/_. 

















CD4008A 


File No. 479 


STATIC ELECTRICAL CHARACTERISTICS (All inputs 

(Recommended DC Supply Voltage (Vpp — Vgg) 


V SS <V l < V DD ) 
3 to 15 V) 


Quiescent Device 
Current 


Noise Immunity 
(Any Input) 
For Definition, 
See Appendix 


Output Drive 
Current 


TEST 

CONDITIONS 


mi 

ElHUHElHmi 

m 

EH 

UiiilBBBHlSIEIBH 


M 

OHE9QHH 

131 

1 

BSlBBIElBSilHiHi 

EHHIEIISflBm 

BE 

E9 

1 

IHHiEIESIHiEi 

EKHEHHEEIBK 

E3 

E 

^eikbi EB^^UEI 

El 

mm 

wmmmmmwmmKrmwm 

Bl 

El 

HHKXSZlHiEMI 

PE 

n 

bhehhh 

El 

HE 

ElEIKBBiBBHi 

El 

n 

mmmrnmm 


El 

BHHKQiHEEE8 

B 

HI 

BimSEEBIBBi 

El 


BBS ESI BUSIES 

Hi 


BQ 9EIS3 I 

El 

E 

bioebeiesiei 

Bl 

■ 

EBUSBHIEESEB 

HE 

mi 

BHQBEMHiIEHi 

HE 

Bl 

■■■!«« 

| 


CHARAC 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 
Fig. No. 


♦ See Appendix 


» AMBIENT TEMPERATURE (T A ) = 25 # C 
TYPICAL TEMPERATURE COEFFICIENT 
^300 F0R ALL VALUES OF V 00 = 0.3% /»C 


::::: 


mmmmmmmmmK 


■■■■■■■■ 


■■■■■■■■ 

■■■■■■■■ 

■■■■■■■■ 


10 20 30 40 50 60 70 80 

LOAD CAPACITANCE (C L )— pF 


AMBIENT TEMPERATURE t T A I «25°C 
LOAD CAPACITANCE (C L ) - 15 pF 


s: 


|£ I00f-|CD4008AD,CD4008AK 


■■■■■■■■ 


■■■■■■■■ 


■■■■■■■■■■■MB 


■■■■■■■■■■■■■■I 


■■■■■■■■■■■■■I 


isssssl 


■■■■■I 

■■■■■I 




SUPPLY VOLTS (V 0D ) 


Fig. 5. 5— Carry-in to carry-out propagation 
delay time vs. C/ . 


Fig.5.6—Max. propagation delay time 
for carry -in to carry-out. 















File No. 479 


CD4008A 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, 
Typical Temperature Coefficient for all values of Vqq = 0.3%/ 


C[_ = 15 pF and input rise and fall times - 20 ns 
^C. (See Appendix for Waveforms) 


CHARACTERISTICS SYMBOLS 


Propagation Delay Time: 
At Sum Outputs; 

From Sum Input 


TEST 

CONDITIONS 


CD4008AD, CD4008AK 
CD4008AF 


Min. Typ. Max. Min. | Typ. | Max 



From Carry Input 

At Carry Output; 
From Sum Input 

From Carry Input 

Transition Time: 

At Sum Outputs 

At Carry Output 
Input Capacitance 


I0 6 AMBIENT TEMPERATURE (T a ) = 25°C = 



INPUT FREQUENCY (f*) — kHz 



Fig. 5. 7— Typ. dissipation characteristics. 


Fig.5.8— Quiescent device current test circuit. 



Fig.5.9— Noise immunity test circuit. 









JU — TfLJJU LJ*UJL__ 







File No. 479 


Digital Integrated Circuits 

Monolithic Silicon 

CD4009A , CD4010A 

Types 



COS/MOS Hex Buffers/Converters 

Inverting Type: CD4009AD, CD4009AE, CD4009AK 
Non-Inverting Type: CD4010AD, CD4010AE, CD4010AK 

Special Features (Each Buffer) 

■ High current sinking capability 8 mA (min.) at Vql = 0.5 V and 

Vqd = + 10 V 

Applications 

■ COS/MOS to DTL/TTL hex converter ■ COS/MOS logic-level converter 

■ COS/MOS current "sink" or "source" driver ■ Multiplexer 1 to 6 or 6 to 1 


CAUTION: 

V CC VOLTAGE LEVEL MUST BE EQUAL TO OR LESS THAN 
V DD . FOR 10.5- TO 15-VOLT SUPPLIES, C L0 AD must be 
EQUAL TO OR LESS THAN 5000 pF. 


CD4009A types may be used as a hex COS/MOS inverter, a 
COS/MOS to DTLor TTL logic-level converter, or a COS/MOS 
current driver. 

The CD4049A and CD4050A are preferred Hex Buffer 
replacements for the CD4009A and CD4010A, respec- 
tively, in all applications except multiplexers. 


CD4010A types may be used as a COS/MOS to DTLor TTL 
hex converter or a COS/MOS current driver. 

Conversion ranges are from COS/MOS logic operating at +3 
V to +15 V supply levels to DTL or TTL logic operating at 
+3 V to +6 V supply levels. Conversion to logic output levels 
greater than +6 V is permitted providing Vcc(DTL/TTL) < 
V DD (COS/MOS). 



56 


9-74 






OUTPUT VOLTS (V 0 ) 


File No. 479 


CD4009A, CD4010A 



CONFIGURATION: 

HEX COS MOS TO DTL OR TTL 
CONVERTER (INVERTING) 
WIRING SCHEDULE: 

CONNECT V C C TO DTL OR 
TTL SUPPLY. 

CONNECT V DD TO COS MOS 
SUPPLY 


Fig.6.3-Schematic diagram tor types CD4009A 
1 of 6 identical stages. 



HEX COS MOS TO DTL OR TTL 
CONVERTER (NON-INVERTING) 
WIRING SCHEDULE 
CONNECT V CC TO DTL OR 
TTL SUPPLY 

CONNECT V DD TO COS MOS 
SUPPLY. 


Fig.6.4-Schematic diagram for types CD4010A. 
1 of 6 identical stages. 


AMBIENT TEMPERATURE (T A )»25°C: MAX 

M t imm i TT i ii M i n i m i— — min. 


V| . v 0 

o-{>-o 






INPUT VOLTS (V,) 


Fig.6.5—Min. & max. voltage transfer charac- 
teristics — CD4009A. 


Fig.6.6—Typ. voltage transfer characteristics 
as function of temp. — CD4009A. 


AMBIENT TEMPERATURE (T A )*25C 
COLLECTOR SUPPLY VOLTAGE (V C( 4 = 5V 
DRAIN SUPPLY VOLTAGE (V DD )= 5 V 




AMBIENT TEMPERATURE (T A ) = 25° C 
COLLECTOR SUPPLY VOLTS (V CC ) = + 5 : 
DRAIN SUPPLY VOLTS (V DD ) = ♦ 10 


V, O— £> — oV| 



Fig.6.7—Min. & max. voltage transfer charac- 
teristics (VqD ~ 5) — CD4010A. 


Fig.6.8—Min. & max. voltage transfer charac- 
teristics (Vq= 10) - CD4010A. 


57 






CD4009A, CD4010A File No. 479 

STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < V 1 < V DD ) 

(Recommended DC Supply Voltage (Vqq — Vgg) 3 to 15 V) 






LIMITS 


CHARAC 

CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 

CD4009AD, CD4009AK, CD4010AD, CD4010AK 


TERISTIC 
CURVES 
& TEST 




v 0 

V DD 

— 55°C 

25»C 

125°C 


CIRCUITS 




Volts 

Volts 



B.W 

■ 'MB 

EHW 

Ku39 

B.'.MB 

EB 

■zaa 


Fig. No. 

Quiescent Device 

mm 



D 

- 

- 


HBi 

iBEO 

KB 

- 

■ 




Current: 

Bi 



,0 

- 

- 

sa 

m 

KQ 

m 

- 

Bi 



Quiescent Device 

m 



D 

- 

- 

■a 

m 

EI 3 

BI 

- 

- 

100 



Dissipation/Package 



,0 

- 

- 

5 

m 

wm 

5 

- 

- 

300 


Output Voltage: 




H 

Bi 

- 

m 

- 



fljl 

■ 




Low-Level 



10 

B 

- 


- 



m 

B 



6.5 

High-Level 

VOH 



5 

4.99 

_ 


be 

5 

- 

HM 

- 



6*10 



EU 

BMI 


- 


10 

_ 

BS9 

_ 

_ 



Noise Immunity 4 
(Any Input) 



B 

■ 

■ 

■ 


■ 


B 

■ 

■ 

B 



CD4009A 



B 

HI 

H 



■ 

m 


m 

■ 

■ 




V NL 



■ 

■ 



■ 



1.4 





CD4010A 




H 

■ 



m 

n 


Bi 

B 

B 


6.23 





■ 

m 



m 





B 

V 


CD4009A 



B 

m 

H 



H 

m 

B 


■ 

B 




V NH 


m 

m 

H 



H 


■ 


fl 

■ 



CD4010A 



m 

B 

B 

_ 

_ 

■ 

B 

B 

■ 

B 

B 



Output Drive Current: 

idn 


oa 

5 


- 

- 

3 

« 

- 

2.1 

rz 

- 



N-Channel 



El 

■ 

- 

- 

KB 

■B 

- 

m 

EM. 

- 


6.13 * 

P-Channel 

IdP 



m 

o 

jf§|| 

- 


m 


m 


- 

mA 



hub 

El 

B3 

- 

- 


m 

- 

EB 

B 

- 

♦ 

Input Current 

ll 


_ 

_ 

_ 

- 

~ 

_ 

10 


_ 

e: 

- 

pA 

* 


♦ See Appendix. 



Fig.6.9—Min. & max. voltage transfer charac- 
teristics (V DD = 15) - CD4010A. 



0LLECT0R SUPPLY VOLTS 

(Vrr) * ♦ 5 (T A ) +125° C 

5 : 

4 : 

1 

I 

# 

■jjjta 

"o 

> 

jp 

ii* 

EijSi 







i 3 - 


||i 

| m 


Q_ 

i 2 j 

1 j 

I 

1 


81 1 . 


0 2 4 6 8 10 12 14 


INPUT VOLTS (V|) 92SS4198R1 

Fig.6.10—Typ. voltage transfer characteristics 
as a function of temperature — 

CD4010A. 


58 














File No. 479 


CD4009A, CD4010A 


STATIC ELECTRICAL CHARACTERISTICS (All inputs 

(Recommended DC Supply Voltage (Vpp — V55). 










CD4009A, CD4010A 


File No. 479 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, C L = 15 pF, and input rise and fall times = 20 ns 
Typical Temperature Coefficient for all values of Vqq = 0.3%/°C. (See Appendix for Waveforms) 


CHARACTERISTIC 

SYMBOL 


LIMITS 

UNITS 

CHARAC- 

TERISTIC 

CURVES 
& TEST 

CIRCUITS 
Fig. No. 

TEST 

CONDITIONS 

CD4009AD, CD4009AK 
CD4010AD.CD4010AK 

CD4009AE 

CD4010AE 


Hsa 

[QQQ] 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Propagation Delay Time: 
High-to-Low Level 

tpHL 

Vcc =VDD 

■3 

- 

15 

55 

- 

15 

70 


6.14 

10 

- 

10 

30 

- 

10 

40 

v D d= 10V 
Vcc= 5V 

■ 

■ 



■ 


35 

Low-to-High Level 


VCC=VDD 


Hi 


a 





6.15 

,0 

- 

25 

55 


25 

70 


■ 

■ 



a 



Transition Time: 

High-to-Low Level 



5 

- 

20 

HI 


ESI 

HI 


6.18 

10 

- 

16 


El 

■a 

m 

Low-to-High Level 

tTLH 

Vcc = V DD 

5 

- 

80 

125 


80 

160 

ns 

6.19 

10 

- 

50 

100 

- 

50 

120 

Input Capacitance 
(Any Input) 

C| 

CD4009A 


- 

15 

- 

- 

15 

- 

pF 

H 

CD4010A 


- 

5 

- 


5 

- 



Fig. 6. 13— Min. n-channel drain characteristics. 



LOAD CAPACITANCE IC L >— pF 


Fig. 6. 14—Typ. high-to-low level propagation 
delay time vs. C(_ - CD4009A, 
CD4010A. 


61 




























File No. 479 


Digital Integrated Circuits 

Monolithic Silicon 

CD4011A, CD4012 A,CD4023A 



COS MOS NAND Gates 
(Positive Logic) 


Quad 2 Input • • • CD401 1 AD, CD401 1 AE, CD401 1 AF, CD401 1 AK 
Dual 4 Input . • • CD4012AD, CD4012AE, CD4012AF, CD4012AK 
Triple 3 Input • • • CD4023AD, CD4023AE, CD4023AF, CD4023AK 


Special Features 

■ Medium speed operation tPHL = tPLH = 25 ns (typ.) 

atCL=15pF 

a Low “high"- and ''low''-level output impedance 400 and 800H (typ.) 

respectively at Vqd — Vgg = 10 V 


The combination of these devices and the RCA NOR 
positive logic gate types CD4000A, CD4001A, CD4002A, 
md CD4025A can account for appreciable package-count 
avings in various logic function configurations. 



Fig. 7. 1 - Schematic diagram for type CD4012A. 





9-74 


63 





CD4011A, CD4012A, CD4023A . 


File No. 479 


STATIC ELECTRICAL CHARACTERISTICS (All inputs Vss<V,<V DD ) 

(Recommended DC Supply Voltage (Vqq — Vgg) 3 to 15 V) 
















File No. 479 


CD4011A, CD4012A, CD4023A 


STATIC ELECTRICAL CHARACTERISTICS (All inputs 

(Recommended DC Supply Voltage (Vqq — V 55) 


Vss<V,<V DD ) 
3 to 15 V) 


Quiescent Device 
Current 


Input Current 


♦ See Append i) 


SYMBOL 

TEST 

CONDITIONS 


Vo 

v D d 


Volts 

Volts 

ll 


5 

*L 


10 

Pr> 


5 



10 




, Hsupply VOLTS <v do ) « 15 


AMBIENT TEMPERATURE 
(Ta) * 25*C 



> 10 12.5 15 

INPUT VOLTS (V T ) 


10 12.5 I 

INPUT VOLTS (V x ) 


Fig. 7.4— Min. & max. voltage transfer charac- 
teristics. 


Fig.7.5-Typ. voltage transfer characteristics 
as a function of temperature. 


65 














CD4011A, CD4012A, CD4023A 


File No. 479 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, C L = 15 pF, and input rise and fall times = 20 ns 
Typical Temperature Coefficient for all values of Vqq = 0.3 %/°C (See Appendix for Waveforms) 


CHARACTERISTICS 

SYMBOLS 

Propagation Delay Time: 
Low-to-High Level 

tPLH 


TEST 

CONDITIONS 


CD4011AD, AF, AK 
, CD4012AD, AF, AK 
i CD4023AD, AF, AK 


CD4011AE 

CD4012AE 

CD4023AE 


V DD 

(Volts) Min. Typ. Max. 



















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rdn^mui 

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TRANSITION TIME (t THL ) -nt I I TRANSITION TIME <t TLH ) 


CD4011A, CD4012A, CD4023A 


File No. 479 


AMBIENT TEMPERATURE (T A ) « 25°C 
TYPICAL TEMPERATURE COEFFICIENT 
: 300 FOR ALL VALUES OF V DD «0.3%/ # C : 


AMBIENT TEMPERATURE (T A )*25 # C 
„ TYPICAL TEMPERATURE COEFFICIENT FOR F 

f 300 ALL VALUES OF V DD «0.3%/°C 



LOAD CAPACITANCE (C L ) - pF 


SUPPLY VOLTS (V DD ) 


Fig.7.18-Typ. high-to-low level transition 
time vs. C[_ — CD4012A. 


Fig.7. 19—Typ. propagation delay time vs. 
v nr> 







File No. 479 


CD4011A, CD4012A, CD4023A 



Fig.7.20—Typ. dissipation characteristics. 



INPUTS 2 2,6,9,13,14 1,5,7,8,12 

92CS-20737 

Fig. 7.21— Quiescent device current 
test circuit for CA401 1 A. 




Fig. 7. 22-Noise-immuni ty test 
circuit for CD4011A. 


Fig. 7. 23— Quiescent device current 
test circuit for CD4012A. 


Fig.7.24— Noise-immunity test 
circuit for CD4012A. 



92CS-2074I 


Fig. 7. 25— Quiescent device current 
test circuit for CD4023A. 


5 V OR 10 V 



Fig.7.26-Noise-immunity test 
circuit for CD4023A. 


69 






File No. 479 


Digital Integrated Circuits 

Monolithic Silicon 

CD4013AD, CD4013AF 
CD4013AE, CD4013AK 


Dual 'D’-Type Flip-Flop 

With Set- Reset Capability 

Special Features 

■ Static flip-flop operation retains state indefinitely with clock level 

either "high" or "low" 

■ Medium speed operation 10 MHz (typ.) clock toggle rate at 

VDD - Vss = 10 V 

■ Low "high"- and "low" output impedance 40012 and 20012, 

respectively at Vdd — V SS ~ 1° V 

Applications 

■ Registers, counters, control circuits 

CD4013A types consist of two identical, independent toggle applications. The logic level present at the "D" input 

data-type flip-flops. Each flip-flop has independent data, set, is transferred to the Q output during the positive-going 

reset, and clock inputs and "Q" and "Q" outputs. These transition of the clock pulse. Setting or resetting is inde- 
devices can be used for shift register applications, and, by pendent of the clock and is accomplished by a high level on 

connecting "Q" output to the data input, for counter and the set or reset line, respectively. 




TRUTH TABLE 



* = LEVEL CHANGE 

X = DON'T CARE CASE 
** s FF1/FF2 TERMINAL ASSIGNMENTS 


TERMINAL 14 - V DD 
TERMINAL 7 = GND 

Fig. 8. 1— Logic diagram and truth table (one of two identical flip-flops). 


92SS-438G 


70 


10-73 









CD4013A File No. 479 

STATIC ELECTRICAL CHARACTERISTICS (All inputs Vss< V, < V DD ) 

(Recommended DC Supply Voltage (Vpp — Vgsl 3 to 15 V) 







LIMITS 


CHARAC 

CHARACTERISTIC 

SYMBOL 

TEST 

CONDITlOf 

IS 

CD4013AD, CD4013AK, CD4013AF 

UNITS 

TERISTIC 

CURVES 

& TEST 






V DD 

— 55°C 

25°C 

125°C 


CIRCUITS 




Volts 

Volts 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 


Fig. No. 

Quiescent Device 




5 

- 

- 

1 

- 

0.005 

1 

- 

- 

60 

pA 

8.9 

Current 

■l 



IQ 

- 

- 

2 

- 

0.005 

2 

- 

- 

120 


Quiescent Device 

Pd 



5 

_ 

- 

5 

- 

0.025 

5 

- 

- 

300 


8.7 

Dissipation/Package 



□ 

- 

- 

20 

- 

0.05 


- 

Hi 


HKH 

Output Voltage: 

VOL 



5 

_ 

- 

SI 

_ 

0 

AM 

- 

m 

09 


■ ■ 

Low Level 



10 

- 

- 


- 

0 


Wm 

S 




High-Level 

VOH 



■3 


- 

. - 


5 

~ 


- 

- 





□ 

09 

- 

- 

9.99 

IB 

- 


- 

- 


■ 

Noise Immunity 

VNL 


0.8 

LL_ 

WM 

bh 

- 

19 


- 

a 

- 

- 



(Any Input) 


|Q 

Bl 

m 

- 

- 

3 

KB 

- 

EB 

- 

n 


For Definition, 

See Appendix 

vnh 


m 

n 

m 

- 

- 

IB 


- 

1.5 

- 

- 


mi 


EB 

Bl 


- 

- 

3 

IB 

- 

3 

- 

- 


Output Drive Current: 

| 



m 

03 

- 

- 

EB 

1 


j||f | 

- 

- 


■ ■ 

N -Channel 




Q 

BEE1 

- 

- 


EB 


IS 

- 

- 


■C H 





* 

09 

- 

- 


ea 

- 

mm 

- 

- 






D 

m 

- 

- 


EB 

- 


SC 

- 




•l 


_ 

- 

- 


,0 

- 


- 

- 

pA 

- 


♦See Appendix 



DRAIN - TO - SOURCE VOLTS (V D$ ) 



Fig.8.5—Min. n -channel drain characteristics. 


Fig.8.6—Min. p-channel drain characteristics. 


72 





File No. 479 CD4013A 

STATIC ELECTRICAL CHARACTERISTICS (All inputs V SS <V, <V DD I 

(Recommended DC Supply Voltage (Vqq — Vgg) 3 to 15 V) 







LIMITS 


CHARAC 

CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 

CD4013AE 

UNITS 

TERISTIC 

CURVES 

& TEST 




• 

Vo 

V DD 

— 40°C 

25°C 

85°C 


CIRCUITS 



L 

Volts 

Volts 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 


Fig. No. 

Quiescent Device 




5 

- 

- 

10 

- 

0.01 

10 

- 

- 

140 

pA 

8.9 

Current 

•l 



10 

- 

- 

20 

- 

0.02 

20 

- 

- 

280 


Quiescent Device 

Pd 



5 

- 

- 

50 

- 

0.05 

50 

- 

_ 

700 

pVV 

8.7 

Dissipation/Package 



10 

- 

- 

200 

- 

' 0.2 

200 

- 

- 

2800 

8.9 

Output Voltage: 

VOL 



5 

- 

- 

0.01 

- 

0 

0.01 

- 

- 

0.05 



Low- Level 



10 


- 

0.01 


0 

0.01 

- 

- 

0.05 



High-Level 

v OH 



5 

4.99 

- 

- 

4.99 

5 

- 

4.95 

- 






10 

9.99 

- 

- 

9.99 

10 

- 

9.95 

- 

" 

V 


Noise Immunity 

vnl 


05 

5 

1.5 

- 

- 

1.5 

2.25 

- 

1.4 

- 



8.10 

(Any Input) 


1.0 

10 

3 

- 


3 

4.5 


2.9 


" 


For Definition, 

See Appendix 

VNH 


4.2 

5 

1.4 

- 

- 

1.5 

2.25 

- 

1.5 

- 

- 


8.10 


9.0 

10 

2.9 

" ~ 


3 

4.5 


3 




Output Drive Current: 

IdN 


0.5 

5 

0.35 

- 

- 

0.3 

1 

- 

0.24 

- 

- 



N-Channel 


0.5 

10 

0.72 

- 

- 

0.6 

2.5 

- 

0.5 

- 

- 



P-Channel 

'DP 


4.5 

5 

-0 1 7 

- 

- 

-0.T4 

-0.5 

- 

-0.12 

- 

- 




9.5 

10 

-0.4 

- 

- 

-0.33 

-1.3 

- 

-0.27 

- 

- 



Input Current 

•l 


- 

- 

- 

- 

10 

- 


- 

” 

pA 

- 


♦See Appendix 


£ 

jS 0 4 

Q 

a. 

7 

y io 3 
> 

o 

tr. 

£ I0 2 
z 

2 

§ 

2 io 

o 

L 


= 

= 

sis 

■ mm 

SS 

= 

=j=: 

■ 

m 

m 

m 

A 

nr 




T 

r 



■ 

■ 

■i 

IB 

■ 

■l 


S3 



■ 

■ 

II 

Ill 

I 

II 

II 

■ 

II 

in 

i 

1 

1 

R 

S 

1! 

SB3 

III 




n 


■l 

H 


■i 

»■ 

■ 

i 

2 



EE3 

B 

■II 




SUPPLY VOLTS (V DD 

B SB 

i 

2 



EEB 


■II 









T 









zr 






z 

rai 


a 



■■■ 






L 



■ 


m 




US 


■■■ 

1 

i 

!j 



!! 

w 

\ 



\ 

S 

| 

I 

i 

jj 

i 

II 





r-M 





■ Ir 






■ 





— 

it 


2 

3 

{pr 

2 


IB 

- 

■ 

- 


- 

■ 

1- 

- 

■IS 


K 

Sil 

Ifii 

e 

»! 


2 

1 

IB 

B 

■ 

■ 


B 

■ 

IB 

B 

■II 

g 

m 

Si 

!9l 

15 

Wi 



1 

;■ 


■ 

■ 

■ 

B 

■ 

IB 

B 

«! 

r* 

me. 

er 

IKi 


mi 

i mm 


■ 

■ 


- 



- 


ss 

BBS 


SIS 

me 

m 

3 

rut 

Si 

l!2i 

!■ 

- 

■■ 

■1 

iB 

■ 

i 

iB 

■ 

■ 

L 

B 

■ 

■■ 

ii 

IB 

IB 

fl 

■II 

■II 


1 

_L 

IB 

m 

■1 

H 

_ 


IB 



■ 

■ 


jj 

n 


ID 


io 2 io 3 io 4 <0 5 I0 6 I0 7 

INPUT FREQUENCY (f.) — Hz 

92CS-I7802RI 



Fig.8.7—Typ. dissipation characteristics. Fig.8.8-Typ. dock frequency vs. Vqq. 


73 





CD4013A 


File No. 479 


DYNAMIC ELECTRICAL CHARACTERISTICS AT T A - 25°C, C L = 15 pF, and input rise and fall times = 20 ns except t r CL, tfCL 
(See Appendix for Waveforms) 

Typical Temperature Coefficient for all values of Vqq = 0.3%/°C 





LIMITS 


CHARAC- 

CHARACTERISTICS 

SYMBOLS 

TEST 

CONDITIONS 

CD401 3AD, CD401 3AK 

CD4013AE 

UNITS 

TERISTIC 

CURVES 

& TEST 




V DD 

(Volts) 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 


CIRCUITS 
Fig. No. 

CLOCKED OPERATION 

Propagation Delay Time: 

t PHL = 


5 

- 

o 

in 

300 


150 

350 

ns 


tPLH 


10 

- 

75 

110 

- 

75 

125 


Transition Time 

tTHL= 


5 

- 

75 

125 

- 

75 

150 

ns 


tTLH 


10 

- 

50 

70 

- 

50 

75 


Minimum Clock Pulse 

tWL = 


5 

- 

125 

200 

- 

125 

500 

ns 


Width 

tWH 


10 

- 

50 

80 


50 

100 


Clock Rise & 

#t rCL= 


5 

- 

- 

15 

- 

- 

15 

ps 


Fall Time 

tfCL 


10 


- 

5 

- 

- 

5 


Set-Up Time 



5 

- 

20 

40 


20 

50 

ns 




10 

- 

10 

20 

- 

10 

25 


Maximum Clock 

*CL 


5 

2.5 

4 

_ 

1 

4 

_ 

MHz 

8.8 

Frequency 



10 

7 

10 

- 

5 

10 

- 

Input Capacitance 

C| 

Any Input 

- 

5 

- 

i 

5 

1 

- 

pF 


SET & RESET OPERATION 



Propagation Delay Time: 

tPHL(R) = 


5 


175 

300 


175 

350 



tPLH(R) 


10 


75 

110 


75 

125 



Minimum Set and Reset 

tWH(S), 


5 


125 

250 


125 

500 

ns 


Pulse Widths 

%H(R) 


10 


50 

100 


50 

125 



* If more than one unit is cascaded in a parallel clocked operation, t r CL should be made less than or equal to the sum of the 
fixed propagation delay time at 15 pF and the transition time of the output driving stage for the estimated capacitive load. 


74 






File No. 479 



IOV 


Teit performed with 
the following sequence 
of "IV and "O's". 

C L D S R 

0 10 1 

0 0 11 

0 0 10 

10 10 


Fig. 8.9— Quiescent device current test circuit. 


CD4013A 



Fig. 8. 10— Noise immunity test circuit. 




75 





File No. 479 


Digital Integrated Circuits 

Monolithic Silicon 

CD4014AD, CD4014AF 
CD4014AE, CD4014AK 



COS/MOS 8- Stage 
Static Shift Register 

SYNCHRONOUS PARALLEL OR SERIAL INPUT/SERIAL OUTPUT 
Special Features 

■ Medium speed operation 5 MHz (typ.) clock rate at Vqd — V SS = 10 V 

■ Fully static operation 

■ MSI complexity on a single chip 8 master-slave flip-flops plus output 

buffering and control gating 

Applications 

■ Synchronous parallel input/serial output data queueing 

■ Parallel to serial data conversion ■ General purpose register 


CD4014A types are 8-stage parallel-input/serial output regis- 
ters having common Clock and Parallel/Serial Control inputs, 
a single Serial Data input, and individual parallel "Jam" 
inputs to each register stage. Each register stage is a D-type, 
master-slave flip-flop. In addition to an output from stage 8, 
"Q" outputs are also available from stages 6 and 7. 

Parallel as well as serial entry is made into the register 
synchronous with the positive clock line transition and under 
control of the Parallel/Serial Control input. When the 


Parallel/Serial Control input is "low", data is serially shifted 
into the 8-stage register synchronously with the positive 
transition of the clock line. When the Parallel/Serial Control 
input is "high", data is jammed into the 8-stage register via 
the parallel input lines and synchronous with the positive 
transition of the clock line. Register expansion using multiple 
CD4014A packages is permitted. 



Fig. 9. 1 — Logic block diagram. 


76 


10-73 










File No. 479 


CD4014A 


TRUTH TABLE 



X ♦ DON'T CARE CASE A = LEVEL CHANGE 




9.2— Schematic diagram — CD4014A. 


77 




CD4014A File No. 479 

STATIC ELECTRICAL CHARACTERISTICS (All inputs Vss < V | < V DD ) 

(Recommended DC Supply Voltage (Vqq — V 55) 3 to 15 V) 


CHARACTERISTIC SYMBOL 


Quiescent Device 
Current 


TEST 

CONDITIONS 

I v 0 [Vdd " 


LIMITS 

CD4014AD, CD4014AK, CD4014AF 


Volts Volts Min. Typ. Max. Min. Typ. Max. Min. Typ. I Max. 


CHARAC 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 


Quiescent Device 
Dissipation/Package p D 


Output Voltage. 
Low-Level 


1500 


High-Level 

v OH 

| 


10 

9.99 

- 

- 

9.99 

10 

- 

9.95 

Noise Immunity 



0.8 

5 

1.5 

- 

- 

1.5 

2.25 

- 

1.4 

(Any Input) 

'/nl 


1.0 

10 

3 

- 

- 

3 

4.5 

- 

2.9 

For Definition. 



4.2 

5 

1.4 

- 

- 

1.5 

2.25 

- 

1.5 


V NH 


9.0 

10 

2.9 

- 

- 

3 

4.5 


3 

Output Drive Current: 



0.5 

5 

0.15 

- 

- 

0.12 

0.3 

~ 

0.085 

N-Channel 

«dn 

i 


0.5 

10 

0.31 

- 

- 

0.25 

0.5 

- 

0.175 

P-Channel 

'D p 


4.5 

5 

-0.1 

- 

- 

-0.08 

-0.16 

- 

-0.055 




9.5 

10 

-0.25 

_ 

_ 

-0.20 

-0.44 

- 

-0.14 


j^lnput Current 
♦ See Appendix 



I0 6 AMBIENT TEMPERATURE (T A ) = 25°C 
ALTERNATING 
AND "l" PATTERN 



LOAD CAPACITANCE (C|_H5pF 

C L =50pF 


INPUT CLOCK FREQUENCY (f CL ) — kHz 

9! 

9.3 — Typ. dissipation characteristics. 


AMBIENT TEMPERATURE (T A )*25°C 
LOAD CAPACITANCE (C L ) = 15 pF 





*■■■■■■■■■■■■■■■■■■■■■■■■ 
■•■■■■■■■■■■■■■■■■■■■■■■a 
iBaaaaBBaaaaBBBaBaaBaaa 


SUPPLY VOLTS (V DD ) 
9.4 — Max. input dock frequency 





File No. 479 CD4014A 

STATIC ELECTRICAL CHARACTERISTICS (All inputs Vss^V^Vdd) 

(Recommended DC Supply Voltage (Vpp — V35) 3 to 15 V) 






LIMITS 


CHARAC 

CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 

CD4014AE 

UNITS 

TERISTIC 

CURVES 

& TEST 




Vo 

V DD 

-40°C 

25°C 

85°C 


CIRCUITS 




Volts 

Volts 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 


Fig. No. 

Quiescent Device 




5 

- 


50 

- 

0.5 

50 

- 

- 

700 

PA 

9.7 

Current 

■l 



10 

- 


100 

- 

1 

100 

- 

- 

1400 

Quiescent Device 

Pd 



5 

- 


250 

- 

2.5 

250 

- 

- 

3500 

pW 


Dissipation/Package 



10 

- 

- 

1000 

- 

10 

1000 

- 

- 

14000 


Output Voltage: 

v OL 



5 

- 

- 

0.01 

- 

0 

0.01 

- 

- 

0.05 



Low-Level 



10 

- 

- 

001 

- 

0 

0.01 

- 

- 

0.05 



High-Level 

VOH 



5 

4.99 

- 

- 

4.99 

5 

- 

4.95 

- 

- 





10 

9.99 


- 

9.99 

10 

- 

9.95 

- 

- 



Noise Immunity 

V NL 


0.8 

5 

1.5 


- 

1.5 

2.25 


1.4 


- 



(Any Input) 


1.0 

10 

3 



3 

4.5 


2.9 

- 



9.8 

For Definition, 

See Appendix 

vnh 


4.2 

5 

1.4 


- 

1.5 

2.25 

- 

1.5 

- 

- 



9.0 

10 

2.9 


- 

3 

4.5 


3 

- 

- 



Output Drive Current. 

idn 


0.5 

5 

0.072 

- 

- 

0.06 

0.3 

- 

0.05 


- 

mA 


N-Channel 


0.5 

10 

0.12 

- 

- 

0.1 

0.5 

- 

0.08 

- 

- 


P-Channel 

IdP 


4.5 

5 

-0.06 

- 

- 

-0.05 

-0.16 

- 

-0.04 

- 

- 


♦ 



9.5 

10 

-0.12 

- 

- 

-0.1 

-0.44 

- 

-0.08 

- 

- 



Input Current 

'« 


- 


- 

- 

10 



- 


pA 



A 

See Appendix 



92CS-I7807 

9.5 — Typ. propagation delay time vs. C L . 



9.6 — Typ. transition time vs. Cf_. 


79 



CD4014A File No. 479 

DYNAMIC ELECTRICAL CHARACTERISTICS at T^ = 25°C, C|_ = 15 pF, and input rise and fall times = 20 ns except t r CL, tfCL 
Typical Temperature Coefficient for all values of Vqq = 0.3%/°C. (See Appendix for Waveforms) 


CHARACTERISTICS 

SYMBOLS 


LIMITS 

UNITS 

CHARAC- 
TERISTIC 
CURVES 
& TEST 

CIRCUITS 
Fig. No. 

TEST 

CONDITIONS 

CD4014AD 

CD4014AK 

CD4014AF 

CD4014AE 




'9 







nn 


- 

300 

750 

- 

300 

1000 

ns 

331 

10 

- 

100 

225 

- 






5 

- 


300 

- 

mu 


ns 

9.6 


- 

75 

125 

- 

m 





5 

- 



- 

KBS 

IS 


- 

IB 

- 



- 


ms 



pip 

M 

- 

- 


- 

- 

■ 


- 


- 

- 


- 

- 

m 




5 

- 

100 

350 

- 

mi 

|Q3 



10 

- 


■a 

- 


mu 

Maximum Clock 

Frequency 

f CL 


5 

1 

2.5 

- 

0.6 

2.5 

- 

MHz 

- 

10 

3, 

5 

- 

2.5 

5 

- 

Input Capacitance 

C| 

ANY INPUT 

- 

5 

- 

- 

5 

- 

PF 

- 


If more than one unit is cascaded in a parallel clocked operation, 
t r CL should be made less than or equal to the sum of the fixed 
propagation delay time at 15pF and the transition' time of the 
output driving stage for the estimated capacitive load. 


10V 





Test performed with the following 
sequence of "1's" and "0's" 

Si S 2 S 3 S 4 S 5 

Don't 
Test 
Test 
Test 
Test 
Test 


0 1110 
1 0 0 0 0 
10 111 
1 0 0 0 1 


92CS- 17908 


9.8— Noise immunity test circuit. 


80 


9.7— Quiescent device current test circuit. 

















File No. 479 


Digital Integrated Circuits 

Monolithic Silicon 

CD4015AD, CD4015AF 
CD4015AE, CD4015AK 



COS MOS Dual 4 -Stage 

Static Shift Register 

With Serial Input/Parallel Output 
Special Features 

■ Medium speed operation 5 MHz (typ.) clock rate at Vqd — V§s = 10 V 

■ Fully static operation 

■ MSI complexity on a single chip 8 master-slave flip-flops plus output 

buffering 

Applications a g er j a | to parallel data conversion 

■ Serial-input/parallel-output data queueing ■ General purpose register 


RCA CD4015A types consist of two identical, independent, 
4-stage serial-input/parallel-output registers. Each register has 
independent "Clock" and "Reset" inputs as well as a single 
serial "Data" input. "Q" outputs are available from each of 
the four stages on both registers. All register stages are 
D-type, master- slave flip-flops. The logic level present at the 


data input is transferred into the first register stage and 
shifted over one stage at each positive-going clock transition. 
Resetting of all stages is accomplished by a high level on the 
reset line. Register expansion to 8 stages using one CD4015A 
package, or to more than 8 stages using additional 
CD401 5A s is possible. 



9-74 


Fig. 10.1— Logic diagram and truth table. 


81 












CD4015A 


File No. 479 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < V) < V DD ) 

(Recommended DC Supply Voltage (Vpp — V§§) 3 to 15 V) 


CHARACTERISTIC SYMBOL 


Quiescent Device 
Current 


TEST CD4015AD, CD4015AK, CD4015AF 

CON DITIONS 

Vo V DD -55°C 25° C 125°C 

Volts Volts Min. I Typ. | Max. Min. I Typ. I Max. Min. I Typ. I Max. 


CHARAC 
TERtSTIC 
CURVES 
& TEST 
CIRCUITS 


Quiescent Device 
Dissipation/Package | ^D 



Fig. 10.3— Typ. propagation delay time vs. Cf_. 











CD4015A 


File No. 479 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C and C L = 15 pF 

Typical Tempeiature Coefficient for all values of Vqq = 0.3 %/°C. (See Appendix for Waveforms) 


CHARACTERISTICS 

SYMBOLS 


LIMITS 

UNITS 

CHARAC- 
TERISTIC 
CURVES 
& TEST 

CIRCUITS 
Fig. No. 

TEST 

CONDITIONS 

CD4015AD 

CD4015AK 

CD4015AF 



V DD 

(Volts) 





HI 


CLOCKED OPERATION 

Propagation Delay Time 

tPHL= 

tPLH 



- 

300 

750 

- 

300 

1000 

ns 

10.3 

10 

- 

100 

225. 

- 

100 

300 

Transition Time 

t THL = 

tTLH 


5 

- 

150 

300 

~ 

150 

400 

ns 

10.4 

10 

- 

75 

125. 

- 

75 

150 

Minimum Clock Pulse 
Width 

twL= 

tWH 


5 

- 

200 

500 

- 

200 

830 

ns 


10 

- 

100 

175 

- 

100 

200 

Clock Rise & Fall Time 

\CL = 
tfCL 


5 

- 

- 

15 

- 

- 

15 

B 


10 

- 

- 

15 

- 

- 

15 

Set-Up Time 



5 

- 

100 

350 

- 

100 

500 

B 


10 

- 

50 

80 

- 

50 

100 

Maximum Clock 

Frequency 



5 

1 

2.5 

_ 

0.6 

2.5 

- 


n 

10 

3 

5 

- 

2.5 

5 

- 

Input Capacitance 

C| 


- 

5 

- 

- 

5 

- 

PF 

Kggigj 

RESET OPERATION 



Propagation Delay Time 

tPHUR) 


5 

- 

300 

750 

- 

300 

1000 


Mi 

10 

- 

100 

225 

- 

100 

300 

Minimum Set and Reset 
Pulse Widths 

%H(R) 


5 

- 

200 

500 

- 

200 

830 

ns 




10 

- 

100 

175 



100 

200 


If more than one unit is cascaded in a parallel clocked operation, 
t r CL should be made less than or equal to the sum of the fixed 
propagation delay time at 15pF and the transition time of the 
output driving stage for the estimated capacitive load. 



Test performed with the following 
sequence of "1's" and "0's" 

S 1 S 2 s 3 
Test 0 1 0 

Don't Test 0 0 1 

Don't Test 1 0 1 

Don't Test 0 0 0 

Don't Test 10 0 

Don't Test 0 0 1 

Test 1 0 1 

Don't Test 0 0 0 

Test 10 0 


Fig. 10.6 - Quiescent device current test circuit. 


84 














File No. 479 


CD4015A 


V DD 



Fig. 10.7 — Noise immunity test circuit. 



ALL P SUBSTRATES ARE CONNECTED TO Vqd 
ALL N SUBSTRATES ARE CONNECTED TO V SS 


Fig. 10.8 — Schematic diagram. 




File No. 479 


Digital Integrated Circuits 

Monolithic Silicon 

CD4016AD, CD4016AF 
CD4016AE, CD4016AK 



COS/MOS Quad Bilateral Switch 

For Transmission or Multiplexing of Analog or Digital Signals 

Special Features 

■ Wide range of digital and analog signal levels — 

Digital or analog signal to 15 V peak 
Analog signal ±7.5 V peak 

■ Low "ON" resistance— 

300 ft typ. over 15 V p . p signal input range, for Vqd — Vss = 15 V 

■ Matched switch characteristics — 

40ft typ. difference between Ron values at a fixed bias point over 15 Vp-p 

signal input range Vqd “ V SS = 15 v 

■ High "On/Off" output voltage ratio -65 dB typ. @ fj s = 10 kHz, Rl = 10 kft 

■ High degree of linearity -< 0-5% distortion typ. @ fj s = 1kHz, 

Vj s = 5 Vp.p, Vdq— V< jS— 10V, R L = lOkft. 


Applications 

■ Analog signal switching/multiplexing 

Signal gating Modulator 

Squelch control Demodulator 

Chopper Commutating switch 

■ Digital signal switching/Multiplexing 

■ COS/MOS logic implementation 

■ Analog-to-digital & digital-to-analog conversion 

■ Digital control of frequency, impedance, phase, and 
analog-signal gain 


■ Extremely low "OFF" switch leakage resulting in very low 
offset current and high effective "OFF" resistance — 

10 pA typ. @ VpD “ VSS = V, Ta = 25°C 

■ Extremely high control input impedance (control circuit 
isolated from signal circuit) — lO^ft typ. 

■ Low crosstalk between switches — 

-50 dB typ. @ fj s = 0.9 MHz, R l = 1 kft 

■ Matched control-input to signal-output capacitances — 
Reduces output signal transients 

■ Transmits freauencies up to 10 MHz 

vdd 



SWITCH A SWITCH B SWITCH C ' 

NOTE: All switch P -channel substrates are internally connected to terminal No. 14. 
All switch N-channel substrates are internally connected to terminal No. 7. 

NORMAL OPERATION: 


SWITCH D 

92SM -3838R2 


Control-Line Biasing 

Switch "ON": Vc"1" = Vqd 
S witch "OFF": Vq" 0" = Vgs 


SIGNAL-LEVEL RANGE: 

V S S.4V is 4VDD 

Fig. 1 1.1— Schematic diagram. 


Caution: 

If V|s exceeds Vqq, input currents 
must not be allowed to exceed 5 mA. 


86 


9-74 






INPUT SIGNAL VOLTS {V (s ) 


INPUT SIGNAL VOLTS (V )s ) 92 

92CS-I7836 



Fig.11.6—Typ. "ON" characteristics for 1 of 


Fig.11.7—Typ. “ON" characteristics for 1 of 

4 switches with Vqq= +5 V. 

- 

4 switches with Vqq= +2.5V, 

V SS =-5V. 


V SS =-2.5V. 











CD4016A File No. 479 

ELECTRICAL CHARACTERISTICS (Allinputs V SS <V, <V DD ) 

(Recommended DC Supply Voltage (V DD - V55) 3 to 15 V) 


ELECTRICAL CHARACTERISTICS (All inputs V SS <V, <V DD ) 

(Recommended DC Supply Voltage (V DD - V55) 3 to 15 V) 









LIMITS 

BB 


SYMBOL 






CD4016AD CD4016AK. CD4016AF 


WV1AVVM# 1 1C 






-550C 

25°C 

125°C . 









IBTM 




ca 

Ujjjl 

mm 

Quiescent Dissipation 
per Package 

■ 

0 

0 

> 

VOLTS 

TERMINALS APPLIED 

14 *10 

■ 

■ 


■ 

■ 



All Switches "OFF" 


8 0 
> > 

7 

5 

GND 

6. 12. 13 GND 

g 


01 

fl 

fl 

300 

pW 



v « 

1.4. 8. 11 

- +10 


■ 


■ 

■ 





V o, 

2.3.9. 10 

^ +10 


■ 

WM 

■ 




All Switches "ON" 

1 

V DD 

V SS 

VOLTS 

TERMINALS APPLIED 

14 +10 

7 GND 

| 

1 

0 1 

1 

1 

300 

pW 



V C 

5 

6,12,13 +10 


| 

■ 



■ 





_< 

< 

0 

14. 8 11 

£ +io 

1 

■ 


I 

m 



| SIGNAL INPUTS (V^) AND OUTPUTS (V QJ ) 


















■ 



H233B 

120 

360 

200 

400 

300 

600 





■ 

-7 5V 

EZ399 

PEI 



WM 


■ftU 

ft 




1 



■ttcqB 


Mm 

■EHS3 


wsm 

IHfll 





■ 



♦5V 

■k!*l 

ESDI 

H) 

gT71 

KE3 

*M»i 







-5V 

MkM 

Ir'i'iB 


gflil 

wm 


ft 

"ON" Resistance 

Q 

R l * 10k 12 

1 


at 

B.lrUf 

wm 

H:WiB 

WEE 

RtTil 

BTil 



m on 

■ 

MM 


♦ 15V 

mm 

Bri&B 

M>TTi1 

ITTil 

BE3 

Ki!il 








■PTil 

EH 


■ED 

TT71 


ft 





■ 


9 3V 

H'Mi 

wm 

MciVil 

■n?n 

wm 

iron 





■ 



♦ 10V 

■ESI 

B&U 


ESI 

BE21 


ft 







■E3 

ESI 


■ED 

KE3 

bed 




■ 

m 


b 

ism 

Q3E1 


Bj23 

9221 



A "ON" Resistance 

Between Any 2 
of 4 Switches 



KEH 

-7 5V 


_ 

_ 

■9 

n 

_ 

_ 

ft 



- 5 V 

gym 

- 

- 

15 

- 

- 

- 

Sine-Wave Response 
(Distortion) 


Bam 

QB 


5V(p pi* 

■ 

■ 

0.4 

■ 

■ 

■ 

°/o 

Input or Output 

Leakage— Switch "OFF" 
(Effective "OFF" 
Resistance) 

■ 

V DD V C = V SS V .s 

♦ 7 5V -7 5V ±7.5V 

■ 

■ 

■ 

■ 

■ 

B 

pA 

■ 

♦ 5V 

-5V 

±5V 

_ 

_ 



_ 

_ 

nA 

Frequency-Response- 
Switch "ON" 

(Sine Wave Input) 

■ 

R,= Ikl* 


V C= V DD = 

20 Log - 

v SS =- 5v 

3ilB 

- 

- 

40 

b 

■ 

fl 

D 

Feedthrough 

Switch "OFF" 

■ 

V |S 5V(p p) 

V DD* 

20 Log 

•SV.V C . V SS =-5V 

10 jT" 1 50,18 

- 

- 

1.25 

1 

■ 

fl 

■ 

Crosstalk Between Any 2 
of the 4 Switches 
(Frequency at -50 dB) 

■ 

R l * Ikl ’ 

V .s< A, = 

5V(p p) 

v c ,Al 

20 Log 

V 00 - ‘5V. 

V C ,Bl= V ss = -5V 
V os (8. 

in - 2s — = - 50rlB 

0 VA, 


- 

0.9 

1 

1 

H 


Capacitance Input 


V 0D S4 5V. V 

c xV ss = 

- 5 V 


- 

- 

■1 

■ 

n 

■ 


Output 







- 

- 

B 




pF 

Feedthrough 

BEH 






- 

- 



B 

9 


Propagation Delay 

Signal Input to 

Signal Output 

*pd 

V C r V DD t 4,0VV SS* gnd c l 
V |S = 10V (square wavel, 
t r s t| = 20ns (input signal) 

- 15pF . 



- 

10 

B 

1 


fl 


* ±10x1 0 — 3 * 

A Symmetrical about 0 volts 

88 


Limit determined by minimum feasible leakage measurement for automatic testing. 















































File No. 479 CD4016A 

ELECTRICAL CHARACTERISTICS (All inputs V $s < V, < V DD ) 

(Recommended DC Supply Voltage (Vqq - V§§) . . 3 to 15 V) 


ELECTRICAL CHARACTERISTICS (All inputs V $s < V, < V DD ) 

(Recommended DC Supply Voltage (Vqq - V 55 ) . . 3 to 15 V ) 









LIMITS 


CHARACTERISTIC 

SYMBOL 






CD4016AE 







— 40°C 

25°C 1 

85°C 









Typ. 

Max. 

Typ. 

Max. 

Typ. 

Max. 


Quiescent Dissipation 
per Package 


O 

O 

> 

; VOLTS 

TERMINALS APPLIED 

14 +10 








All Switches "OFF" 


v ss 

v c 

7 

5 

GND 

6.12,13 GND 


- 

5 

0.1 

5 

- 

80 

pW 




1 

4.8, 11 

S +10 









P T 

V o, 

2.3.9. 10 

- +10 








All Switches "ON" 

T 

V DD 

V SS 

VOLTS 

TERMINALS APPLIED 

14 +10 

7 GND 


5 

0 1 

5 


80 

pW 



V C 

5 

6.12,13 +10 











V is V os 

14. 8 11 

< +10 








| SIGNAL INPUTS (V js ) ANO OUTPUTS (V QJ I 




1 

Q 

O 

> 

V SS 

V .s 














♦ 7 5V 

130 

370 

200 

400 

260 

520 





+7 5V 

-7 5V 

-7 5V 

130 

370 

200 

400 

260 

520 








10 25V 

160 

790 

280 

850 

400 

1080 





“ 



♦5V 

150 

610 

250 

660 

340 

840 





+5V 

- 5 V 

-5V 

150 

610 

' 250 

660 

340 

840 

£1 

"ON" Resistance 

r on 

n 




^0 25V 

370 

1900 

580 

2000 

770 

2380 

R L J= k. 




♦ 15V 

130 

370 

200 

400 

260 

520 





+ 15V 

OV 

♦O 25V 

130 

370 

200 

400 

260 

520 

£1 







9.3V 

180 

790 

300 

850 

400 

1080 








♦ 10V 

150 

610 

250 

660 

340 

840 

£1 




+ 10V 

OV 

♦O 25V 

150 

610 

250 

660 

340 

840 







5 6V 

350 

1900 

560 

2000 

750 

2380 


A "ON" Resistance 

Between Any 2 
of 4 Switches 

-* r on 


♦7 5V 

-7 5 V 

±7 5 V 

_ 

_ 

10 

_ 

_ 

- 

a 


+5V 

- 5 V 

±5V 

- 

- 

15 


- 

- 

Sine-Wave Response 
(Distortion) 


R l - 10k 12 

‘.s'" 1kH ' 

+5V 

-5V 

5V(p p) A 

- 

- 

0.4 

- 

- 

- 

°/o 

Input or Output 

Leakage— Switch "OFF" 
(Effective "OFF" 
Resistance) 


V DD V C = V/ SS V .s 

♦ 7 5V -7 5V ± 7.5V 

- 

- 

+ 100 

- 

- 

- 

pA 


♦ 5V 

-5 V 

±5V 

_ 

_ 

O 

# 

±125 

_ 

_ 

nA 

Frequency-Response- 
Switch "ON" 

(Sine Wave Input) 


R,- 1k< > 


V C =V DD= -5V.V SS --5V 
V 

20 Log 10 -iiSr -3dB 

- 

- 

40 

- 

- 

- 

MH/ 

Feedthrough 

Switch "OFF" 


V (J 5V(p pi 

V DD J 

20 Log 

•5V.V C * \ 

V- 

10 V 

IS 

r ss -5V 

50.18 

- 

-■ 

1.25 

- 

- 

- 

MH/ 

Crosstalk Between Any 2 
of the 4 Switches 
(Frequency at -50 dB) 


R l - 1ki> 
V. S (A,= 

5V(p p) 

V c (Ai 

20 Log 

V DD i * 5V 

V C (8I= V ss .- - 5V 

V iBl 

in - 2i — = - 50.1B 
,U V (A) 


- 

0.9 

- 


- 

MH/ 

Capacitance Input 

C IS 

V 00 = *5V.V 

C = V SS = 

- 5 V 


- 

- 

4 

- 

- 

- , 


Output 

c os 






- 

- 

4 

- 

- 

- 

pF 

Feedthrough 

C lOS 






- 

- 

; 0.2 

- 

- 

- 


Propagation Delay 

Signal Input to 

Signal Output 

l pd 

V c' v dd" i,ovv ss* gndc l' 15pF 

V, s * 10V (square wave). 
t| - 20 ns (inpul signal) 

- 

- 

10 

- 

- 

- 

ns 


• ±10x 10 -3 
A Symmetrical about 0 volts 


Limit determined by minimum feasible leakage measurement for automatic testing. 


89 




CD4016A 


File No. 479 


ELECTRICAL CHARACTERISTICS (All inputs V ss < V, < V DD ) 

(Recommended DC Supply Voltage (Vqp - V 55 ) 3 to 15 V) 


CHARACTERISTIC SYMBOL 


LIMITS 

CD4016AD, CD4016AK , CD4016A F 

-55°C 25°C 125 U C 

Min. I Typ. [Max. Min. | Typ. [ Max. Min. I Typ. I Max 


Switch Threshold Voltage* 

mi 

Input Current 

■ 

Average Input Capacitance 


Crosstalk (Control Input j 
to Signal Output) 


Turn "ON" 

Propagation Delay 

‘pd c 

Maximum Allowable 
Control Input 

Repetition Rate 




V DD -VsS= ,0V - 

V C =10V 

R L = 10ki2 

(square wave); 

«rc = *»c s 20 ns 

V |S — 10V.C L - 15pF 

V DO" ,0VV SS- 
C L = 15pF 

GND.R l = 1kl2 

V^= 10V (square wave) 
t r = t f = 20 ns 


CHARAC- SUPPLY 
TERISTIC* CONDITIONS 



LOAD 

CONDITIONS 


TYPICAL 

CHARAC- 

R l = 1kS2 

R l = lOkft 

R l = 100k £2 

TERISTIC 

VALUE V is 

VALUE V |s 

VALUE V js 

' CURVE 

<n> (V) 

in) (v) 

(fi) (V) 

Fig. No. 


mil 


SlSiitiMmd 


Eibll 















File No. 479 CD4016A 

ELECTRICAL CHARACTERISTICS (All inputs V SS <V, <V DD ) 

(Recommended DC Supply Voltage (Vqq — V 55 ) 3 to 15 V) 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

LIMITS 

UNITS 

CD4016AE 

-40°C 

25°C 

85°C 

Min. | Typ. |Max. 

Min. | Typ. |Max. 

Min. | Typ. |Max 

| CONTROL (V c ) 1 

Switch Threshold Voltage* 

v TH N 

V . S - V DD 

V DD~ V SS = 15V ' 10V - 
5V; l| S =10pA 

- 

- 

- 

0.5 

1.5 

2.7 

1 


■ 

1 

Input Current 

•c 

V DD- V SS= ,0V 

v c- v oo- v ss 

- 

- 

- 

- 

±10 


■ 

i 

1 


Average Input Capacitance 

c c 



- 

- 

- 

5 


- 

- 

- 

pF 

Crosstalk (Control Input 
to Signal Output) 


v 00 -vss=iov. 
v c = 10V 

(square wavel. 

« rc = t <c --20ns 

R L = 10ki2 

- 

- 

- 


50 

- 

- 


- 

mV 

Turn "ON" 

Propagation Delay 

'pd c 

V .s~ ,0V C L" ,5pF 


- 


- 

20 

- 

- 

- 


ns 

Maximum Allowable 

Control Input 

Repetition Rate 


V DD-' ,0VV SS =GNDR L i,ki2 

C L = 15pF 

V C = (square wavel 

t f = t { = 20 ns 


- 

- 


10 

- 

- 



MHz 



92CS -16072 

Fig. 1 1.8— Typ. "ON” characteristics as a 
function of temp, for 1 of 4 
switches with Vqq=+5V, 

V SS =*-5V. 


SIGNAL RMS MILLIVOLTS (V os ) 

u> 0 K 0 

SUPPLY VOLTS: V 00 = + 5, V 
CONTROL VOLTS (V C )*-5 
INPUT SIGNAL VOLTS (Vj s 
• LOAD CAPACITANCE (CL)’C 
FIXTURE AND METER NUL 
ClOS( F ,xTURE)* 08pF 

SS- 

=5 

FIX 

LEt 

Vp 

ru 

i ( 

-F 

R 

>11 

SIN 

E+Cf 

T 

E Vt 
AET 

/ 

AV 

ER 

0 . 7 - 

2 . 3 + 

Hh 

2.5 

IS) 

*40 

PF 


It 1 RE VOLTMETER 

O BOONTON RADIO 

Y 1 MODEL 91-CA 

TTT ! 0R EQUIV . „ 


/ 


t 

i 






jit tv 

t 

L 

J 


1 

A 

f 


_> 

i 

* 5 







F 

1 A 




1 

/ 


“J 

J 

■/ 

- 41.5 3 

L J 

A* < 

3 

CL 

“1 





i 

f 

I 


1 



a 


/ 

f 


- 

0 

0 



1 

J 


i 



a 

1 

1 



1 

7 

r~ 




I0 _l 

4 


2 4 61 

10 

4 

6 

0 2 2 


?o 3 ‘ 


1 6 ! 

o 4 


INPUT SIGNAL FREQUENCY (fi.) kHz 

92CS-I6079 


Fig. 1 1.9— Typ. feedthru vs. freq. — switch 
"OFF”. 


91 






CD4016A 


File No. 479 



92CS- 16080 

Fig. 1 1. 10—Typ. crosstalk between switch 
circuits in the same package. 



92CS-I6070 

Fig. 11.1 1—Typ. switch frequency response 
— switch "ON". 



ALL UNUSED TERMINALS 
ARE CONNECTED TO V cc 


92CS-I6086 


Fig. 1 1. 12-Test circuit for square wave 
response. 


V DD 



9ZCS-I607I 

Fig. 1 1. 13— "OFF" switch input or output 
leakage test circuit. 



SCALE: X = 0.2 ms/DIV Y = 2.0 V/DIV 
VDD = Vc = +7.5V, VsS = -7.5V, R|_ = 10KS2 
C L = 15pF 

f|S=1KHz V|S = 5V p-p 
DISTORTION = 0.2% 

Fig. 1 1. 14—Typ. sine wave response of Vqq= 
+7.5V, V S s=-7.5V. 


SCALE: X = 0.2 ms/DIV Y = 2.0 V/DIV 
VDD = Vc = +5 V, Vss = -5 V, Rl = 10K« 
Cl = 15 pF 

f|S=1KHz V|S = 5 V p-p 
DISTORTION = 0.4 % 


Fig. 1 1. 15—Typ. sine wave response of Vqq= 
+5V. Vss=* -5V. 


SCALE: X = 0.2 ms/DIV Y = 2.0 V/DIV 
Vqd = Vc = +2.5V, Vss = -2.5V, «L= 10KS2 
C L =15pF 

f IS = 1 KHz Vis = 5V p-p 
DISTORTION = 3 % 

Fig. 1 1. 16—Typ. sine wave response of Vqq’ 
+2.5V, 1 / 55 = -2.5V. 



SCALE: X = 100 ns/DIV 
Y = 5.0 V/DIV 



SCALE: X= 100 ns/DIV 
Y = 5.0 V/DIV 



SCALE: X= 100 ns/DIV 
Y = 2 V/DIV 


Fig. 1 1. 17—Typ. square wave response at 
Vdd = V(f=+15V, Vss^Gnd. 


Fig. 1 1. 18—Typ. square wave response at 
VdD=VC= + 10V ’ V SS = Gnd. 


Fig. 1 1. 19—Typ. square wave response at 
Vdd~ VqT + 5V, 1 / 55 = Gnd. 


92 








File No. 479 


CD4016A 



ALL UNUSED TERMINALS 
ARE CONNECTED TO V s$ 

92CS-I6O07 


v c 


Vos WITH TEST UNIT 
( 1 SWITCH OF CD4016A 
PLUGGEO IN TEST 
FIXTURE) 


VOS FIXTURE ALONE 
(NO UNIT... TERM 
5 TO 3 OF SOCKET) 



V C = 10V PER DIV. 
Vos = 0.2V PER DIV. 
100ns PER DIV. 


Fig. 1 1.20— Crosstalk-control input to signal 
output. 



92CS-I6085 

Fig. 1 1 .21 —Propagation delay time signal 
input (Vis) to signal output 
(Vos). 



Fig. 1 1.23— Max. allowable control-input 
repetition rate. 



92CS-I608e 

Fig. 1 1.22— Turn-on propagation delay-control 
input. 



Fig. 1 1 .24— Capacitance C/QS and COS- 



Fig. 1 1 -25-Switch thresholf voltage - N-channel 
test circuit. 


93 



File No. 479 


Digital Integrated Circuits 

Monolithic Silicon 

CD4017AD, CD4017AF 
CD4017AE, CD4017AK 



COS/MOS Decade 
Counter/Divider 

Plus 10 Decoded Decimal Outputs 

Special Features 

■ Medium speed operation 5 MHz (typ.) at Vqd — VSS = ™ V 

■ Fully static operation 

■ MSI complexity on a single chip decade counter plus 10 decoded outputs 

Applications 

■ Decade counter/decimal decode display applications 

■ Frequency division 


CD4017A types consist of a 5-stage Johnson decade counter 
and an output decoder which converts the Johnson binary 
code to a decimal number. Inputs include a "Clock", a 
"Reset", and a "Clock Enable" signal. 


■ Counter control/timers 

■ Divide by N counting 

N = 2 — 10 with one CD4017A and one CD4001A 
N > 10 with multiple CD4017A's 


The decade counter is advanced one count at the positive 
clock signal transition if the clock enable signal is "low". 
Counter advancement via the clock line is inhibited when the 
clock enable signal is "high". A "high" reset signal clears the 
decade counter to its zero count. Use of the Johnson decade 
counter configuration permits high speed operation, 2-input 
decimal decode gating, and spike-free decoded outputs. 
Anti-lock gating is provided, thus assuring proper counting 
sequence. The 10 decoded outputs are normally "low" and 
go "high" only at their respective decimal time slot. Each 


■ For further application information, see ST4166 
"COS/MOS MSI Counter and Register Design & 
Applications" 


decoded output remains "high" for one full clock cycle. A 
carry-out (CoUT) signal completes one cycle every 10 clock 
input cycles and is used to directly clock the succeeding 
decade in a multi-decade counting chain. 






94 


Fig. 12. 1 — Logic diagram. 


9-74 











Fig. 12.6— Typ. transition time vs. C(_ for 
carry output. 





CD4017A File No. 479 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < V| < V DD ) 

(Recommended DC Supply Voltage (Vqq — Vgg) 3 to 15 V) 







LIMITS 


CHARAC 

CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 

CD4017AD, CD4017AK, CD4017AF 

UNITS 

TERISTIC 
CURVES 
& TEST 




Vo 

V DD 

-55°C 

25°C 

125°C 


CIRCUITS 




Volts 

Volts 

Min. 

Typ. 


BnjjjjHj 

■233 


£2413 

EBB 



Fig. No. 

Quiescent Device 




B 

- 

- 


- 

EB 

5 

- 

- 



12.9 

Current 




,0 

- 

- 

KM 

- 


MM 

- 

- 

m 


Quiescent Device 

Pd 



B 

mm 

- 

m 

~ 


m 

- 

- 




D issi pation /Pack age 



10 

rn 

- 


- 


UJ! 

- 

- 



Output Voltage: 

VOL 



B 

mm 

— 


- 


fflf 

_ 

- 

EO 



Low-Level 



10 

EZ 

- 


- 

0 


- 

IB 


iHI 


High-Level 

VOH 



B 

njj 

- 

_ 

ESI 

5 

- 

hsb 

1^31 

- 

Hi 




B 


- 

- 


10 

- 


o 

- 

m 


Noise Immunity 

vnl 


0.8 

■3 

& 

- 


15 

2.25 

- 

1.4 

- 

- 

mm 


(Any Input) 


1.0 

.0 

EB 


- 

m 

KB 

- 

2 9 

- 

- 

■ 

12.10 

For Definition, 

See Appendix 

Vnh 


4.2 

B 

B 

- 

- 

IB 


- 

1.5 

- 

- 

H 

mmmm 


m 

B 

m 

- 

- 

3 

4 5 

- 

3 



- 

B 



Output Drive Current: 


Decoded 


B 

QH 

- 

- 

01 

m 


BBI 

- 

B 

■ 


N-Channel 

'd n 

Outputs 


B 

3BI 

- 

- 

e m 

EM 

- 


- 

m 



ZB 


» 

323 

- 

- 

S3 

0.4 

— 

133 

- 

B 


■ 




El 

3jj| 

- 

- 

S3 

1 

- 


- 

B 

O 

4 

■ B 



m 

B 

BSE 

- 

_ 

Tim 


_ 

-0.021 

_ 

_ 



1 



SI 

El 

QQ| 

- 

- 

-0.1 

-0.2 

- 

-0.07 

- 

- 




Carry 

S3 

B 


- 

- 

-0.15 


- 

-0.105 

- 

- 




Output 


10 

-0.45 

- 

- 


- i 

- 

SI 

- 

- 




'l 




- 

- 

- 

10 

- 


- 


pA 

■■ 


♦See Appendix. 



92CS-I78E9RI 


Fig. 12.8— Typ. dissipation characteristics. 


96 












File No. 479 


CD4017A 


STATIC ELECTRICAL CHARACTERISTICS (All inputs ^SS< y }<^DD^ 

(Recommended DC Suoply Voltage (Vqq — Vcjs) 3 to 15 V) 


CHARACTERISTIC 

SYMBOL 


LIMITS 

UNITS 

CHARAC- 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 

Fig. No. 

TEST 

CONDITIONS 

CD4017AE 


v 0 

Volts 

V DD 

Volts 

-40°C 

25°C 

85°C 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Quiescent Device 

Current 

'L 



5 

~ "1 

- 

50 

- 

0.5 

50 

- 

- 

700 

UA 

12.9 

10 

- 

- 

100 

- 

1 

100 

- 

- 

1400 

Quiescent Device 
Dissipation/Package 

PD 



5 

_ 

_ 

250 

_ 

2.5 

250 

— 

_ 

3500 

p\N 

- 

10 

- 

- 

1000 

- 

10 

1000 

- 

- 

14,000 

Output Voltage: 

Low-Level 

VOL 



5 

- 

- 

001 

- 

0 

001 

- 

- 

0.05 

V 

- 

10 

- 

- 

001 


0 

0.01 

- 

- 

0.05 

High-Level 

v OH 



5 

4.99 

— 

- 

4 99 

5 

- 

4 95 

- 

- 

V 


10 

9.99 

- 

- 

9 99 

10 

- 

9.95 

- 

- 

Noise Immunity 
(Any Input) 

For Definition, 

See Appendix 

vnl 


0.8 

5 

15 

- 

- 

1.5 

2.25 

- 

1.4 

- 

- 

V 

12.10 

1.0 

10 

3 

- 

- - 

3 

4.5 


2.9 

- 


vnh 

4.2 

5 

1 4 

- 

- 

1.5 

2.25 

- 

1.5 

- 

- 

V 

9.0 

10 

2 9 

- 

- 

3 

4.5 


3 

~ 

- 

Output Drive Current: 

N-Channel 

! d N 

Decoded 

Outputs 

05 

5 

0 03 

_ 

_ 

0025 

0.1 

1 

0.02 

_ 


mA 

♦ 

0.5 

10 

0.085 

- 

- 

0.07 

0.4 

- 

0.055 

- 

- 

Carry 

Output 

0.5 

5 

0.095 

— 

— 

0.08 

0.4 

_ 

0.065 

_ 

— 

0.5 

10 

0.3 

- 

- 

0.25 

1 

- 

0.2 

- 

- 

P-Channel 

'd p 

Decoded 

Outputs 

4.5 

5 

-0.018 

_ 

_ 

-0.015 

-0.075 

_ 

-0.012 

_ 

_ 

mA 

9.5 

10 

-0.085 

- 

- 

-0.07 

-0^2 

r - 

-0.055 

- 

- 

Carry 

Output 

4.5 

5 

-0.095 

- 

- 

-0.08 

-0.4 

- 

-0.065 

- 


9.5 

10 

-0.3 

- 

- 

-0.24 

- 1 

- 

-0.20 

- 


Input Current 

'l 


- 

- 

- 

- 

10 

- 

- 

- 

- 

pA 



♦ See Appendix. 


iov 



Test performed with the following 
sequence of "1's and "OV'at each stage. 


S 1 s 2 S3 

1 1 1 

0 0 0 

O 1 0 

0 0 0 

0 1 0 

0 0 0 


Si s 2 S3 

0 1 0 

0 0 0 

0 10 
0 0 0 

010 
0 0 0 

0 1 0 


Fig. 12.9— Quiescent device current test circuit. 



Fig. 12. 10— Noise immunity test circuit. 






CD4017A File No. 479 

DYNAMIC ELECTRICAL CHARACTERISTICS at T^ = 25°C, Cj_ = 15 pF, and input rise and fall times = 20 ns except t r CL, tfCL 
Typical Temperature Coefficient for all values of Vqq = 0.3%/°C . (See Appendix for Waveforms) 





LIMITS 


CHARAC- 



TEST 


CD4017AD 





TERISTIC 

CHARACTERISTICS 

SYMBOLS 

CONDITIONS 

CD4017AK 

CD4017AE 

UNITS 

CURVES 




CD4017AF 





& TEST 




Q 

O 

> 








CIRCUITS 




(Volts) 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 


Fig. No. 

| CLOCKED OPERATION | 

Propagation Delay Time: 



5 

- 

350 

1000 

- 

350 

1300 

ns 

12.4 

Carry Out Line 

tpHL" 


10 

- 

125 

250 

- 

125 

300 

Decode Out Lines 

*PLH 


5 

- 

500 

1200 

- 

500 

1600 


12.3 



10 

- 

200 

400 

- 

200 

500 


Transition Time: 



5 

- 

100 

300 

- 

100 

350 

ns 

12.6 

Carry Out Line 

t THL = 


10 

- 

50 

150 

- 

50 

200 

Decode Out Lines 

*TLH 


5 

- 

300 

900 

- 

300 

1200 

ns 

12,5 



10 

- 

125 

350 

- 

125 

450 

Minimum Clock 

*WL = 


5 

- 

200 

500 

- 

200 

830 

ns 


Pulse Width 

*WH 


10 

- 

100 

170 

- 

100 

250 


Clock Rise & Fall Time 

trCL = 


5 


- 

15 


- 

15 

Ms 


tfCL 


10 


- 

15 

- 

- 

15 


Clock Enable Set-Up 



5 

- 

175 

500 

- 

175 

700 

ns 


Time 



10 

- 

75 

200 

- 

75 

300 


Maximum Clock 

'CL* 


5 

i 

2.5 

- 

0.6 

2.5 

- 

MHz 


Frequency 


10 

3. 

5 

- 

2 

5 

- 


Input Capacitance 

C l 

Any Input 

- 

5 

1 

' i 

5 

- 

pF 

- 

RESET OPERATION | 

Propagation Delay Time: 



5 

- 

350 

1000 

- 

350 

1300 



To Carry Out Line 

VHLIR) 


10 

- 

125 

250 

- 

125 

300 



To Decode Out Lines 


5 

- 

450 

1200 

- 

450 

1600 

ns 




10 

- 

200 

400 

- 

200 

500 


Reset Pulse Width 



5 

- 

200 

500 

- 

200 

830 

ns 


t WH(R) 


10 

_ 

100 

165 

- 

100 

250 


Reset Removal Time 



5 

_d 

300 

750 

- 

300 

1000 





,0 


100 

225 

- 

100 

275 




* Measured with respect to carry output line 



Fig. 12. 1 1— Divide by N counter (N <10) with N decoded outputs. 

98 


When the N th decoded output is reached (N^ 1 clock pulse) 
the S-R flip flop (constructed from two NOR gates of the 
CD4001 A) generates a reset pulse which clears the CD4017A 
to its zero count. At this time, if the N th decoded output is 
greater than or equal to 6, the Cqut line goes "high" to 
clock the next CD4017A counter section. The "0" decoded 
output also goes high at this time. Coincidence of the clock 
"low" and decoded "0" output "low" resets the S-R flip 
flop to enable the CD4017A. If the N^ 1 decoded output is 
less than 6, the Cqut l' ne W *H not 9° "high" and, there- 
fore, cannot be used. In this case "0" decoded output may 
be used to perform the clocking function for the next count- 
er. 





File No. 479 


Digital Integrated Circuits 

Monolithic Silicon 

CD4018AD, CD4018AF 
CD4018AE, CD4018AK 


COS/MOS 

Presettable Counter 

Special Features 

■ Medium speed operation 5 MHz (typ.) at Vqd — V SS = 10 V 

■ Fully static operation ■ MSI complexity on a single chip 

Applications 

■ Fixed and programmable divide-by-10, 9, 8, 7, 6, 5, 4, 3, 2 counters 

■ Fixed and programmable counters greater than 10 

■ Programmable decade counters ■ Frequency division 

■ Divide-by-"N" counters/frequency synthesizers ■ Counter control/timers 

CD4018A_ types consist of 5 Johnson-Counter stages, to properly gate the feedback connection to the Data input, 

buffered Q outputs from each stage, and counter preset Divide-by functions greater than 10 can be achieved by use 

control gating. "Clock", "Reset", "Data", "Preset Enable", of multiple CD4018A units. The counter is advanced one 

and 5 individual "Jam" inputs are provided. Divide by 10, 8, count at the positive clock-signal transition. A "high" Reset 

6, 4, or 2 counter configurations can be implemented by signal clears the counter to an "all-zero" condition. A "high" 

feeding the Q5, Q4, Q3, Q2, Q1 signals, respectively, back to Preset-Enable signal allows information on the Jam inputs to 

the Data input. Divide-by-9, 7, 5, or 3 counter configurations preset the counter. Anti-lock gating is provided to assure the 

can be implemented by the use of a CD401 1 A gate package proper counting sequence. 



Fig. 13.1 — Logic diagram. 


9-74 



99 










CD4018A 


File No. 479 


STATIC ELECTRICAL CHARACTERISTICS (All inputs Vss < V, < V DD ) 

(Recommended DC Supply Voltage (Vpp — V 55 ) 3 to 15 V) 


CHARACTERISTIC 

SYMBOL 


LIMITS 

UNITS 

CHARAC- 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 

Fig. No. 

TEST 

CONDITIOI* 

JS 

CD4018AD, CD4018AK, CD4018AF 


v 0 

Volts 

V DD 

Volts 

-55°C 

25° C 

125°C 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Quiescent Device 

Current 

'L 



5 

- 

- 

5 

- 

0.3 

5 

- 

- 

300 

PA 

13.9 

10 

- 

- 

10 

- 

0.5 

10 

- 

- 

600 

Quiescent Device 
Dissipation/Package 

PD 



5 

_ 

_ 

25 

- 

1.5 

25 

_ 

_ 

1500 

fi\N 

Bl 

10 

- 

- 

100 

- 

5 

100 

- 

- 

22§§ 



♦ see Appendix. 


("DATA" INPUT TIED TO 0 5 FOR DECADE COUNTER CONFIGURATION) 



Fig. 13. 2— Timing diagram. 




File No. 479 


CD4018A 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V $s < V, < V DD ) 

(Recommended DC Supply Voltage (Vqq — Vcjg) 3 to 15 V) 


CHARACTERISTIC 

SYMBOL 


LIMITS 

UNITS 

CHARAC 

TERISTIC 

CURVES 

81 TEST 

CIRCUITS 

Fig. No. 

TEST 

CONDITIONS 

CD4018AE 


V o 

Volts 

V DD 

Volts 

— 40°C 

25° C 

85° C 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Quiescent Device 

Current 

'L 



5 

- 

- 

50 

- 

0.5 

50 

- 

_ 

700 

mA 

13.9 

to 

- 

- 

100 

- 

1 

100 

- 

- 

1400 

Quiescent Device 
Dissipation/Package 

PD 



5 

_ 

_ 

250 

_ 

2.5 

250 

- 

- 

3500 

pW 

- 

10 

- 

- 

1000 

- 

10 

1000 

- 

- 

14000 

Output Voltage: 

Low-Level 

VOL 



5 

_ 

_ 

0.01 

- 

0 

0.01 

- 

— 

0.05 

V 

* 

10 

- 


0.01 

- 

0 

0.01 

- 

- 

0.05 

High-Level 

VOH 



5 

4 99 

_ 

_ 

4 99 

5 

- 

4.95 

- 

_ 

V 

- 

10 

9 99 


- 

9.99 

10 

- 

9.95 

- 

- 

Noise Immunity 

(Any 1 nput) 

For Definition. 

See Appendix 

VNL 


0.8 

5 

1 5 

- 

- 

1 5 

2 25 

- 

1.4 

- 

- 

V 

13.10 

1.0 

10 

3 

" 

- 

3 

4.5 


2.9 

- 

- 

Vnh 


4.2 

5 

1 4 

- 

- 

1.5 

2.25 

- 

1.5 

- 

- 

V 

- 

9.0 

10 

2 9 

- 

- 

3 

4.5 

~ 

3 

- 

- 

Output Drive Current : 

N-Channel 

i d n 

os 

0.5 

5 

0.095 

- 

- 

0.08 

0.4 

- 

0.065 

- 

- 

mA 

♦ 

0.5 

10 

03 

- 

- 

0.25 

1 


0.2 

- 

- 

Q lP2, 

6364 

0.5 

5 

0.03 

- 

- 

0.025 

0.1 

- 

0.02 

- 

- 

0.5 

10 

0 18 


- 

0.15 

0.4 

- 

0.12 

~ 

- 

P-Channel 

'd p 

C>5 

4.5 

5 

-0.095 

- 

- 

-0.08 

-0.4 

- 

-0.065 

~ 

- 

mA 

♦ 

9.5 

10 

-0.3 

- 

- 

-0.25 

-1 

- 

-0.2 


- 

Q1.Q2. 

Q 3 Q 4 

4.5 

5 

-0.035 

- 

- 

-0.03 

-0.15 

- 

-0.024 

- 

- 

9.5 

10 

-0.18 

~ 

- 

-0.15 

-0.4 


-0.12 

~ 


Input Current 

•l 




- 

_ 

10 

~ 



- 

PA 

- 


♦See Appendix 


| 1500 

AMBIENT TEMPERATURE (T A ) = 25°C 
TYPICAL TEMPERATURE COEFFICIENT FOR ' 
ALL VALUES OF V DD = 0.3% /°C t 




























44 

44 

44 

44 


44 

444 

444 


::: 





■S 

!S5 

CL 


a 




s 

1 

IB 

IBI 

B 


■BBI 

SS 


::: 





IB 

jBB 

7 






SS! 

a 

■a 

IBI 

B 


■ BBI 

aa 


::: 





IB 

mm 

X 






is: 

a 

is 

TT 

fl 


SSSi 

aa 

IB 






isi 

iss 

~ 1000 






IBI 

a 

IB 


ft 

ft 

SSSS 

SS 

IB 






IBI 









SI 

PP 

LY 

VO 

LT 

(V 

DD> 

5 






ft 

iss 

P 






ft 






IBI 

■SS 




ii 

IBI 


IBI 

IBI 

B 

Bl 


B 

III 1 


a 





IBI 

IBI 

IBB 

j 



IB 





B 

m» 

•"! 

B 

■BBI 

IBBI 

IBI 

■Bl 




n 

n 

IBB 

0 

(■1 


IB 





a 

Bl 

IBI 

B 

SSSi 

■BBI 

IBI 

■Bl 

IBI 

IBI 

IBI 

IBI 

IBI 

ibS 

| 500 








:: 

:: 






-r_ 







< 

0 

g 








:: 

:: 




g 

10- 


:: 







0 

oc 

CL 








:: 

::: 














10 20 30 40 50 60 70 80 

LOAD CAPACITANCE (C L ) — pF 

9ZCS- 17826 


Fig. 13.3— Typ. propagation delay time vs. C/_ 
for decoded outputs. 



C/_ for Q 5 output. 


101 





CLOCK INPUT FREQUENCY (1 CL )- MHz 


CD4018A 


File No. 479 



SUPPLY VOLTS (V 0D ) 


Fig. 13.7—. Typical dock frequency 
vs. Vqq 


INPUT CLOCK FREQUENCY (f CL ) — kHz 


Fig. 13.8— Typ. dissipation characteristics 


, 1 1 Test performed with 

16 n 0-1 " the following sequence 

15 of " 1 's" and "O's" at 

1 14 ~j ^ || each stage. 

i 12 1 S-| S 2 S3 S4 S5 Sg S7 

’ !o 0110000 

» 9 ' ' 1110 0 11 

_ o-! — -> 1 1 0101 1 1 

0100100 

oJL 0 10 0 10 1 

sNj-i, 1001110 

7 dr 0 0 0 1 0 0 0 

0 0 0 0 0 0 0 

92CS " 7913 1 0 0 0 1 0 0 

0 0 0 0 0 1 0 

0 0 0 0 0 0 0 

Fig. 13.9 — Quiescent device current test circuit. 



o — Ol.5 V OR 3 V 


Fig. 13. 10 — Noise immunity test circuit. 











File No. 479 


CD4018A 


DYNAMIC ELECTRICAL CHARACTERISTICS at Ta = 25°C, Cl = 1 5 pF, and input rise and fall times = 20 ns except t r CL,tfCL 
Typical Temperature Coerficient for all values of Vdd = 0.3%/°C (See Appendix for Waveforms) 


CHARACTERISTICS 

SYMBOLS 

TEST 

CONDITIONS 

LIMITS 

UNITS 

CHARAC- 

TERISTIC 

CURVES 

& TEST 

CIRCUITS 
Fig. No. 

CD4018AD 

CD4018AK 

CD4018AF 

CD4018AE 


V DD 

(Volts) 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

| CLOCKED OPERATION j 

Propagation Delay Time: 



5 

- 

350 

1000 

- 

350 

1300 

ns 

13.4 

To Q 5 Output 

t PHL ~ 


10 

- 

125 

250 

- 

125 

300 




*PLH 


5 

_ 

500 

1200 

_ 

500 

1600 



To Other Outputs 









— 

ns 

13.3 



10 

- 

200 

400 

- 

200 

500 



Transition Time: 


5 

- 

100 

300 

“ 

BIBI 

350 













j To Q 5 Output 

t THL = 


10 

- 

50 

150 


50 





l TLH 


5 

■ 

KP 1 


: B 





To Other Outputs 







SB 



ss 






10 

■ 





B 



Minimum Clock 



5 

- 



m 

jjj^S 




Pulse Width 



10 

- 

|y 


Bl 

mm 





VCL - 


5 

- 

- 

15 

s 

- 

15 




t fCL 


10 

- 

- 

15 

■ 

- 

15 





5 

_ 



M 





Data Input Set-Up Time 









SfijEE 

ns 

— 




10 

- 

MU 


- 

mu 

300 



Maximum Clock 



5 

1 

2.5 

_ 

0.6 

2.5 

_ 



Frequency 

f CL 


10 

3, 

5 

- 

2 

B 

- 



Input Capacitance 

C l 

Any Input 

- 

5 

- 

- 

B 


■ 

- 

PRESET* OR RESET OPERATION 


Propagation Delay Time: 



5 

- 

350 

1000 

- 

ms 

ms 



To Q 5 Output 

t PLH(R)' 


10 

- 


mug 

- 






tPHLtPR) = 


5 

_ 



_ 

IFBil 




To Other Outputs 





5§§||^9 

■ 9E9 9 





— 


tPLH(PR) 

■■1 


- 

200 

400 

B 

||OT 




Preset or Reset 

t WH(R)< 


5 

ms 



B 

wmn 

mm 



Pulse Width 

X \NH(PR) 



- 



- 

m 




Preset or Reset 



5 

- 

iM 

750 

- 

ms 

0 



Removal Time 



10 

- 

100 


- 

m 





*At Preset Enable or Jam Inputs. 


EXTERNAL CONNECTIONS FOR DIVIDE 
BY 10, 9, 8, 7, 6, 3, 4, 3 OPERATION 


DIVIDE BY 10 
DIVIDE BY 8 
DIVIDE BY 6 
DIVIDE BY 4 


Q sT 

34 

a 3 

a 2 J 


CONNECTED 
BACK TO 
"DATA - 


NO EXTERNAL 
COMPONENTS 
REQUIRED 


0IVI0E BY T 

1/2 CD40IIA 

q 3 r is. “"i 

J1 \ J X j CONNECTED BACK TO "DATA" 
^—4-1 y lSKIPS ‘ALL- ft" STATE) 


Ql I 


DIVIDE BY 9 

1/2 CD40IIA 



CONNECTED BACK TO "DATA" 
(SKIPS "ALL-I'f" STATE) 


DIVIDE BY 5 

1/2 CD40IIA 



CONNECTED BACK TO "OATA* 
(SKIPS "ALL- ft" STATE) 


CONNECTED BACK TO "DATA" 
(SKIPS "ALL- ft" STATE) 


92CS- I707IRI 


Fig. 13.11 — External connections for divide by 10,9,8,7,6,5,4,3 operation. 


103 











File No. 479 


Digital Integrated Circuits 

Monolithic Silicon 

CD4019AD, CD4019AF 
CD4019AE, CD4019AK 



COS MOS Quad 
AND-OR Select Gate 

Special Features 

■ Medium-speed operation tpHL = t PLH = 50 ns (typ.) at C[_ = 15 pF 

Applications 

■ AND-OR select gating 

■ Shift-right/shift-left registers 

■ True/complement selection 

■ AND/OR/Exclusive-OR selection 


CD4019A types are comprised of four "AND-OR Select" 
gate configurations, each consisting of two 2-input AND 
gates driving a single 2-input OR gate. Selection is ac- 
complished by control bits K a and Kb- In addition to 


selection of either channel A or channel B information, the 
control bits can be applied simultaneously to accomplish the 
logical A + B function. 



104 


9-74 





File No. 479 


CD4019A 


TYPICAL CD4019A APPLICATIONS 


“B" REGISTER "A" REGISTER 



Fig. 14.2- AND/OR select gating. 



Fig. 14.3— "Shift left/shift right" register. 



Fig. 14.4 — "True" complement" selector. 


105 







CD4019A 


File No. 479 


STATIC ELECTRICAL CHARACTERISTICS (All inputs 

(Recommended DC Supply Voltage (Vqq — Vgs)- 


v ss <v,<v DD ) 

3 to 15 V) 







File No. 479 


STATIC ELECTRICAL CHARACTERISTICS (All inputs 

(Recommended DC Supply Voltage (Vqq - 

LIMITS 

CD4019AE 


v ss < v,<v DD ) 

3 to 15 V) 


CHARACTERISTIC SYMBOL 


! Quiescent Device 
Current 


Quiescent Device 
Dissipation/Package 


Output Voltage: 
Low- Level 


TEST 

CON DITIONS 

V 0 V DD 

Volts Volts Min 


— 40°C 

I Typ. I Max. 


CHARAC 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 


Noise Immunity 
(Any Input) 

For Definition. 

See Appendix 

Output Drive Current: 
N-Channel 


3.6 5 1.4 
7.2 10 2.9 


I Input Current 
♦See Appendix 


» AMBIENT TEMPERATURE (T A ) » 25°C 

, TYPICAL TEMPERATURE COEFFICIENT FOR ALL 

x 300 VALUES OF V DD = 0.3% /°C 


BB 

BB 

si 

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sill 

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:s 

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IBB 

ss 

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LOAD CAPACITANCE (C L ) - pF 
Fig. 14.6-Typ. propagation delay time vs C[_. 


AMBIENT TEMPERATURE (T A ) » 25°C 
TYPICAL TEMPERATURE COEFFICIENT FOR ALL 
<= 300 VALUES OF V DD - 0.3% / # C 


BBBBBBBBBBBBBBBBP «bBBb| 

■s!8!i@s3ss!;sa 
S iiiiisiisssiissisSsssI 


LOAD CAPACITANCE (C L )— pF 
Fig. 14. 7— Typ. transition time vs. Ci. 





CD4019A 


File No. 479 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, C L = 15 pF, and input rise and fall times = 20 ns 
Typical Temperature Coefficient for all values of Vqq = 0.3 %/°C (See Appendix for Waveforms) 


CHARACTERISTICS SYMBOLS 


Propagation Delay Time: 


TEST 

CONDITIONS 


CD4019AD.CD4019AK. 

CD4019AF 

CD4019AE 

Min. 

Typ. 

Max. 

Min. 

Typ. 

j Max. 

- 

100 

225 

- 

100 

300 

- 

50 

100 

- 

50 

125 


ICHARAC- | 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 
Fig. No. 












File No. 479 


Digital Integrated Circuits 

Monolithic Silicon 

CD4020AD, CD4020AF 
CD4020AE, CD4020AK 



COS/MOS 

14-Stage Ripple-Carry 

Binary Counter/Divider 

Special Features 

■ Medium speed operation 7 MHz (typ.) at Vqd — V SS = 10 V 

■ Low "high"- and "low"-level output impedance 100012 (typ.) at 

VDD -vss = io V 

n MSI complexity on a single chip 14 fully static, master-slave stages 

■ COS/MOS gate-input loading at both Reset and Input-pulse lines 


CD4020A types consist of a pulse input shaping circuit, reset 
line driver circuitry, and 14 ripple-carry binary counter 
stages. Buffered outputs are externally available from stages 
1, and 4 through 14. The counter is reset to its "all zeroes" 
state by a high level on the reset inverter input line. Each 
counter stage is a static master-slave flip-flop. The counter is 
advanced one count on the negative-going transition of each 
input pulse. 


Applications 

■ Frequency-dividing circuits 
n Time-delay circuits 

■ Counter control 

■ Counting functions 


INPUT 

PULSE 



9-74 


109 









CD4020A 


File No. 479 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V SS <V, <V DD ) 

(Recommended DC Supply Voltage (Vqq — V 55) 3 to 15 V) 





— 

LIMITS 


CHARAC 

CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 

CD4020AD, CD4020AK, CD4020AF 

UNITS 

TERISTIC 

CURVES 

8. TEST 




ES 

ERR 





CIRCUITS 







K 223 




UUQI 


Kffli 



Fig. No. 

Quiescent Device 


■ 


5 

- 

- 

ma 

- 


BB 

- 


m 


m 

Current 


■ 

■ 

10 

- 

- 

sa 

- 

1 

sa 

- 

- 



Quiescent Device 
Dissipation 'Package 

Pd 


■ 

5 

- 

- 

sa 

- 

BB 

m 

- 

- 



m 



ra 

- 

- 

JjTjJ 

- 

10 


- 

- 

U 

Output Voltage 

VOL 

■ 


• 

- 

- 


- 

0 

SI 

- 

- 



■ 

Low Level 

■ 

■ 

H 

- 

- 


- 

0 

HjjH 

- 

- 

U 



High-Level 

VOH 

■ 

■ 

» 

ESI 

- 

- 

HSi 

5 

- 

IBM 

- 

- 

n 

UHU 

■ 

■ 

m 


- 

- 


wm 

- 

HU 

- 

- 

■ 


Noise Immunity 

Vnl 

■ 


D 

m 

- 

- 

JEM 


- 

BB 

- 

- 

mm 

JEM 

(Any Input) 

I 

m 

IB 

m 

- 

- 



- 

SB 

- 

- 


For Definition, 

See Appendix 

Vnh 


m 

El 

m 

- 

- 



- 


- 

- 

m 

m 


m 

IB 

m 

- 

- 

3 


- 

SB 

- 

- 

m 

Output Drive Current: 

'|qN 


m 

n 

pm 

- 

- 



- 

u 

- 

- 

m 

■ ■ 

N-Channel 



IB 


- 

- 

ESI 

0.4 

- 


- 

- 

1 1 

P Channel 

'dP 



H 


- 

- 


B 2 I 

- 


- 

- 


BB 


ES 

IB 


- 

- 


m 

- 


- 

- 

| 

Input Current 

ll 



- . 

- 

_ 

10 


__ 

- 

- 

pA 

■SB 


♦ See Appendix. 



Fig. 15.2 — Schematic diagram of pulse shapers and 1 of 14 binary stages. 


110 












File No. 479 


CD4020A 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < V , < V DD ) 

(Recommended DC Supply Voltage (Vpp — Vgg) 3 to 15 V) 






LIMITS 


CHARAC 













TERISTIC 

CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 



CD4020AE 




CURVES 

& TEST 




V 0 


-40°C 

25°C 

85°C 


CIRCUITS 




Volts 




Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 


Fig. No. 

Quiescent Device 




D 



50 


1 

m 



0Q| 



Current 




10 



100 


m 

HI 



BSE 

Quiescent Device 

Pd 



B 



250 


m 

Hi 






Dissipation 'Package 



m 



1000 





- 


Output Voltage 

V 0L 



5 



001 


0 

EHI 



i0^ 



Low Level 



B 

Hi 


001 


0 







High-Level 

VOH 




BUM 



001 

B 


HU 


- 





B 


■ 



B 







Noise Immunity 

VNL 


0.8 

B 


■ 


1 5 

2 25 


1.4 




15.12 

(Any Input) 


1.0 

B 





B 

Hi 




For Definition. 

See Appendix 

VNH 


4.2 

m 





H 






15.13 


9.0 

B 

Bl 




B 






Output Drive Current 

'i d n 


0.5 

B 




gg| 


■ 



- 


■ 1 

N-Channel 


0.5 

B 




HI 

B 

B 



- 


I I 

P Channel 

•dp 


4.5 

B 






■ 





I Bl 


9.5 

B 










H m\ 

Input Current 

ll 


_j 





Bi 





- 


♦ See Appendix. 


. 

M 

</> 

S >o 

1 

< 

d 

2 

z 

2 5 
o 

AMBIENT TEMPERATURE (T A ) ■> 25°C E 

TYPICAL TEMPERATURE COEFFICIENT FOR I D = - 0.3% /°C Z 




M M 






































1 II II II II II II 1 II 1 II 1 II M 1 



















GATE - TO- SOURCE VOLTS (Vnc) = 15 





































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0 5 10 15 

DRAIN -TO -SOURCE VOLTS (V DS ) 

92CS-I78I3 


DRAIN -TO-SOURCE VOLTS (Vqs) 

-15 -10 M5 0 

















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AMBIENT TEMPERATURE (T A )=25°C 

TYPICAL TEMPERATURE COEFFICIENT FOR I 0 = -0.3%/ # C 


92CS-I78I4 


Fig. 15-3— Typ. n-channel drain characteristics. 


Fig. 15.4— Typ. p-channel drain characteristics. 








CD4020A 


File No. 479 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, C L » 15 pF, and input rise and fall times » 20 ns except t,CL, tfCL 
Typical Temperature Coefficient for all values of Vqq = 0.3 %/°C . (See Appendix for Waveforms) 


CHARACTERISTICS 

SYMBOLS 


LIMITS 

UNITS 

CHARAC- 

TERISTIC 

CURVES 

& TEST 

CIRCUITS 
Fig. No. 

TEST 

CONDITIONS 

CD4020AD 

CD4020AK 

CD4020AF 

CD4020AE 


V DD 

(Volts) 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

CLOCKED OPERATION | 

Propagation Delay Time: 

t PHL = 
t PLH 


5 

- 

450 

600 

- 

450 

650 

ns 

15.7 

10 

- 

150 

225 

- 

150 

250 

Transition Time 

l THL = 
*TLH 


5 

- 

450 

600 

- 

450 

650 

ns 

15.8 

10 

- 

200 

300 

- 

200 

350 

Minimum Clock 

Pulse Width 

l WL = 

*WH 


5 

- 

200 

335 

- 

200 

500 

ns 

" 

10 

“ 

70 

125 

- 

70 

165 

Clock 

Rise & Fall Time 

VCL = 
x fCL 


5 



15 

- 


15 

PS 

- 

10 



15 

Z_ 

- 

15 

Maximum Clock 

Frequency 

f CL 


5 

1.5 

2.5 

- 

1 

2.5 

- 

MHz 

15.9 

10 

4 

7 

- 

3 

7 

- 

Input Capacitance 

C| 

Any Input 

- 

5 

- 

- 

5 

- 

PF 

- 

RESET OPERATION j 

Propagation Delay Time: 

tPHLIR) 


5 

- 

2000 

3000 


2000 

3500 

ns 

15.7 

10 

- 

500 

775 

- 

500 

900 

Minimum Reset 

Pulse Width 

X \NH(B) 


5 

- 

1800 

2500 

- 

1800 

3000 

ns 

- 

10 

- 

300 

475 

- 

300 

550 


'Propagation Delay is from clock input to Q-j output. 


DRAIN -TO- SOURCE VOLTS (V DS ) 




Fig. 15.5— Min. n-channel drain characteristics. 


Fig. 15.6— Min. p-channel drain characteristics. 





PROPAGATION DELAY TIME (tpHL st PLH> 



3 








File No. 479 


Digital Integrated Circuits 

Monolithic Silicon 

CD4021AD, CD4021AF 
CD4021AE, CD4021AK 



COS/MOS 8-Stage 
Static Shift Register 

Asynchronous Parallel Input/Serial Output, 
Synchronous Serial Input/Serial Output 


Special Features 

■ Asynchronous parallel or synchronous serial operation under control of 
parallel/serial control-input 

■ Individual "jam" inputs to each register stage 

■ Master-slave flip-flop register stages 

■ Fully static operation DC to 5 MHz 


CD4021A types are 8-stage parallel or serial-input/serial- 
output shift registers having common Clock and Parallel/ 
Serial Control inputs, a single Serial Data input, and 
individual parallel "Jam" inputs to each register stage. Each 
register stage is a D-type, master-slave flip-flop. "Q" outputs 
are available from the sixth, seventh, and eighth stages. 

When the parallel/Serial Control input is "low", data is 
serially shifted into the 8-stage register synchronously with 
the positive-going transition of the Clock pulse. 


Applications 

■ Asynchronous parallel input/serial output data queueing 

■ Parallel to serial data conversion ■ General purpose register 

When the Parallel/Serial Control input is "high", data is 
jammed into the 8-stage register via the parallel input lines 
asynchronously with the clock line. 

Register expansion is possible using additional CD4021A 
packages. 



10-73 









File No. 479 


CD4021A 



£ 


CL 



Fig. 16.2— One typical stage and its equivalent 
detailed circuit. 




Fig. 16.3 —Schematic diagram — CD4021A. 


115 










CD4021A 


File No. 479 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < V, < V DD ) 

(Recommended DC Supply Voltage (Vqq — V§s) 3 to 15 V) 



TEST 

CONDITIONS 


CD4021 AD. CD4021AK, CD4021AF 
























CD4021A 


File No. 479 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, C L = 15 pF and input rise and fall times = 20 ns except t r CL, t f CL 
Typical Temperature Coefficient for all values of Vqq = 0.3%/°C. (See Appendix for Waveforms) 


LIMITS 


CHARACTERISTICS 


Propagation Delay Time 


Transition Time 


Minimum Clock Pulse ty\i[_ = 

Width t\/\/H 

Minimum High-Level 
Parallel/Serial Control t WH(P/S) 

Pulse Width 



Maximum Clock 
Frequency 

Input Capacitance 


TEST 

CONDITIONS 


CD4021AD 

CD4021AK 

CD4021AF 


Any Input 


lock or Parallel/Serial Control Input 


Typ. 

Max. 

Min. 

Typ. Max. 

300 

750 

- 

300 1000 

100 

225 

- 

100 300 

150 

300 

- 

150 400 

75 

125 

- 

75 150 

200 

500 

- 

200 830 

100 

175 

- 

100 200 

200 

500 

- 

200 830 

100 

175 

- 

100 200 

- 

15 

- 

15 






15 

— 

— 15 


~ 




CHARAC- 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 
Fig. No. 




' If more than one unit is cascaded in a parallel clocked operation, 
t r CL should be made less than or equal to the sum of the fixed 
propagation delay time at 15pF and the transition time of the 
output driving stage for the estimated capacitive load. 




1.5 V OR 3V 
92CS-I792I 


Test performed with the following sequence 
of "One's" and "Zero's". 

S 1 s 2 s 3 s 4 s 5 
0 0 10 0 
10 111 
10 10 1 
0 1111 
0 10 0 0 

Fig. 16.8— Quiescent device current test circuit. 


Fig. 16.9— Noise immunity test circuit. 









File No. 479 


Digital Integrated Circuits 

Monolithic Silicon 

CD4022AD, CD4022AF 
CD4022AE, CD4022AK 



COS MOS Divide -By-8 

C©u sates 3 / Dav ader 

with 8 Decoded Outputs 

Special Features 

■ Medium speed operation 5 MHz (typ.) at VpD — Vss = 10 V 

■ MSI complexity on a single chip 

■ Divide by N counting; N = 2 to 8 with one CD4022A plus one CD4001 A, 
package 

Applications 

■ Binary frequency division 

■ Binary counting/decoding ■ Binary counter control/timers 


CD4022A types consist of a 4-stage divide-by-8 Johnson 
counter, associated decode output gating and a carry-out bit. 
The counter is cleared to its zero count by a "high" reset 
signal. The counter is advanced on the positive clock-signal 
transition provided the clock enable signal is "low”. 

Use of the Johnson divide-by-8 counter configuration 
permits high-speed operation, 2-input decode gating, and 


spike-free decoder outputs. Anti-lock gating is provided, thus 
assuring proper counting sequence. The 8 decode gating 
outputs are normally "low" and go "high" only at their 
respective decoded time slot. Each decode gate output 
remains "high" for one full clock cycle. The carry-out signal 
completes one cycle every 8 clock-input cycles and is used as 
a ripple-carry signal to directly clock a succeeding counter 
package in a multi-package counting system. 




Fig. 17. 1— Logic diagram. 


Fig. 17.2— Timing diagram. 


10-73 


119 








CD4022A 


File No. 479 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < V , < V DD ) 

(Recommended DC Supply Voltage (Vqq — Vgg) 3 to 15 V) 







LIMITS 


CHARAC 

CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 

CO4022AD, CD4022AK, CD4022AF 

UNITS 

TERISTIC 

CURVES 

& TEST 




v 0 

V DD 

-55°C 

25°C 

125°C 


CIRCUITS 




Volts 

Volts 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 


Fig. No. 

Quiescent Device 

Current 

'L 



5 

- 

- 

5 

- 

0.3 

5 

- 

- 

300 

HA 




10 

- 

- 

10 

- 

0.5 

10 

- 

- 

600 

17.9 

Quiescent Device 

PD 



5 

_ 

_ 

25 

_ 

1.5 

25 

_ 

- 

1500 

pW 


Dissipation/Package 



10 

- 

- 

100 

- 

5 

100 

- 

- 

6000 

_ 

Output Voltage: 

VOL 



5 

- 

- 

0.01 

- 

0 

0.01 

- 

- 

0.05 



Low-Level 



10 

- 

- 

0.01 

- 

0 

0.01 

- 

- 

0.05 



High-Level 

v OH 



5 

4.99 

- 

- 

4.99 

5 

- 

4.95 

- 

- 





10 

9.99 

- 

- 

9.99 

10 

- 

9.95 

- 

- 



Noise Immunity 

vnl 


0.8 

5 

1.5 


- 

1.5 

2.25 

- 

1.4 





(Any Input) 

For Definition. 

See Appendix 


1.0 

10 

3 

- 


3 

4.5 

- 

2.9 


- 


17.10 

v N h 


4.2 

5 

1.4 

- 

- 

1.5 

2.25 

- 

1.5 


- 




9.0 

10 

2.9 

- 


3 

4.5 

- 

3 


- 



Output Drive 

Current 

N-Channel 


Decoded 

Outputs 

0.5 

5 

0.062 

- 

- 

0.05 

0.15 

- 

0.035 

- 

- 

| 

MB 

•d n 

0.5 

10 

0.12 

- 

- 

0.1 

0.3 

- 

0.07 

- 

- 


■ ■ 

Carry 

Output 

0.5 

5 

0.185 

- 

- 

on 

m 

- 

0.105 

- 

- 

■ 

B 



0.5 

10 

0.375 

- 

- 

EH 

1 

- 




R 

1 



Decoded 

Outputs 

4.5 

5 

•0.038 

- 

- 



- 


- 

n 

■ 

H| H 

P-Channel 

i d p 

9.5 

10 

SSI 

- 

- 

QS 


- 


- 

m 


IU 


Carry 

Output 

4.5 

5 

BS5 

- 

- 

03 

ezi 

- 


- 


IhtB 



9.5 

10 

SSI 

- 

- 

ESI 

ESI 

- 



HI 

■ 


Input Current 

l \ 


- 

- 

- 

- 

10 

- 

■ 


B 

m 

BBB 


♦ See Appendix. 




120 


Fig. 17.3— Typ. propagation delay time vs. C[_ 
for decoded outputs. 


Fig. 17.4— Typ. propagation delay time vs. C[_ 
for carry output. 




File No. 479 CD4022A 

STATIC ELECTRICAL CHARACTERISTICS (All inputs Vss^V^Vdd) 

(Recommended DC Supply Voltage (V DD - V S s) 3 to 15 V) 







LIMITS 


CHARAC 

CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 

CD4022AE 

UNITS 

TERISTIC 

CURVES 

& TEST 




v 0 

V DD 

! — 40°C 

25° C 

85°C 


CIRCUITS 




Voltt 

Volts 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 


Fig. No. 

Quiescent Device 

Current 

lL 



5 

- 

- 

50 

- 

0.5 

50 

- 

- 

700 

PA 




10 

- 

- 

100 

- 

1 

100 

- 

- 

1400 

17.9 

Quiescent Device 
Dissipation/Package 

PD 



5 

_ 

_ 

250 

- 

2.5 

250 

_ 

_ 

3500 

p\N 




10 

- 

- 

1000 

- 

10 

1000 

- 

- 

14000 

“ 

Output Voltage: 

V 0L 



5 

- 

- 

0.01 

- 

0 

0.01 

- 

_ 

0.05 



Low-Level 



10 

- 


0.01 


0 

0.01 

- 

- 

0.05 



High-Level 

VOH 



5 

4.99 

- 

- 

4.99 

5 

- 

4.95 

- 

- 





10 

9.99 

- 

- 

9.99 

10 

- 

9.95 

- 

- 



Noise Immunity 

V/fva > 


0.8 

5 

15 

- 

- 

1.5 

2.25 

- 

1.4 


- 

\J 


(Any Input) 

For Definition. 

See Appendix 

v NL 


1.0 

10 

3 


- 

3 

4.5 

- 

2.9 

- 



17.10 

Vmu 


4.2 

5 

1.4 

- 

- 

1.5 

2.25 

- 

1.5 

- 

- 



V NH 


9.0 

10 

2.9 



3 

4.5 

- 

3 





Output Drive 

Current 


Decoded 

Outputs 

0.5 

5 

0.03 



0.025 

0.15 

- 

0.02 

- 




i d n 

0.5 

10 

0.06 



0.05 

0.3 

- 

0.04 


- 

mA 


N* Channel 

Carry 

Output 

0.5 

5 

0.095 

- 

- 

6.08 

0.5 

- 

0.065 

- 

- 




0.5 

10 

0.155 



0.13 

1 

- 

0.105 

- 

- 





Decoded 

Outputs 

4.5 

5 

-0.018 


- 

-0.015 

-0.075 

- 

-0.012 

- 

- 



P-Channel 

l D p 

9.5 

10 

-0.06 

! - 

- 

-0.05 

-0.15 

- 

-0.04 

- 

- 

mA 



Carry 

Output 

4.5 

5 

-0.095 


- 

-0.08 

-0.4 

- 

-0.065 


- 




9.5 

10 

-0.155 

- 

- 

-0.13 

-0.8 

- 

-0.105 

- 

- 



Input Current 

ll 


- 




10 

- 




pA 



♦ See Appendix. 




Fig.17.5—Typ. transition time vs. C{_ for 
decoded outputs. 


Fig.17.6—Typ. transition time vs. C[_ for 
carry output. 


121 




CLOCK INPUT FREQUENCY (f CL )-MHz 


CD4022A 


File No. 479 









File No. 479 


CD4022A 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Cl = 15 pF, and input rise and fall times = 20 ns except t r CL f tfCL 
Typical Temperature Coefficient for all values of Vqq = 0.3%/°C (See Appendix for Waveforms) 





LIMITS 


CHARAC 

CHARACTERISTICS 

SYMBOLS 

TEST 

CONDITIONS 

CD4022AD.CD4022AK 

CD4022AF 

CD4022AE 

UNITS 

TERISTIC 

CURVES 

& TEST 




V DD 

(Volts) 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 


CIRCUITS 
Fig. No. 

| CLOCKED OPERATION | 

Propagation Delay Time: 



5 

- 

325 

1000 

- 

325 

1300 

ns 

17.4 

Carry-Out Line 

tpHL* 


10 

- 

125 

250 

- 

125 

500 

Decode Out Lines 

t PLH 


5 

- 

400 

1200 

- 

400 

1600 

ns 

17.3 



10 

- 

200 

400 

- 

200 

800 

Transition Time: 



5 

- 

85 

300 

- 

85 

340 

ns 

17.6 

Carry-Out Line 

l THL' 


10 

- 

50 

100 

- 

50 

200 

Decode-Out Lines 

*TLH 


5 

- 

300 

900 

- 

300 

1200 

ns 

17.5 



10 

- 

125 

250 

- 

125 

500 

Minimum Clock 

tWL' 


5 

- 

250 

500 

- 

250 

830 

ns 

17.11 

Pulse Width 

% H 


10 

- 

85 

170 

- 

85 

250 

Clock 

x rCL' 


5 

- 

- 

15 

- 

- 

15 

s 

17.11 

Rise & Fall Time 

l fCL 


10 


- 

15 

- 

- 

15 

Clock Enable Set-Up Time 



5 

350 

175 

- 

700 

175 

- 

ns 

17.12 



10 

150 

75 

- 

300 

75 

- 

Maximum Clock 

f CL 


5 

1 

2.5 

- 

0.6 

2.5 

- 

MHz 

17.7 

Frequency 


10 

3 

5 

- 

2 

5 

- 

Input Capacitance 

C| 

Any Input 

- 

5 

i 

- 

5 

- 

pF 

- 

RESET OPERATION 


Propagation Delay Time: 

X PHL> 


5 

- 

300 

900 

- 

300 

1200 



Carry-Out Line 

tPLH 


10 

- 

125 

250 

- 

125 

500 



Decode-Out Line 



5 

- 

500 

1250 

- 

500 

2500 

ns 




10 

- 

200 

400 

- 

200 

800 


Minimum Reset Pulse 

twL' 


5 

- 

150 

300 

- 

150 

600 

ns 

17.13 

Width 

%H 


10 

- 

75 

150 

- 

75 

300 


123 




File No. 503 


MBUQ 

Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4024AD,CD4024AE,CD4024AF 

CD4024AK,CD4024AT 



COS/MOS 7-Stage Binary Counter 

With Buffered Reset 
Special Features: 

■ Medium speed operation 7 MHz (typ.) input pulse rate at 

vdd-Vss = 10 V 

■ Low "high" and "low" level output impedance 70012 and 

50012 (typ.), respectively at Vdd - ^SS -10 V 

■ Logic block complexity on a single chip each output 

accessible and resettable 

h Static counter operation — counter retains state indefinitely 
with input pulse level "low" or "high" 

■ COS/MOS gate input loading on both reset and input- pulse lines 


The CD4024A types consist of an input pulse shaping 
circuit, reset line driver circuitry, and seven binary counter 
stages. The counter is reset to "zero" by a high level on the 
reset input. Each counter stage is a static master-slave 
flip-flop. The counter state is advanced one count on the 
negative-going transition of each input pulse. 

* Formerly developmental type TA5385C. 


Applications: 

■ Frequency-dividing circuits 

■ Time-delay circuits 

■ Counter control 

■ D/A counter and switch on one chip 



Fig. 1-1 — Functional diagram for CD4024AD, AK. AE, AF. 



Fig. 1-2 — Functional diagram for CD4024A T. 


124 


9-74 







File No. 503 


CD4024A 



NOTE: SUBSTRATES FOR ALL "P” UNITS ARE CONNECTED TO V DD 

SUBSTRATES FOR ALL "N" UNITS, UNLESS OTHERWISE SHOWN, ARE CONNECTED TO GROUND. 

Fig. 1-3 — Schematic diagram (pulse shape / and 1 binary stage). 



125 







CD4024A 


File No. 503 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < V, < V DD ) 

(Recommended DC Supply Voltage (Vpp — Vgg) 3 to 15 V) 








CHARAC 

CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 

CD4024AD, CD4024AK, CD4024AT, CD4024AF 

UNITS 

TERISTIC 

CURVES 
& TEST 




El 


BHB^SBBt 

m 

iSBEZ^B 


CIRCUITS 







ESI 

■233 


■23 


I2H 


■33 


Fig. No. 

Quiescent Device 

Current 


■ 


5 

- 

- 

5 

- 

EB 

5 

- 


m 


1-13 


■ 

■ 

10 

- 

- 

mi 

- 


mm 

- 

- 

600 


Quiescent Device 

Pd 

■ 

■ 

B 






WM 

- 

- 




Dissipation/Package 

■ 

■ 

m 

- 

- 


- 

5 


- 

- 

gm 


Output Voltage: 


■ 

■ 

B 

_ 

- 

ms 

- 

0 


- 

- 

mi 



Low-Level 

■ 

■ 

,0 

- 

- 

12 m 

- 

0 

l^jl 

- 

- 




High-Level 

rag2§§§§ 


■ 

B 


- 



5 

- 

mi 

- 

- 




■ 

B 

mm 

- 

- 


IB 

- 


- 

- 



Noise Immunity 

■ 


m 

* 

IB 

- 

- 

IB 

QUjj 

U3 

1 , 

- 

- 


1-14 

(Any Input) 


m 

B 

3 

- 

- 

a 

a 

mu 

a 

- 

- 





m 

• 

1.4 

- 

- 

a 


mu 


- 

- 


1-15 



m 

B 

BB 

- 

- 

3 

a 

mi 

3 


- 


Output Drive Current: 



EB 

* 

QBQH 

- 

- 



- 

33E3 

- 

- 


m 

N-Channel 

IdN 


m 

B 


- 

- 

mm 

1 

- 


- 

- 

■S3 

P-Channel 




B 

om 

- 

- 

mm 

mm$ 

- 

nm 

- 

- 


bb 



EB 

B 

mm 

- 

- 


a 

- 

a 

- 

- 

WBm 


'l 


_ 

_ 

- 

- 

_ 

10 

- 

_ 


- 

pA 

I^B 


For Output Drive Current test connections see Appendix. 



AMBIENT TEMPERATURE (T A )*25 °C 

i. 

























z_ 














-- 






GATE-TO-SOURCE VOLTS <V r . c )« 15 

- 


















— 













n 


__ 










_L 




to 




-- 









* 

i 

" 




3 

T 






- 




tr 







■ 

IBI 


t 



_ 

J 
















a lu 







■ 

111 

n 



I 


■ 

:: 















< 







f A 

n 

t 





a 

■ Bl 















-j 







-f 

in 

■ 





a 

±t 















I 







■■ 

■j 

■■i 

iai 

■ 

■ 





a 

E 

■a 

2a 















z 

£ 5 






p 

a 

■i 





j = 


a 

a 

■a 

■a 

IB 

IB 











; = 



0 







T 








:: 












iz 






f 




-T 


-1 






-- 

_ 


: 

I 








-- 






i 


- 



iai 

iai 

ii 

■ 

■ 


-- 



-- 

-- 


z 

4 








j- 






11 


= - 


T 


-- 

- 


-- 



■ai 

■a 

- 

a 

a 

ai 

ai 












e 

H 

± 


-- 

- 

4 


-- 

- 


-- 

- 


5 

± 

- 

a 

a 













0 5 10 15 

DRAIN-TO- SOURCE VOLTS (V DS ) 

92CS- 1 7809 


Fig. 1—5 Typ. N-channel drain characteristics. 


DRAIN -TO -SOURCE VOLTS IV DS ) 



92CS- 17934 

Fig. 1—6 Typ. P-channel drain characteristics. 


126 















DRAIN MILLIAMPERES (I 


File No. 503 


CD4024A 


STATIC ELECTRICAL CHARACTERISTICS (All inputs 

(Recommended DC Supply Voltage (Vpp — Vgs) 


Vss< v | < V DD> 
3 to 15 V) 



DRAIN-TO-SOURCE VOLTS (V os ) 


Fig. 1—7 Min. N -channel drain characteristics. 


Fig. 1,-8 Min. P-channel drain characteristics. 








CD4024A 


File No. 503 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Vgg = OV, C L = 15pF, and Input rise and fall times = 20ns, except t r ^ and tf^ 
Typical Temperature Coefficient for all values of V DD = 0 .3%/°C. (See Appendix for Waveforms) 





LIMITS 


CHARAC- 
TERISTIC 
CURVES 
& TEST 

CHARACTERISTICS 

SYMBOLS 

TEST CONDITIONS 

CD4024AD, CD4024AK 
CD4024AT. CD4024AF 


CD4024AE 

UNITS 




VDD 

(Volts) 









CIRCUITS 
Fig. No. 




Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 


0 INPUT OPERATION 

Propagation Delay Time* 

VHL' 


5 

- 

175 

350 

- 

175 

400 

ns 

1-9 

*plh 


10 

- 

80 

150 

- 

80 

150 

Transition Time 

^HL' 


5 

- 

175 



HI 

Eini$ 

ns 

1-10 

*TLH 


■a 

HI 

80 



B 






HI 

EE1 

EE9 

ESI 


823E 

ns 






in 


125 

- 


165 



EH 


5 

- 

- 

15 

- 

- 

15 

JUS 



Vm 


10 

- 

- 


- 

- 

10 


Maximum Input Pulse 



5 

1.5 

2.5 

- 

i 

2.5 

- 


1-12 

Frequency 

Yt> 


mm 

4 

7 

- 

3 

7 

- 


Input Capacitance 

QH 


- 

5 

- 

- 

5 

- 

PF 

- 


Propagation Delay Time 

tpHLIR) 


5 





ICJl 





mm 


ESI 







Minimum Reset 



5 

- 

375 

500 

- 

375 

600 

ns 


Pulse Width 

X \NH{H) 


10 

- 

200 

300 

- 

200 

350 



* Propagation delay time is from clock input to Q-| output. 




128 


















File No. 503 


CD4024A 




Fig. 1—12 Typ. input pulse frequency vs. Vqq. 



92CS-I7896 

Fig. 1—13 Quiescent device current test circuit. 



Fig. 1-14 Noise Immunity 
test circuit. 


5V OR IOV 



92CS- I7898RI 


Fig. 1—15 Reset noise immunity 
test circuit. 


129 





File No. 503 



Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4026A, CD4033A 

Types 



voo 



■ 

2L 

pSL.'l 


CLOCK 






— 6 

z 

2 


13 c 


CLOCK 



° 

ENABLE 


2_d 

. 2 

IS 



O 

RESET 


— • 

Q 




K 



f-cA 






3 


4 


Display 


DISPLAY 

enable 


ENABLE 

in 


OUT 




ungated'c" 


SEGMENT OUT 

CD4026A vss 




COS/MOS Decade Counters/Dividers 

With Decoded 7-Segment Display Outputs and: 

Display Enable - CD4026AD, AE, AF, AK 

Ripple Blanking - CD4033AD, AE, AF, AK *»• 


Special Features: 

■ Counter and 7-segment decoding in one package 

■ Ideal for low-power displays 

■ Easily interfaced with 7-segment display types 

o Fully static counter operation: DC to 2.5 MHz (typ.) 

■ Display Enable Output (CD4026A) 

■ "Ripple Blanking" and Lamp Test (CD4033A) 


RCA CD4026A and CD4033 A a each consists of a 5-stage 
Johnson decade counter and an output decoder which 
converts the Johnson code to a 7-segment decoded output 
for driving each stage in a numerical display. 

These devices are particularly advantageous in display appli- 
cations where low power dissipation and/or low package 
count are important. 


Applications: CD4033 A Vss 

■ Decade counting/7-segment decimal display 

■ Frequency division/7-segment decimal displays 

■ Clock/watches/timers (e.g. -f 60, -r 60, -M2 counter /display) 

■ Counter/display driver for meter applications 


Inputs common to both types are Clock, Reset, & Clock 
Enable; common outputs are Carry Out and the seven 
decoded outputs (a, b, c, d, e, f, g). Additional inputs and 
outputs for the CD4026A include Display Enable input and 
Display Enable and Ungated "C-segment" outputs. Signals 
peculiar to the CD4033 are Ripple-Blanking and Lamp Test 
inputs and a Ripple-Blanking Output. 

A “high" Reset signal clears the decade counter to its zero 
count. The counter is advanced one count at the positive 
clock signal transistion if the Clock Enable signal is "low". 
Counter advancement via the clock line is inhibited when the 
Clock Enable signal is "high”. Antilock gating is provided on 
the Johnson counter, thus assuring proper counting 
sequence. The Carry-Out (C ou t) signal completes one cycle 
every ten clock input cycles and is used to directly clock the 
succeeding decade in a multi-decade counting chain. 

The seven decoded outputs (a, b, c, d, e, f, g) illuminate the 
proper segments in a seven segment display device used for 
representing the decimal number 0 to 9. The 7-segment 
outputs go "high" on selection in the CD4033A; in the 
CD4026A these outputs go "high" only when the Display 
Enable IN is "high". 


A Formerly developmental type TA5677. 


CD 402 6 A 

When the Display Enable I N is"l_ow"the seven decoded outputs 
are forced "low" regardless of the state of the counter. 
Activation of the display only when required results in 
significant power savings. This system also facilitates imple- 
mentation of display-character multiplexing. 

The Carry Out and ungated "C-segment" signals are not 
gated by the Display Enable and therefore are available 
continuously. This feature is a requirement in imple- 
mentation of certain divider functions such as divide-by-60 
and divide-by-12. 

CD4033A 

The CD4033A has provisions for automatic blanking of the 
non significant zeros in a multi-digit decimal number which 
results in an easily readable display, consistent with normal 
writing practice. For example, the number 0050.07000 in an 
eight digit display would be displayed as 50.07. Zero 
suppression on the integer side is obtained by connecting the 
RBI terminal of the CD4033A associated with the most 
significant digit in the display to a "low-level" voltage and 
connecting the RBO terminal of that stage to the RBI 
terminal of the CD4033A in the next-lower significant 


130 


9-74 





File No. 503 


CD4026A, CD4033A 



Fig.2— 1 CD4026A logic diagram. 


position in the display. This procedure is continued for each 
succeeding CD4033A on the integer side of the display 

On the fraction side of the display the RBI of the CD4033A 
associated with the least significent bit is connected to a 
"low level" voltage and the RBO of that CD4033A is 
connected to the RBI terminal of the CD4033A in the next 
more-significant-bit position. Again, this procedure is 
continued for all CD4033A's on the fraction side of the 
display. 

In a purely fractional number the zero immediately pre- 
ceding the decimal point can be displayed by connecting the 
RBI of that stage to a "high level" voltage (instead of to the 
RBO of the next more-significant-stage). For Example: 
optional zero *0.7346. 

Likewise, the zero in a number such as 763.0 can be 
displayed by connecting the RBI of the CD4033A associated 
with it to a "high-level" voltage. 

Ripple blanking of non-significant zeros provides an ap- 
preciable savings in display power. 

The CD4033A has a "Lamp Test" input which, when 
connected to a "high-level" voltage, overrides normal de- 
coder operation and enables a check to be made on possible 
display malfunctions by putting the seven outputs in the 
"high" state. 



Fig. 2-2 — CD4026A timing diagram. 


For maximum ratings, see page 22. 


131 











CD4026A, CD4033A 


File No. 503 


STATIC ELECTRICAL CHARACTERISTICS (All inputs Vss < V , < V DD ) 

(Recommended DC Supply Voltage (Vqq — V§s> 3 to 15 V) 


CD4026AD, CD4026AK ,CD4026AF 
CD4033AD, CD4033AK, CD4033AF 


CHARAC- 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 


HA 






Fig.2— 12 Max. input dock frequency 
V DD- 












File No. 503 


CD4026A, CD4033A 


STATIC ELECTRICAL CHARACTERISTICS (All inputs Vss^V!<V DD ) 

(Recommended DC Supply Voltage (Vqq — V 53) 3 to 15 V) 


CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 

LIMITS 

UNITS 

CHARAC- 

TERISTIC 

CURVES 

& TEST 
CIRCUITS 

Fig. No. 

CD4026AE, CD4033AE 


v 0 

Volts 

V DD 

Volts 

| — 40°C 

25°C 

85°C 

IftUH 

EjQH 


I2EB 

PEB 





Quiescent Device 

Current 

lL 



D 


■ 



g 




19 

pA 

2-14 

10 

- 

- 

itJ 


- 

na 

- 

- 


Quiescent Device 
Dissipation/Package 

PD 



5 

- 

- 


■ 

m 


_ 

- 


pW 


10 

- 

- 

1000 


E9 


- 

- 


Output Voltage: 

Low-Level 

VOL 


■ 

■3 

- 

- 



0 

BB1 

- 

- 




11 

- 

- 



0 


- 

- 

ggj 

High-Level 

VOH 



H 

El 

- 

- 


5 

- 


- 

- 



O 


- 

- 


II 

- 


- 

- 

Noise Immunity 
(All Inputs) 

VNL 


m 

m 

i m 

H9 

- 

IB 


- 

IB 

- 

- 

B 


m 

11 


- 

- 

3 

m 

- 

B! 

- 

- 

Vnh 


n 

1.4 

- 

- 

IB 

EH 

- 

IB 

- 

- 


m 

m 

El 

- 

- 

11 

m 

- 


- 

- 

Output Drive Current: 

N-Channel 

'd n 

Decoded 

Outputs 

E9 

n 


- 

- 

ESI 


- 


- 

- 




0 

HU 

- 

- 

QQj 


- 

EB 

- 

- 

Carry 

Output 

0.5 

5 

0.095 

- 

- 


eb 

- 


- 

- 

■ 

0.5 

10 

El 

- 

- 


1 

- 

EB 

- 

- 

P-Channel 


||§ 

ta 

■a 


- 

- 


5^3 

- 

mum 

- 

- 


m 


m 

e m 

- 

- 


m 

- 

QQj 

- 

- 


m 

B 

SES 

- 

- 

JjJj 

EB 

- 


- 

- 

- 

B3 

n 

ESI 

- 

- 

■jgyi 

-1 

- 

SB 

- 

- 

Input Current 

'l 


■ 


- 

- 

u_ 

10 

- 


- 

- 

pA 



For Output Drive Current test connections see Appendix. 



92CS-I7829RI 

Fig.2-13 Typ. dissipation characteristics. 


10 V 



Fig.2- 14 Quiescent device current test circuit. 


135 














CD4026A, CD4033A 


File No. 503 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Vgg = OV, C L = 15pF, and input ri*« and fall times « 20ns, except t,CL and tfCL 
Typical Temperature Coefficient for all values of Vqq = 0.3%/°C. (See Appendix for Waveforms) 
























File No. 503 


CD4026A, CD4033A 


INTERFACING THE CD4026A AND CD4033A WITH COMMERCIALLY AVAILABLE 7-SEGMENT DISPLAY DEVICES 
(Refer to Application Note ICAN-6733for detailed interfacing information) 


LOW-POWER INCANDESCENT READOUTS 

PINLITES INC- Series 0 and R 


TUBE REQUIREMENTS: 
0-03-15 
0-04-30 
0-06-30 
R-R3-20 
R-R4-30 



V T (V) 

1.5 

3.0 

3.0 

2.0 

3.0 


ASSUMED 
TRANSISTOR 
CHARACTERISTICS 
/9dc (min.)> 30 
V C E(sat.)< 0-50V 


(®Vdd > 
<B 5 

it ^ 


CD4009A 

@V[)d = 10 V (min.). 

V 0 "0” < 0.6 V 
lj = 8 mA (min.) 

@ V DD = 6 V (min.) 
V o “0” < 1.0V 
Ij = 5mA (min.) 
V TO 3.5 V 


mA/ Segment 
8 
8 
8 

4.3 

4.3 


3.5 V (min.) 
0.25 mA (min.) 

7.5 mA (min.) 


INCANDESCENT READOUTS 

RCA Numitron- DR2000 Series 
TUBE REQUIREMENTS: 

V T = 3.5- 5.0 V 
Iq. = 24 mA /Segment 


ASSUMED 

TRANSISTOR 

CHARACTERISTICS 

$6c (min.) > 25 
VcE(sot.)< 0.50V 

( 5 ) Vqq = 8 V (min.) 

Ig = 1.0mA (min.) 
Ij = 24 mA (min.) 

CD4009A 

@Vdd = 10V (min.) 
V o “0” < 2 V 
If = 20 mA (min.) 
V T -3.5 VT0 6 V 

92CS-19133R2 


NEON READOUTS (NIXIE TUBE*) 

1. Alco Electronics— MG19 

2. Burroughs- B5971, B7971, B8971 

TUBE REQUIREMENTS V T (Vdc) m A/Segment 

Alco MG 19 180 0.5 

Burroughs B597 1 170 3 

” B7971, B8971. 170 6 



TRANSISTOR CHARACTERISTICS 
Leakage with transistor cutoff -0.05mA 
V (BR) CER *'• >V T 
/J(j c (min) - 30 

A (Trademark) Burroughs Corp. 


LOW-VOLTAGE VACUUM FLUORESCENT READOUTS 



1- Tung-Sol DIGIVAC S/G^Type DT1704A or DT1705C 


2. Nippon Electric (NEC)-Type DG12E or LD915 

TUBE REQUIREMENTS: 100 to 300 yu A/ seg- 
ment at tube voltages of 12 V to 25 V depending 
on required brightness. Filament requirement 
45 mA at 1.6 V, AC or DC. 


137 





CD4026A, CD4033A 


File No. 503 

INTERFACING THE CD4026A AND CD4033A WITH COMMERCIALLY AVAI LABLE 7-SEGMENT DISPLAY DEVICES 

(Refer to Application Note ICAN-6733 for detailed interfacing information) (cont'd.) 


LIGHT EMITTING DIODE DISPLAYS 


V DD 



VCE (SAT) < 0.5 V 

R - v 00-Vce(sotr v F<«- ED > 

Tled 

WHERE V F * FORWARD DROP ACROSS DIODE 



92CS- I9I37R3 




File No. 503 



Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4027AD, CD4027AE, CD4027AK 



COS/MOS Dual J-K 

Sias!e?=s§!aw@ tF8ias= F8 ©bs 

With Set/Reset Capability 
Special Features: 

■ Static flip-flop operation retains state indefinitely with clock level 

either "high" or "low" 

■ Medium speed operation 8 MHz (typ.) clock toggle rate at 

Vdd-Vss = iov 

b Low "high"-and "low" output impedance 70012 and 30012, 

Applications: respectively, at V DD -V SS - 10 V 

n Registers, counters, control circuits 


RCA CD4027A A is a single monolithic chip integrated circuit 
containing two identical complementary-symmetry "J-K" 
master- slave flip-flops. Each flip-flop has provisions for 
individual "J", "K", "Set", 'Tleset", and "Clock" input 
signals. Buffered "Q" and "Q" signals are provided as 
outputs. This input-output arrangement provides for com- 
patible operation with the RCA CD4013A dual "D"-type 
flip-flop. 

a Formerly developmental type TA5872. 


The CD4027A is useful in performing control, register, and 
toggle functions. Logic levels present at the "J" and "K" 
inputs along with internal self-steering control the state of 
each flip-flop; changes in the flip-flop state are synchronous 
with the positive-going transition of the "clock" pulse. Set 
and reset functions are independent of the clock and are 
initiated when a "high" level signal is present at either the 
"Set" or "Reset" input. 



10-73 


WHERE I * HIGH LEVEL 
0* LOW LEVEL 


92CM-I7I88R2 


139 









CD4027A 


File No. 503 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < V, < V DD ) 

(Recommended DC Supply Voltage (Vqq — Vgg) 3 to 15 V) 



. LIMITS 


CD4027AD, CD4027AK 



Noise Immunity 
(Any Input) 


Output Drive Current 

N-Channel 


Input Current I l ( 











- 

3 

4.5 


2.9 



- 

1.5 

2.25 

- 

1.5 

- 

- 

- 

3 

4.5 

- 

3.0 


- 

- 

0.5 

1 

- 

0.33 

_ 

- 

- 

1 

2.5 


07 

- 

- 

- 

-0.25 

-0.5 

- 

-0.175 

- 

- 

- 

-0.65 

-1.3 

- 

i-0.45 

- 

- 

- 

- 

10 

- 


- 

- 



DRAIN MILLIAMPERES (I D ) 






















File No. 503 CD4027A 

STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < V, < V DD ) 

(Recommended DC Supply Voltage (Vqq - Vgg) 3 to 15 V ) 


CHARACTERISTIC 

SYMBOL 


LIMITS 

UNITS 

CHARAC 

TERISTIC 

CURVES 

& TEST 

CIRCUITS 

Fig. No. 

TEST 

CONDITIONS 

CD4027AE 



os 





BOH 



PM 



BHB 


Quiescent Device 

Current 

lL 


■ 

* 

- 

- 

10 

- 


m 

- 

- 

m 



El 

- 

- 


- 

ya 


- 

- 

23 

Quiescent Device 
Dissipation/Package 



■ 

M 

_ 

_ 


_ 

QQI 


_ 

_ 

700 

pW 


10 


- 

|2J| 

- 

m 


- 

“ 


Output Voltage: 

Low-Level 

VOL 


■ 

B 


- 


- 

0 

EBI 

- 

- 


B 


B 


- 

BH 

- 

0 


- 

- 


High-Level 

VOH 


■ 

B 

Q 

- 

- 

BUI 

5 

- 

H1B 

- 

- 



B 


- 

- 


m 

- 


- 

- 

Noise Immunity 
(Any Input) 

VNL 

1 


m 

mm 

- 

- 

£jj 


- 

wm 

- 

- 


fl 

m 

B 



- 

3 

KB 

- 

m 

- 

- 



m 

B 

m 

- 

- 

Efl 


- 

m 

- 

- 



B 

2.9 

- 

- 

3 

£2 

- 


- 

- 

Output Drive Current: 

N-Channel 



B 

0.3 

- 

- 


i 



B 

- 

mA 

1 


10 

0.72 

■ 

B 


m 

B 

B 



P-Channel 



H 


B 

B 



B 


B 

fl 

mA 

3-3. 

3-5 



B 

B 

B 


1 

B 


B 

B 

Input Current 

'l 


_ 

- 


_ 

_ 

JL 

_ 

- 

_ 

- 

pA 



For Output Drive Current test connections see Appendix. 



DRAIN - TO - SOURCE VOLTS (V DS ) 



Fig. 3— 5 Min. P-channei drain characteristics. 


141 


















CD4027A File No. 503 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Vgg = OV, C L = 15pF, and Input rise and fall times - 20ns, except^CL and tfCL. 
Typical Temperature Coefficient for all values of Vqq = 0.3%/°C. (See Appendix for Waveforms) 


CHARACTERISTICS 

SYMBOLS 


LIMITS 

UNITS 

CHARAC- 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 

Fig. No. 

TEST CONDITIONS 

CD4027AD, CD4027AK 

CD4027AE 


VDD 

(Volts) 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Propagation Delay Time 

t PHL' 

Vlh 


5 

- 

150 

300 

- 

150 

400 

ns 

3-7 

10 

- 

75 

110 

- 

75 

150 

Transition Time 

^HL' 

*TLH 


5 

- 

75 

125 

- 

75 

250 

ns 

3-8 

10 

- 

50 

70 

- 

50 

140 

Minimum Clock Pulse Width 

%L' 

%H 


5 

- 

165 

330 

- 

165 

500 

ns 

- 

10 

- 

65 

110 

- 

65 

165 

Clock 

Rise & Fall Time 

** 

tCL' 

l iCL 


5 

- 

- 

15 

- 

- 

15 

Ids 

- 

10 

- 

- 

5 

- 

- 

5 

Set-Up Time 



5 

- 

70 

150 

- 

70 

200 

ns 

- 

10 

- 

25 

50 

- 

25 

75 

Maximum Clock Frequency 
(toggle mode) 

fCL 


5 

1.5 

3 

- 

1 

3 

- 

MHz 

3-9 

10 

4.5 

8 

- 

3 

8 

- 

Input Capacitance 

C l 



- 

■- 

5 

- 

- 

5 

- 

pF 

- 

SET & RESET OPERATION | 

Propagation Delay Time 

VhLIR)' 

t PLH(S) 


5 

- 

175 

225 

- 

175 

350 

ns 

- 

10 

- 

75 

110 

- 

75 

150 

Minimum Set and Reset 

Pulse Widths 

^HIS)' 

*WL(R) 


5 

- 

125 

200 

- 

125 

300 


- 

10 

- 

50 

80 

- 

50 

120 



* If more than one unit is cascaded in a parallel clocked operation, t r CL should be made less than or equal to 
the sum of the fixed propagation delay time at 15 pF and the transition time of the output driving stage 
for the estimated capacitive load. 




142 






SUPPLY VOLTS (V 0D ) 


INPUT FREQUENCY (f,)- Hz 


Fig. 3— 9 Max. clock frequency vs. supply 
voltage. 


Fig. 3— 10 Typ. dissipation characteristics. 


143 






CD4027A 


File No. 503 


K)V 



TEST PERFORMED WITH THE FOLLOWING 
LOGIC LEVELS PRESENT 

CL J K S R 

0 I I 0 I 

0 0 0 I I 

OOOIO 

1 0 0 I 0 

92CS-I9096 

Fig.3-12 — Quiescent device current test circuit. 



Fig.3-13 — Noise-immunity test circuit. 


144 









File No. 503 



Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4028AD, CD4028AF 
CD4028AE, CD4028AK 


3-BIT 

BINARY H 
INPUTS f 


BCD I 
INPUTS! 



BUFFERED 
OCTAL 
DECODED 
OUTPUTS 
( I OF 0 ) 


-BUFFERED 
DECIMAL 
DECODED 
OUTPUTS 
(I OF 10) 


VSS 

92CS — 19131 


COSMOS 

SCS°t®°5@ei9nal Decoder 

Special Features: 

■ BCD to decimal decoding or binary to octal decoding 

■ High decoded output drive capability 8 mA (typ.) sink or source 

■ "Positive logic" inputs and outputs decoded outputs go "high" on 

selection 

■ Medium speed operation tjHL» tjLH = 30 ns (typ.) @ 

v D d = 10 V 

Applications: 

■ Code conversion ■ Indicator-tube decoder 

■ Address decoding— memory selection control 


RCA CD4028A A types are BCD to decimal or binary to octal 
decoders consisting of pulse shaping circuits on all 4 inputs, 
decoding-logic gates, and 10 output buffers. A BCD code 
applied to the four inputs, A to D results in a "high" level at 
the selected one of 10 decimal decoded outputs. Similarly, a 
3-bit binary code applied to inputs A through C is decoded in 


octal code at output 0 to 7. A "high'-level signal at the D 
input inhibits octal decoding and causes inputs 0 through 7 
to go "low". If unused, the D input must be connected to 
V$S- High drive capability is provided at all outputs to 
enhance dc and dynamic performance in high fan-out 
applications. 


* Formerly developmental type TA5873. 

TABLE I - TRUTH TABLE 


All inputs and outputs are protected against electrostatic 
effects. 



Fig.4—1 Logic diagram. 


145 





CD4028A 


File No. 503 


STATIC ELECTRICAL CHARACTERISTICS (All inputs 

(Recommended DC Supply Voltage (Vqq - Vgs) • 


v S s< v,<v DD ) 

3 to 15 V) 


CHARACTERISTIC 


Quiescent Device 
Current 


Quiescent Device 
Dissipation/Package 


CHARAC 

TERISTIC 


& TEST 
CIRCUITS 


Noise Immunity 
(Any Input) 



i 10 15 20 

DRAIN-TO- SOURCE VOLTS (V 0D ) 

92CS-I9098 


Fig.4—2 Typ. N-channel drain characteristics. 


Fig.4—3 Typ. P-channei drain characteristics. 


DRAIN MILLIAMPERES (I 0 1 












File No. 503 CD4028A 

STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < V, < V DD ) 

(Recommended DC Supply Voltage (V D p - Vgg) 3 to 15 V) 


CHARACTERISTIC 

SYMBOL 


LIMITS 


CHARAC 

TERISTIC 

CURVES 
& TEST 
CIRCUITS 

Fig. No. 

TEST 

CONDITIONS 

CD4028AE 


V 0 

Volts 

E Bff 

-40°C 

25°C 

85°C 




EBB 

era 

bob 

B2S 

BJIB 

E2B 

Quiescent Device 

Current 

'L 


■ 

■3 

- 



- 

5 

m 

- 

- 


PA 

4-8 

H3 

- 

- 

EEs 

- 

m 

m 

- 

- 

■E&3 

Quiescent Device 
Dissipation/Package 

PD 


■ 

B 

- 

- 


_ 

m 

IES 

- 

- 


pVV 


B 

- 

- 


- 

BE! 

imss 


- 

Hi*,..*; 

Output Voltage: 

Low- Level 

VOL 



B 

- 

- 

0.01 

- 

B3 


- 

- 

ESI 

V 


B 

- 

- 



0 

0.01 

- 

- 

jyjjj 

High Level 

VQH 



B 

4.99 

- 

- 

BESfi 

B3 

- 


B 

- 

V 


B 


- 

- 

jym 

■a 

- 


B 

- 

Noise Immunity 

(Any Input) 

Vnl 


0.8 

m 



- 

1.5 


- 

1.4 


- 

V 

4-9 

mm 

B 


- 

- 

3 

m 

- 

mi 

- 


V NH 

4.2 

B 

a 

- 

- 

m 


- 

1.5 

- 

- 

V 

D 

El 

g 

- 

- 

m 

ESI 

- 

3.0 

- 

- 

Output Drive Current: 

N-Channel 

'd n 


B 

^Qjjj 

- 

■ 



a 

0.25 

a 

a 

mA 

42 

omi 

B 


- 

a 


I 

a 


a 

a 

P-Channel 

’d p 


B 

-0.32 

- 

a 



a 


a 

a 

mA 

4-3 

mm 


-0.65 

- 

- 

-0.48 

-1.9 

- 

-0.4 

- 

- 

Input Current 

'l 

Any Input 

_ 

- 

- 

- 


m 

- 


- 


pA 



For Output Drive Current test connections see Appendix. 




Fig.4—4 Typ. propagation delay time vs. C{_. 


Fig.4—5 Typ. transition time vs. C[_. 


147 














CD4028A 


File No. 503 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, V $s - OV, C, = 15pF, and all input rise and fall times = 20ns 
Typical Temperature Coefficient for all values of V QD = 0.3%/°C (See Appendix for Waveforms) 


CHARACTERISTICS 


Propagation Delay Time VHL' 


CHARAC- 
, TERISTIC 

CD4028AE UNITS CURVES 

I & TEST 

CIRCUITS 



Input Capacitance 


AMBIENT TEMPERATURE <T A )« 25 °C 
LOAD CAPACITANCE (C L J * 15 pF 



SUPPLY VOLTS (V DD I 


FREQUENCY tf ) — Hz 


Fig.4-6 Max. propagation delay time vs. Vqq. 


Fig.4—7 Dissipation vs. input frequency. 



PERFORM TEST 
UNDER EACH 
INPUT CONDITION 



O — O 1.5 V OR 3 V 


Fig.4—8 Quiescent device current test circuit. 


Fig.4—9 Noise-immunity test circuit. 



































File No. 503 


CD4028A 


TYPICAL APPLICATIONS 


1/6 CD4009A 



0 12 3 4 5 6 7 


9 10 II 12 13 14 15 


92CS-I7293RI 


Fig A— 10 Code conversion circuit. 




ABC 

I CD4028A I 
01 234567891 


ABC D 
CD4028A 
01 23456789 

TrTTTTTT 

\0 I 234567 


The circuit shown in Fig.4— 10 converts any 4-bit code to a 
decimal or hexadecimal code. Table 2 shows a number of 
codes and the decimal or hexadecimal number in these codes 
which must be applied to the input terminals of the 
CD4028A to select a particular output. For example: in 
order to get a "high" on output No. 8 the input must be 
either an 8 expressed in 4-Bit Binary code, a 15 expressed in 
4-Bit Gray code, or a 5 expressed in Excess-3 code. 

TABLE 2 - CODE CONVERSION CHART 


■ 



BV'.'f 

[jgjgj 


| 

| 

| 

1 

s 

f 

0 

IB 

IB 

D 

□ 

ID 

□ 

□ 

□ 

□ 

□ 

□ 

0 

0 

m 

m 

0 

m 


0 

Q 

U 

IB 

□ 

■3 

B 

■ 

n 

B 

D 

0 

□ 

B 

B 

□ 

□ 

0 

0 

0 

0 

0 

0 

0 


0 

0 

□ 

□ 

0 

D 

B 

D 

■ 

■ 

0 

0 

□ 

0 

□ 

B 

□ 

□ 

B 

□ 

□ 

B 

d 

d 

0 


o 

0 

□ 

□ 

0 

□ 

E 

E 

■ 

E 

□ 

B 

□ 

□ 

0 

B 

□ 

□ 

□ 

□ 

□ 

□ 

0 

0 

0 


0 

0 

□ 

□ 

0 

□ 

E 

E 

□ 

E 

B 

■ 

□ 

□ 

Cl 

0 

Cl 

□ 

□ 

□ 

0 

□ 

0 

D 

0 


o 

0 

□ 

□ 

□ 

□ 

m 

E 

a 

n 

□ 


□ 

□ 

□ 

□ 

0 

□ 

Cl 

□ 

□ 

□ 

0 

0 

0 


0 

0 

□ 

0 

□ 

D 

E 

E 

□ 



B 

□ 

□ 

□ 

□ 

□ 

0 

□ 

□ 

□ 

Cl 

0 

0 

0 


0 

0 

□ 

D 

0 

□ 

m 

E 

□ 

E 


□ 

□ 

□ 

□ 

□ 

□ 

□ 

0 

Cl 

□ 

□ 

0 

0 

0 


0 

0 

0 

0 

0 

0 

B 

E 

□ 

B 


■ 

□ 

□ 

□ 

B 

□ 

□ 

□ 

o 

□ 

B 

0 

0 

0 


0 

0 

D 

□ 

□ 

□ 

B 

E 




■ 

□ 

□ 

□ 

□ 

□ 

□ 

□ 

□ 

o 

□ 

0 

0 

0 


0 

0 

D 

□ 

B 

D 

E 

m 

□ 

■ 


O 

□ 

□ 

□ 

□ 

□ 

□ 

□ 

□ 

□ 

0 

0 

0 

0 


0 

0 

D 

□ 

0 

□ 

m 

m 

□ 

B 


□ 

□ 

□ 

□ 

B 

□ 

□ 

□ 

B 

B 

□ 

D 

0 

0 


□ 

o 

D 

□ 

D 

D 

m 

E 

□ 


□ 


B 

□ 

B 

B 

□ 

□ 

□ 

□ 

□ 

B 

0 

m 

0 


o 

0 

D 

O 

B 

□ 

m 

E 

□ 

B 

□ 

■ 

□ 

□ 

B 

0 

EJ 

□ 

B 

□ 

□ 

B 

0 

0 

D 


b 

0 

D 

O 

□ 

0 

E 

E 

■ 

B 

□ 

B 

□ 

□ 

□ 

0 

□ 

□ 

□ 

□ 

0 

□ 

0 

0 

0 


0 

0 

D 

0 

0 

□ 

m 

m 

■ 

B 

□ 

0 

□ 

□ 

□ 

Bi 

□ 

□ 

□ 

□ 

□ 

0 

0 

0 

0 


n 

o 

D 

0 

0 

0 

IS 

m 


B 

0 

□ 

□ 

□ 

□1 

01 

□ 

□ 

□ 

□ 

□ 

□ 

0 

0 

0 


0 

0 


? ± i 


“TTT 



64 OUTPUTS (SELECTED OUTPUT IS HIGH) 


92CM-I7294R] 


Fig.4— 1 1 6-bit binary to 1 of 64 address decoder. 



TUBE REQUIREMENTS 


Type 


Vt IVdc) | mA/numeral 


Burroughs B4081 

B4336/718 
84032 
B4021 


TRANSISTOR CHARACTERISTICS: 


Leakage with transistor cutoff <. 0.05 mA 
v (BR)CEO £ 70v 


a (Trademark) Burrough Corp. 


92CS-I7295RI 


Fig.4— 12 Neon readout (Nixie Tube*) display application. 

149 









Solid State 
Division 


File No. 503 

Digital Integrated Circuits 

Monolithic Silicon 


CD4029AD, CD4029AE, CD4029AK 


CARRY IN 

(CLOCK 

ENABLE) 


JAM 

INPUTS Vpp 
'l 2 3 4 t 


92CS-ITI90RI 


COS/MOS Presettable 
Up/Down Counter 

Binary or BCD-Decade 
Special Features: 

■ Medium speed operation 5 MHz (typ.) @ C[_ = 15 pF and Vqd-Vss = 10 V 

■ Multi-package parallel clocking for synchronous high speed output response or 
ripple clocking for slow clock input rise and fall times 

■ "Preset Enable" and individual "Jam" inputs provided 

■ Binary or decade up/down counting ■ BCD outputs in decade mode 

Applications: 

o Programmable binary and decade counting/frequency synthesizers-BCD output 

■ Analog to digital and digital to analog conversion 

■ Up/Down binary counting ■ Up/Down decade counting 

■ Magnitude and sign generation ■ Difference counting 


RCA CD4029A* types consist of a four-stage binary or 
BCD-decade up/down counter with provisions for "look- 
ahead" carry in both counting modes. The inputs consist of a 
single Clock, Carry-in (Clock Enable), Binary/Decade, Up/ 
Down, Preset Enable, and four individual Jam signals. Four 
separate buffered Q signals and a Carry Out signal are 
provided as outputs. 

A "high" preset Enable signal allows information on the Jam 
inputs to preset the counter to any state asynchronously 
with the clock. A "low" on each Jam line, when the 
Preset-Enable signal is "high", resets the counter to its zero 
count. The counter is advanced one count at the positive 
transition of the clock when the Carry-In and Preset Enable 
signals are "low". Advancement is inhibited when the 
Carry-In or Preset Enable signals are "high". The carry-out 
signal is normally "high" and goes "low" when the counter 


reaches its maximum count in the "Up" mode or the 
minimum count in the "Down" mode provided the Carry-In 
signal is "low". The Carry-In signal in the "low" state can 
thus be considered a "Clock Enable". The carry-in terminal 
must be connected to Vgs when not in use; 

Binary counting is accomplished when the Binary/Decade 
input is "high"; the counter counts in the Decade mode 
when the Binary/Decade input is "low". The counter counts 
"Up" when the Up/Down input is "high", and "Down" 
when the Up/Down input is "low". Multiple packages can be 
connected in either a parallel-clocking or a ripple-clocking 
arrangement as shown in Fig. 5-12. Parallel clocking provides 
synchronous control and hence faster reponse from all 
counting outputs. Ripple-clocking allows for longer clock 
input rise and fall times. 

A Formerly developmental type TA5925. 



150 


9-74 







File No. 503 


CD4029A 


Truth Tables 


TRUTH TABLE FOR F-F No.l TRUTH TABLE FOR F-F‘S 2,3,4 



1 I CLOCK 

TE 

PE 

J 

Q 

5 II CLod 

TE 

PE 

J 

Q 

a 

CONTROL 

INPUT 

LOGIC 

LEVEL 

ACTION 

CL 

PE J 
TE Q| 

X 

X 

0 

0 

0 

1 

PE J 

TE Q 

* 

X 

0 

0 

0 

1 

BIN/DEC. 

(B/D) 

1 

0 

BINARY COUNT 

DECADE COUNT 

"L 

1 

1 

X 

5 

'o’ cC 

- 

0 

1 

X 

0 

0 


Q| 

X 

X 

0 

1 

1 

Q 

Q 

X 

X 

0 

1 

1 

0 

UP /DOWN 
(U/D) 

1 

0 

UP COUNT 

DOWN COUNT 

~ "L 

0 

1 

X 

0 

Q NC 

~ "L 

1 

1 

X 

Q 

Q NC 


S 

X 

1 

X 

0 

0 NC 


S 

X 

1 

X 

Q 

Q NC 

PRESET ENABLE 
(PE) 

1 

0 

JAM IN 

NO JAM 

NC-NO CHANGE TE -TOGGLE ENABLE X-DON'TCARE 

CARRY IN (Cl) 
(CLOCK ENABLE) 

1 

0 

NO COUNTER 

ADVANCE AT POS. 
CLOCK TRANSITION 

ADVANCE COUNTER 

AT POS. CLOCK 
TRANSITION 




CARRY IN 
(CL ENABLE)] 

UP/DOWN 

BINARY/ 


n 



COUNT I 5 I 6 i 7 


9 i 10 I II i 12 • 13 M4 l 15 I 9 I 8 I 7 I 6 I 5 I 4 l 3 I 2 I I I 0 i 0 I 15 


Fig. 5-2 — Timing diagram-binary mode. 


92Crw1 - 17192 


CLOCK (CL) 
CARRY IN 
(CL ENABLE) 


UP/DOWN 


BINARY/ 

DECADE 


J| 

d 2 

J 3 


Q. 

0 2 

03 

04 


CARRY OUT 


hjljTjTjTjTJThJTjTJljTJ - LK^ 



COUNT 


0 ! . ! 2 i 3 j 4 >5 
1 1 1 1 1 


6 7 8 


9 


8 7 


I 


6 


5 4 


3 


2 


0 0 


9 I 

I 


6 


Fig.5-3 — Timing diagram-decade mode. 


92CM -I7I93RI 


151 






IN DELAY TIME(tpH L Mp LH ) 


CD4029A 


File No. 503 


STATIC ELECTRICAL CHARACTERISTICS (All inputs 

(Recommended DC Supply Voltage (Vqq — Vgg). 


Vgs< V 1 < V DD^ 
3 to 15 V) 


CHARACTERISTIC 

SYMBOL 

Quiescent Device 

Current 

'L 

Quiescent Device 

D issi pation /Package 

Pd 


TEST 

CONDITIONS 


Output Voltage: 
Low-Level 


Noise Immunity 
(Any Input) 





I 


Input Current 


For Output Drive Current test connections see Appendix 


AMBIENT TEMPERATURE (T A )»25*C t 

TYPICAL TEMPERATURE COEFFICIENT FOR ALL VALUES E 
OF Vpo«0.3%/ <, C t 



AMBIENT TEMPERATURE (T A )*25°C 
TYPICAL TEMPERATURE COEFFICIENT FOR ALL VALUES 
OF Vqd * 0.3 % / °C 


LOAD CAPACITANCE (C L ) — pF 

92CS-I9I05 

LOAD CAPACITANCE (Cl) — pF 

92CS-I9I06 

Fig.5—4 Typ. propagation delay time vs. Cj_ 
for Q outputs. 

Fig.5—5 Typ. propagation delay time vs. Ci_ 
for carry output. 












File No. 503 


CD4029A 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < V] < 

(Recommended DC Supply Voltage (Vqq — Vg $) 3 t 


CHARACTERISTIC 

SYMBOL 

CONDITIONS 

V 0 V 
Volts V 

Quiescent Device 

Current 

lL 



- 

Quiescent Device 
Dissipation/Package 

PD 



- 

Output Voltage: 

Low-Level 

VOL 



1 

High-Level 

VOH 



- 

Noise Immunity 

(Any Input) 

Vnl 


0.8 

1.0 

- 


Vnh 


4.2 

9.0 

- 

Output Drive Current: 

N-Channel 

l n N 

Q 

Outputs 

0.5 

0.5 

- 


LIMITS 


CD4029AE 




Q 

4.5 

5 

P* Channel 

UP 

Outputs 

9.5 

10 


U 

Carry 

4.5 

5 



Output 

9.5 

10 

Input Current 

•i 

Any Input 



UNITS 

CHARAC- 

TERISTIC 

CURVES 

& TEST 

CIRCUITS 

Fig. No. 

uA 

5-10 

pW 

- 

V 

- 

V 


V 

5-11 

V 



LOAD CAPACITANCE (C L I — pF 

92CS-I9I07 

LOAD CAPACITANCE (C L )—pF 

Fig.5—6 Typ. transition time vs. C[_ for 

Q outputs. 

Fig.5—7 Typ. transition time vs. C/_ for 
carry output. 









CD4029A File No. 503 

DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Vgg = OV, C L = 15pF, and input rise and fall times = 20ns, except t r CL and tfCL 
Typical Temperature Coefficient for all values of Vpp = 0.3%/°C. (See Appendix for Waveforms) 





LIMITS 


CHARAC- 

CHARACTERISTICS 

SYMBOLS 

TEST CONDITIONS 


CD4029AE | 

UNITS 

TERISTIC 
CURVES 
& TEST 
CIRCUITS 


VDD 

(Volts) 

Min. 


Max. 

Min. 

Typ. 

Max. 

CLOCKED OPERATION 

Propagation Delay Time: 



5 

- 

325 

650 

- 

325 

1300 


5-4 

Q Outputs 

'PHL' 


10 

- 

115 

230 

- 

115 

460 


Carry Output 

X PLH 


5 

- 

425 

850 

- 

425 

1700 


5-5 



10 

- 

150 

300 

- 

150 

600 


Transition Time: 



5 

- 

100 

200 

- 

o 

o 

400 

ns 


Q Outputs 

X THL' 


10 

- 

50 

100 

- 

50 

200 


Carry Output 

*TLH 


5 

- 

^JjJ| 

Egg 

- 



ns 




mm 

- 



- 


SB 




5 

- 



- 

OI 

JH 






10 

- 



- 

2 




Clock Rise & Fall Time 

t r CL,“ 


5 

- 

- 

15 

- 

- 

EM 



tfCL 


10 

- 

- 

15 

- 

- 






5 

- 



- 



mm 



qqUI 



bb 


230 

- 

mm 

460 

m 





5 

mm 

El 

- 

1 

B 

- 

m 






5 


2 

5 

- 

Input Capacitance 

c i 

Any Input 

- 

5 

- 

- 

5 

- 

PF 


PRESET ENABLE 

Propagation Delay Time: 



5 


325 

650 

- 

325 

1300 



Q Outputs 

t PHL' 


MM 

B^Sl 

BPI 


- 





Carry Output 

l PLH 


5 

- 



- 

KOI 

mm 

mm 




mm 

mmm 

igOI 


- 



B 


Minimum Preset Enable 

ENHBI 


mm 


ffl 


- 

iBa 



■ ■ 

Pulse Width 

mm 


mm 


El 

160 

- 

IB 


1 

mnw 

Minimum Preset Enable 



5 

- 

B 

650 

- 

IQ 


1 


Removal Time 




10 

- 

iKH3i 


- 

IBB 

■ 

B 


CARRY INPUT 

Propagation Delay Time: 



5 

- 

iB 

350 

- 

|Q| 

| 700 

IB 

■■■ 

Carry Output 



mm 

- 

!B 


-/ 

EB 


IB 



‘From Up/Down, Binary /Decade or Carry Input Control Inputs to Clock Input. 

** If more than one unit is cascaded in the parallel clocked application, t f CL should be made less than or equal to the sum of the fixed propaga- 
tion delay at 15 pF and the transition time of the carry output driving stage for the estimated capacitive load. 


154 


























MAXIMUM CLOCK FREQUENCY(fCLMAX )_ MH * 


File No. 503 


CD4029A 



Fig. 5-8 Max. clock frequency vs. Vqq. 


Fig.5—9 Typ. dissipation characteristics. 


10 V 



Fig.5— 10 Quiescent device current test circuit. Fig . 5—11 Noise-immunity test circuit. 


>5 





CD4029A 


File No. 503 


"PARALLEL CLOCKING" 




the Up/Down control is that the clock input to the first counting stage must be "high". 


Fig.5—12 Cascading counter packages. 


The CD4029A "Clock" and "Up/Down" inputs are used directly in 
most applications. In applications where "Clock Up" and "Clock 
Down" inputs are provided, conversion to the CD4029A "Clock" and 
"Up/Down" inputs can easily be realized by use of the circuit shown 
below. 


CD4029A changes count on positive transitions of "Clock Up" or 
"Clock Down" inputs. For the gate configuration shown below, when 
counting "up" the "Clock Down” input must be maintained "high" 
and conversely when counting "down" the "Clock Up" input must be 
maintained "high". 



Fig.5—13 Conversion of "dock up", "dock down" input 
signals to "dock" and "up/down" input signals. 


156 









File No. 503 



Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4030AD, CD4030AF 
CD4030AE, CD4030AK 



COS/MOS Quad Exclusive-OR Gate 

(Positive Logic) 

Special Features: 

■ Medium speed operation tpHL = tPLH = 40 ns (typ.) @ Cl= 15 pF 

and Vdd~ v SS = 10 V 

■ Low output impedance. . 500^2 (typ.) @ Vdd~ V SS = 10 V 

Applications: 

■ Even and odd-parity generators and checkers 

■ Logical comparators 

■ Adders/subtractors 

■ General logic functions 


RCA CD4030A* types each contains four independent 
Exclusive-OR gates integrated on a single monolithic silicon 
chip. Each Exclusive-OR gate consists of four N -channel and 
four P-channel enhancement-type transistors. 

All inputs and outputs are protected against electrostatic 
effects. 


Formerly developmental typeTA5940. 


TRUTH TABLE FOR ONE OF 
FOUR IDENTICAL GATES 


A 

B 

J 

0 

0 

0 

1 

0 

1 

0 

1 

1 

1 

1 

0 



WHERE "1" = HIGH LEVEL 
"0" = LOW LEVEL 


Fig.6— 1 Schematic diagram for 1 of 4 identical exclusive-0 R gates. 


TYPICAL APPLICATIONS 




Fig.6-2a Even-parity-bit generator (1-3/4 x CD4030A). 


Fig.6— 2b Even-parity checker (2 x CD4030A ). 


9-74 


157 






CD4030A 


File No. 503 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < V, < V DD ) 

(Recommended DC Supply Voltage (Vqq — V 53) 3 to 15 V) 


CHARACTERISTIC 



LIMITS 

UNITS 

CHARAC 

TERISTIC 

CURVES 

& TEST 
CIRCUITS 

Fig. No. 

TEST 

CONDITIONS 

CD4030AD, CD4030AK, CD4030AF 


Vo 

Volts 

v dd 

Volts 

— 55°C 

25°C 

125°C 


Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 


Quiescent Device 

Current 



B 

- 

- 


- 


ezb 

- 

- 

m 

pA 



- 

- 

1 

- 


1 

- 

- 


Quiescent Device 
Dissipation/Package 



B 

- 

_ 

m 

- 


m 

- 

- 


pW 

- 

,0 

- 

- 

10 

- 

0.1 

EB 

- 

- 


Output Voltage: 

Low-Level 



B 

- 

- 


- 

0 

om 

- 

- 


V 

- 

El 

- 

- 



0 

m 

- 

- 


High-Level 





- 

- 


5 



- 

- 

V 

- 

El 


- 

- 


10 

~ 


- 

- 

Noise Immunity 
(All Inputs) 


1 


D 


- 

- 

ca 


~ 


- 

- 

V 

P| 

Jl 

El 


- 

- 

3 

m 

KM 

Q9I 

- 

- 



O 

El 

- 

- 

ill 



IB 

- 

- 

V 

7.2 

10 

2.9 

- 

- 


4.5 



- 

- 

Output Drive Current: 

N-Channel 


■ 

0.5 

5 

0.75 

B 

a 


a 

a 


B 

a 

mA 

1 

■ 



D 

B 

a 

| 

a 

a 


B 

B 

P-Channel 

>D P 

■ 

Q 



fl 



a 



fl 


mA 

n 

■ 

pi 

I 


B 

- 


S 

- 



B 

Input Current 

>1 

EBaWaBi 

_ 

_ 

- 

■ 


- 

_ 

- 

_ 

PA 

- 


For Output Drive Current test connections see Appendix. 


TYPICAL APPLICATIONS (Cont'd) 




Fig.6-2c Odd-parity-bit generator (2 x CD4030 A). Fig.6-2d Odd-parity checker (2 x CD4030 A).. 


158 
















File No. 503 


CD4030A 


STATIC ELECTRICAL CHARACTERISTICS (All inputs 

(Recommended DC Supply Voltage (Vqq — V35) 


Vss^V^Vdd) 
3 to 15 V) 



159 


DRAIN MILL1AMPERES (Ip) 










CD4030A File No. 503 

DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Vss = OV. C L = 15pF, and all input rise and fall times - 20ns 


Typical Temperature Coefficient for all values of Vqq = 0.3%/°C . (See Appendix for Waveforms) 


CHARACTERISTICS 

SYMBOLS 


LIMITS 

UNITS 

CHARAC- 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 



CD4030AD, AK, AF 

CD4030AE 


Vdd 

(Volts) 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Propagation Delay Time 

Vhl, 

X PLH 


5 





100 


ns 

6-7 

6-9 

10 


mm 

100 


40 

150 

Transition Time: 

High-to-Low Level 

*THL 


5 


70 

nn 


70 


H 

63 

10 



a 


B 

150 

Low-to-High Level 

X TLH 


5 


mm 

ESI 


80 

B3I 

ns 

10 



75 


30 


Input Capacitance 

C . 

Any Input 

- 

5 

- 

- 

5 

- 

pF 

- 



Fig. 6-5 8-bit com para tor. 



A| B| A 2 B 2 A 3 B 3 A4 B 4 

•— Cj CD4008A Co - 

(CARRY- (CARRY - 

IN) OUT) 

^ — i — i — r~ 

A S| S 2 s 3 S 4 S5 Sg S7 Sg • 

"O" *ADD S 1 ... 8 = X,_ b ±Y ,... 8 

"I " = SUBTRACT 


A| B| A 2 B 2 A 3 B^ A 4 B 4 
:j CD4008A C 0 


a-least significant bit 
• -MOST SIGNIFICANT BIT (SIGN BIT) 

92CS- I74I8R2 

Fig. 6-6 8-bit two 's complement adder substractor. 


TABLE I -TWO'S COMPLEMENT NUMBERS AND THEIR 
EQUIVALENT DECIMAL VALUES. 


The Two's complement adder - subtractor can add or subtract 
any two of the numbers in Table I. For example: 




x 

y 

Cj 

s 


_°J1 


0 0 0 0 0 1 0 2 
11110 11-6 
0 + 

1 1 1 1 1 0 1 = -3 


SIGN 

BIT 

X 1 1111110 - 2 + 

y 1 1 1 1 1 0 1 1 - 5 

7 0 0000100 + 
Cj 1 + 

S JJO I 0 0 0 0 0 1 1 = 3 
C c 


160 
























File No. 569 



Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4031AD CD4031AE 
CD4031AK 



COS/MOS 64- Stage 
Static Shift Register 


Applications: 

For use in digital equipment where 
low-power dissipation, 
low package count, and/or 
high noise immunity are primary 
design requirements. 

■ Serial shift registers 

■ Time delay circuits 


RCA CD4031A* is a 64-stage static shift register in which 
each stage is a D-type, master-slave flip-flop. 

The logic level present at the data input is transferred into 
the first stage and shifted one stage at each positive-going 
clock transition. Maximum clock frequencies up to 2 Mega- 
hertz can be obtained. Because fully static operation is al- 
lowed, information can be permanently stored with the clock 
line in either the "low" or "high" state. The CD4031 A has a 
mode control input that, when in the "high" state, allows 
operation in the recirculating mode. Register packages can be 
cascaded and the clock lines driven directly for high speed 
operation. Alternatively, a delayed clock output (CLq) is 
provided that enables cascading register packages while allow- 
ing reduced clock drive fan-out and transition-time require- 
ments. 

Data (Q) and Data (U) outputs are provided from the 64th 
register stage. The Data (Q) output is capable of driving one 
TTL or DTL load. 

•Formerly Dev. No. TA5989. 


MAXIMUM RATINGS, Absolute Maximum Values: 


Storage-Temperature Range . -65°C to +150°C 

Operating-Temperature Range 

Ceramic packages -55°C to +125°C 

Plastic package — 40°C to +85°C 

DC Supply Voltage Range ( V DD - Vss) -0.5 to +1 5 V 

Device Dissipation (per package) 200 mW 

All Inputs Vss<V|<V DD 

Recommended DC Supply 

Voltage Range (Vdd - V SS> 3 to 1 5 V 

Recommended Input Voltage Swing Vqd t0 V SS 


Features: 


■ Fully static operation: DC to 4 MHz @ Vpp - Vg§ = 10V 

■ Operation from a single 3 to 15 V positive or negative 
power supply 

■ High noise immunity 

■ Microwatt quiescent power dissipation: 10 fi\N (typ.) for 
ceramic packages; 100 /tiW (typ.) for plastic packages 

■ Full military operating temperature range: — 55°C to 

+125°C (Ceramic Pkg.) 

■ Single phase clocking requirements 

■ Protection against electrostatic effects on all inputs 

■ Data compatible with TTL-DTL 

■ Recirculation capability 


■ Two cascading modes: 

Direct clocking for high-speed operation 

Delayed clocking for reduced dock drive requirements 



RECIRCULATION 


Fig. 1— Functional diagram. 


162 


3-72 






File IMo. 569 


CD4031A 


MODE I rv. 
CONTROL.-* |P»-| 


RECIRCULATION 





INPUT CONTROL CIRCUIT TRUTH TABLE 


X *DOtfr CARE 


TG.« TRANSMISSION GATE 


Input to Output is: 

(a) A Bidirectional Short Circuit when Control 
Input 1 is "Low" and Control Input 2 is 
"High" 

(b) An Open Circuit when Control Input 1 is 
"High" and Control Input 2 is "Low" 


O-i-A/W- 


INPUT PROTECTION 
NETWORK 




TYPICAL STAGE TRUTH TABLE 


D 

CL* 

D+l 

0 


0 

1 

J- 

1 

X 

"V 

NC 


NC'NO CHANGE 
X- OOtiT CARE 
A « LEVEL CHANGE 


Fig. 2-CD4031A logic diagram and truth tables. 



MODE CONTROL V DD - RECIRCULATION 
GND = NEW DATA 


Fig. 3— Cascading using direct docking for high speed operation (see clock rise & fall time requirement). 



Fig. 4— Cascading using delayed docking for reduced dock drive requirements. 


163 













CD4031 A File No. 569 

STATIC ELECTRICAL CHARACTERISTICS (All inputs V SS <V,<V DD ) 

(Recommended DC Supply Voltage (Vqq - Vss) 3 to 15 V) 


TEST 

CONDITIONS 


CD4031AD, C04031AK 





v„ 

V DD 

-55°C 

25’C 

125°C | 

CHARACTERISTIC 

SYMBOL 


Volts 

Volts 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Quiescent Device 

i, 



5 

- 

- 

10 

- 

0.5 

10 

- 

- 

600 

Current 

'L 



10 

- 

- 

25 

- 

1 

25 

- 

- 

1500 

Quiescent Device 

Pn 



5 

- 

- 

50 

- 

2.5 

50 

- 

- 

3000 

Dissipation/Package 

r D 



10 

- 

- 

250 

- 

10 

250 

- 

- 

15000 


CHARACTER- 
ISTIC 
CURVES 
& TEST 
CIRCUITS 











File No. 569 


CD4031A 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V S S < V, < V DD ) 

(Recommended DC Supply Voltage (V DD - V 55 ) 3 to 15 V) 


CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 

CD4031AE 

UNITS 

CHARACTER- 
ISTIC 
CURVES 
& TEST 
CIRCUITS 
Fig. No. 


Vo 

Volts 

V DD 

Volts 

-40°C 

25°C 

85°C 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Quiescent Device 

Current 

»L 



5 

- 

- 

50 

- 

1 

50 

- 

- 

700 


13 

10 

- 

- 

100 


2 

100 

- 

- 

1400 

Quiescent Device 

Dissipation/Package 

P D 



5 

- 


250 

- 

5 

250 

- 

- 

3500 

M W 

- 

10 


- 

1000 

- 

20 

1000 

- 

- 

14000 

Output Voltage: 

Low-Level 

V 0L 



5 

- 

- 

0.01 


0 

0.01 

- 

B 


V 

- 

10 

- 

- 

0.01 

- 

0 

0.01 

- 

IB 

rm 

High-Level 

V 0H 



5 

4.99 

- 


4.99 

5 

- 

4.95 

- 

- 

V 

- 

10 

9.99 

- 

- 

9.99 

10 

- 

9.95 

- 


Noise Immunity 

(All Inputs) 

For Definition See 
Appendix * 

Vnl 


0.8 

5 

1.5 

- 

- 

1.5 

2.25 

- 

1.4 

- 


V 

14 

1.0 

10 

3 



3 

4.5 

- 

2.9 

- 

- 

v N h 

4.2 

5 

1.4 



1.5 

2.25 

- 

1.5 


B 


9.0 

10 

2.9 


- 

3 

4.5 

- 

3 

■ 

■ 

Output Drive 

Current: 

N-Channel 

IqN 

Q 

0.4 

4.5 

1.6 

- 

- 

1.3 

2.6 


1.05 



mA 

5 

0.5 

10 

5 

9.6 

- 

4 

8 


3.2 

m 

B 

Q 

0.5 

5 

0.05 

. 

_ 

0.045 

0.18 


0.037 

■ 

■ 

0.5 

1 10 

0.12 

- 

- 

0.1 

0.4 


0.08 



cl d 

0.5 

5 

0.24 

- 

- 

0.2 

0.8 


0.16 

- 


0.5 

10 

0.75 



0.6 

2.4 


0.5 

- 

- 

P-Channel 

'd p 

Q 

4.5 

5 

-0.20 


~i 

-0.16 

-0.64 


-0.13 

- 

- 

mA 

6 

9.5 

10 

-0.42 

- 

_ 

-0.35 

-1.4 


-0.29 

- 

_ 

5 

4.5 

5 

-0.05 

- 


-0.045 

-0.18 


-0.037 

- 

- 

9.5 

10 

-0.12 

- 

_ 

-0.10 

-0.4 


-0.08 

- 

- 

CL D 

4.5 

5 

-0.24 



-0.20 

-0.8 


-0.16 

- 

- 

9.5 

10 

-0.5 



-0.40 

-1.6 


-0.32 

- 


Input Current 

•l 

Any Input 

- 

- 

- 

- 

10 

- 

- 



pA 



* For "Q" and "Q” outputs use MSI Outputs Limits; for CLq output use Gate Output Limits. 




Fig. 7— Typical propagation delay time Fig. 8— Typical propagation delay vs. 

vs. Cl for data outputs. a for delayed dock output. 


165 





CD4031A 


File No. 569 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25° C, V SS = OV, C L = 15 pF (unless otherwise specified), and input rise and fall 
times = 20 ns, except t r CL and tfCL. 

Typical Temperature Coefficient for all values of Vqq = 0.3%/ °C. (See Appendix for Waveforms) 



Transition Time: 
Q Output 


5 Output 


CLq Output 

Clock Rise 
& Fall Time** 


Data Overhang 
Time 


Maximum Clock** 

Frequency 

Input Capacitance : 

Clock 

All Others 


1 Limits 1 

1 

CD4031AE | 




■S9ES91 






wEsmmEssm 




■HH3IEES 


WBMWBSM 

(■■KJEiiB 


30 120 

■HEjIilKSm 


300 1200 

— KEEBBlCDM 





K'jHTS 




2 


2 

1 


1 

1 ElSI 






HMEflEfl 


0 

20 50 

t 08 j 2 1 

K3I 

HEHHHHI 

IKflBIHH 

1 

hebhhhI 



60 

1 1 s| 


■EMHII 


Characteristic 
Units Curves and 
Test Circuits 



Capacitive loading on Q output affects propagation delay of Q output. These limits apply for Q load C|_ < 15pF. 

If more than one unit is cascaded in the parallel clocked application, t r CL should be made less than or equal to the sum of the propagation 
delay at 15pF and the transition time of the output driving stage. 

Maximum Clock Frequency for Cascaded Units; 


a) Using Delayed Clock Feature — f 


b) Not Using Delayed Clock 


max (n-1 ) CLd prop, delay + Q prop, delay + set-up time 


max propagation delay + set-up time 


where n ** number of packages 


"T AMBIENT TEMPERATURE (T A )=25°C 

TVDir-AI TCUPFPATI IRF Crtl 


ALL VALUES OF V DD *0.3 


LOAD CAPACITANCE ICiJ-pF 92CS- 19749 

NOTE: t THL F0R Q OUTPUT IS SIGNIFICANTLY LESS THAN «TLH 


I AMBIENT TEMPERATURE IT A )=25°C j 
TYPICAL TEMPERATURE COEFFICENT FOR I 


ALL VALUES OF V DD = 0.3 


SUPPLY VOLTS IVp D l s 5 


LOAD CAPACITANCE lC|_>-pF 


Fig. 9— Typical transition time vs. Cl 
for data outputs. 


Fig. 10-Typical transition time vs. Cl 
for delayed dock output. 



























MAXIMUM CLOCK FREQUENCY (f CL ) -MHr 


File No. 569 


CD4031A 




-File No. 503 


□QOE0D 

Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4032A, CD4038A 



COS/MOS Triple Serial Adder 

Positive Logic Adder - CD4032AD, CD4032AE, CD4032AK 
Negative Logic Adder- CD4038AD, CD4038AE, CD4038AK 


Special Features: 

■ Invert inputs on all adders for sum complementing 
applications 

■ Fully static operation dc to 5 MHz (typ.) 

■ Buffered outputs 

■ Single-phase clocking 

■ Microwatt quiescent power dissipation 5 /jW (typ.) 


RCA CD4032A* and CD4038A types consist of three serial 
adder circuits with common clock and carry-reset inputs. 
Each adder has provisions for two serial data input signals 
and an invert command signal which, when a logical "1” 
complements the sum. Data words enter the adder with the 
least significant bit first; the sign bit trails. The output is the 
MOD 2 sum of the input bits plus the carry from the 
previous bit position. The carry is only added at the 
positive-going clock transition for the CD4032A or at the 
negative going clock for the CD4038A, thus, for spike free 
operation the input data transitions should occur as soon as 
possible after the triggering edge. 

The carry is reset to a logical “O' at the end of each word by 
applying a logical ‘'i” signal to a carry-reset input one 


Applications: 

■ Serial arithmetic units 

■ Digital correlators 

■ Digital datalink computers 

■ Flight control computers 

■ Digital servo control systems 


bit-position before the application of the first bit of the next 
word Fig. 7-2 and 7-4 shows definitive waveforms for all 
input and output signals. 

A Formerly developmental type TA5963. 


For maximum ratings, see page 22. 




92CS-I766Z 


Fig. 7-1 CD4032A logic diagram of one of three serial 

adders. Fig.7-2 CD4032A timing diagram. 


168 


9-74 




CD4032A, CD4038A 


File No. 503 

STATIC ELECTRICAL CHARACTERISTICS (All inputs V SS <V,<V DD ) 

(Recommended DC Supply Voltage (Vqq — Vgg) 3 to 15 V) 


CHARACTERISTIC 

SYMBOL 


LIMITS 

UNITS 

CHARAC 

TERISTIC 

CURVES 

& TEST 

CIRCUITS 

Fig. No. 

TEST 

CONDITIONS 

CD4032AD, CD4032AK 

CD4038AD, CD4038AK 


Vo 

Volts 

V DD 

Volts 

— 55°C 

25° C 

125°C 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Quiescent Device 

Current 

lL 



5 

- 

- 

5 

- 

0.3 

5 

- 

- 

300 

pA 

7-8. 

7-10 

10 

- 

- 

10 

- 

0.5 

10 

- 

- 

600 

Quiescent Device 
Dissipation/Package 

PD 



5 

- 

_ 

25 

- 

1.5 

25 

- 

- 

1500 

pW 


10 

- 

- 

ICO 

- 

5 

ICO 

- 

- 

6000 

Output Voltage: 

Low-Level 

VOL 



5 

- 

- 

0.01 

- 

0 

0.01 

- 

_ 

0.05 

V 


10 


- 

0.01 

- 

0 

0.01 

- 

" 

0.05 

High-Level 

Vqh 



5 

4.99 

- 

- 

4.99 

5 

- 

4.95 

- 

- 

V 


10 

9.99 

- 

- 

9.99 

10 

- 

9.95 

- 

- 

Noise Immunity 
(All Inputs) 

VNL 


0.8 

5 

1.5 

- 

- 

1.5 

2.25 

- 

1.4 

- 

- 

V 

7-9. 

7-11 

1.0 

10 

3.0 

- 

- 

3 

4.5 

- 

2.9 

- 

- 

V NH 

4.2 

5 

1.4 

- 

- 

1.5 

2.25 

- 

1.5 

- 

- 

V 


9.0 

10 

2.9 

- 

- 

3 

4.5 

- 

3.0 

" 

- 

Output Drive Current: 

N-Channel 

! d N 

V Q = 0.5 V 

5 

0.6 

- 

- 

0.5 

0.9 

- 

0.3 


- 

mA 

- 

V q = 0.5V 

10 

0.75 

- 

- 

0.7 

2.4 

- 

0.6 

- 

- 


P-Channel 

'd p 

Vq = 4.5V 

5 

-0.21 

- 

- 

-0.15 

-0.4 

- 

-0.075 

- 

- 

mA 

- 

Vq = 9.5 V 

10 

-0.7 

- 

- 

-0.55 

-1.2 

- 

-0.35 

- 

- 

- 

Input Current 

•l 



- 

- 

- 

- 

10 


- 

- 

- 

pA 

- 


For Output Drive Current test connections see Appendix. 



Fig. 7— 3 CD4038A logic diagram of one of three serial 
adders. 



WORD I 1.1000011 * -61 WORD 3 0.0100100 * +36 

WORD 2 I.IOOIIOI = -51 WORD 4 0,01 10001 = +49 

hOOIOOOO =-112 O.IOIOIOO =+85 

92CS-I9I2I 


Fig. 7— 4 CD4038A timing diagram. 


169 





PROPAGATION DELAY TIME ( t PLH ,t PH L> 


CD4032A, CD4038A. 


File No. 503 


STATIC ELECTRICAL CHARACTERISTICS (All inputs 

(Recommended DC Supply Voltage (Vqq — Vgg)- 


v S s^v,<v DD ) 

3 to 15 V) 





























File No. 503 — — CD4032A, CD4038A 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Vgg = OV, C L = 15pF, and input rise and fall times = 20ns. except 
Typical Temperature Coefficient for all values of Vqq = 0.3%/°C. (See Appendix for Waveforms) V CL and t f CL ’ 





LIMITS 


CHARAC- 

TERISTIC 

CURVES 

8t TEST 

CHARACTERISTICS 

SYMBOLS 

TEST CONDITIONS 

CD4032AD, CD4032AK 
CD4038AD. CD4038AK 


CD4032AE 

CD4038AE 


UNITS 




vdd 

(Volts) 









CIRCUITS 




Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 


Fig. No. 

Propagation Delay Time: 



5 

- 

400 

1100 

- 

400 

1400 


7-5 

A, B, or Invert 

Inputs to Sum Outputs 

Vhl, 


10 

- 

125 

250 

- 

125 

300 


Clock Input 

t plh 


5 

- 

800 

2200 

- 

800 

2400 

ns 


to Sum Outputs 



10 

- 

250 

500 

- 

250 

600 


Transition Time 

l THL, 


5 

- 

125 

375 

- 

125 

425 

ns 

*7 C 

(Sum Outputs) 

*TLH 


10 

- 

50 

150 

- 

50 

200 

/■b 

Clock 

'\CL, 


5 

- 

- 

15. 

- 

- 

15 

Ms 


Rise & Fall Time 

t f CL 


10 


- 

15 

- 

- 

15 


Input Set-Up Times* 



5 

t r CL 



t r CL 







10 



“ 

” 



Maximum Clock 

f CL 


5 

1.5 

2.5 

- 

1 

2.5 

- 

MHz 


Frequency 


10 

3 

' 5 

- 

2 

5 

- 


Input Capacitance 

C . 

Any Input 

- 

5 

- 

- 

5 

- 

pF 

- 


*This characteristic refers to the minimum time required for the A, B, or Reset Inputs to change state following a positive clock transition 
(CD4032A) or negative transition (CD4038A). 

*lf more than one unit is cascaded t f CL should be made less than or equal to the sum of the transition time and the fj xec | propagation delay 
of the output of the driving stage for the estimated capacitive load. 




Fig.7—7 Typ. dissipation characteristics. 


Fig. 7— 8 Quiescent device current test circuit CD4032A. 






File No. 575 



Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4034AK 

CD4034AD 



COS/MOS MSI 8-Stage Static 
Bidirectional Parallel/Serial 
Input/Output Bus Register 

Special Features: 

■ Bidirectional parallel data input 

■ Parallel or serial inputs/parallel outputs 

■ Asynchronous or synchronous 
parallel data loading 

■ Parallel data-input enable on "A" data lines 

■ Data recirculation for register storage 

■ Multipackage register expansion 


■ Fully static operation DC-to-5 MHz (typ.) 
at Vqd-VsS = 10 V 


RCA CD4034A is a static eight-stage parallel-or serial-input 
parallel-output register. It can be used to: 

1) bidirectionally transfer parallel information between two 
buses, 2) convert serial data to parallel form and direct the 
parallel data to either of two buses, 3) store (recirculate) 
parallel data, or 4) accept parallel data from either of two 
buses and convert that data to serial form. Inputs that 
control the operations include a single phase clock (CL), 
"A"-data enable (AE), Asynchronous/synchronous (A/S), 
"A" bus to ' B" bus/"B" bus to "A" bus (A/B), and 
parallel/serial (P/S). 

Data inputs include 16 bidirectional parallel data lines of 
which the eight "A" data lines are inputs (outputs) and the 
"B" data lines are outputs (inputs) depending on the signal 
level on the A/B input. In addition, an input for serial data is 
also provided. 

All register stages are D-type master-slave flip-flops with 
separate master and slave clock inputs generated internally to 
allow synchronous or asynchronous data transfer from 
master to slave. Isolation from external noise and the effects 
of loading is provided by output buffering. 


PARALLEL OPERATION 

A "high" P/S input signal allows data transfer into the 
register via the parallel data lines synchronously with the 
positive transition of the clock provided the A/S input is 
"low". If the A/S input is "high" this transfer is independent 
of the clock. The direction of data flow is controlled by the 
A/B input. When this signal is "high" the A data lines are 
inputs (and B data lines are outputs); a "low" A/B signal 
reverses the direction of data flow. 


Applications: 

■ Parallel Input/Parallel Output, 

Parallel Input/Serial Output, 

Serial Input/Parallel Output, 

Serial Input/Serial Output Register 

■ Shift right/shift left register 

■ Shift right/shift left with parallel loading 

■ Address register 

■ Buffer register 

■ Bus system register with enable parallel lines at bus side 

■ Double bus register system 

■ Up-Down Johnson or ring counter 
b Pseudo-random code generators 

■ Sample and hold register (storage, counting, display) 

■ Frequency and phase comparator 



B DATA 


J 


92CS- 19202 


Fig. 1— Functional diagram. 


9-74 


173 





CD4034A 

The AE input is an additional feature which allows many 
registers to feed data to a common bus. The "A" Data lines 
are enabled only when this signal is "high". 

Data storage through recirculation of data in each register 
stage is accomplished by making the A/B signal "high" and 
the AE signal "low". 

SERIAL OPERATION 

A "low" P/S signal allows serial data to transfer into the 
register synchronously with the positive transition of the 
clock. The A/S input is internally disabled when the register 
is in the serial mode (asynchronous serial operation is not 
allowed). 

The serial data appears as output data on either the B lines 
(when A/B is "high") or the A lines (when A/B is "low" and 
the AE signal is "high"). 


— File No. 575 

Register expansion can be accomplished by simply cascading 
CD 4034 A packages. 

The CD4034A is supplied in two different packages; the 
CD4034AK in a 24-lead flat pack, and the CD4034AD in a 
24-lead ceramic dual-in-line package. 


MAXIMUM RATINGS, Absolute-Maximum Values: 


Storage Temperature Range 

. .. -65 to +150 

°C 

Operating Temperature Range 

DC Supply Voltage Range 

. .. -55 to +125 

°c 

(V DD -Vss) 

. .. 0.5 V to +15 

V 

Device Dissipation (Per Pkg.) 

200 

mW 

All Inputs 

Recommended DC Supply Voltage 

■ ■ • v S s<Vi<Vdd 


(V D d - v ss> 

3 to 15 

V 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < V, < V DD ) 

(Recommended DC Supply Voltage (Vp D - V55 ) .......... 3 to 15 V) 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < V, < V DD ) 

(Recommended DC Supply Voltage (Vp D - V55 ) .......... 3 to 15 V) 


CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 

LIMITS 


CHARAC- 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 
Fig. No. 

CD4034AD, CD4034AK 


VO 

Volts 

VDD 

Volts 

— 55°C 

25°C 

125°C | 


bei 


— 


fll 

9 

CEB 


Quiescent Device 

Current 

‘L 



5 

_ 

_ 

m 

_ 

■mm 

5 

- 

_ 


pA 



KOI 

- 

- 

wm 

- 

mm 

IB 

- 

- 


Quiescent Device 

D issi pat ion/Package 

pd 



• 

- 

- 

m 

- 

mm 

tm 

- 

- 


pW 



mm 

_ 

_ 

EE3 

_ 

HSU 

H7ii 

_ 

_ 


Output Voltage: 
Low-Level 

VOL 



LL 

- 

_ 

055 

_ 

_ 

EES 

- 

_ 


V 

— 


wm 

_ 

_ 

rm 

_ 

_ 

rm 

_ 

_ 


High-Level 

mn 

■ 


• 


_ 

_ 

w 

5 

- 


_ 

_ 

V 

HI 


m 

WP^Ok 

_ 

_ 


■a 



_ 

_ 

Noise Immunity 
(All Inputs) 

For Definition 

See Appendix 

mn 

■ 

Cl 

s 

1.5 

- 

- 

1.5 


- 

warn 

- 

Hi 

1 

■ 

m 

cm 

3 

_ 

- 

3 

rm 

_ 

warn 

_ 

WM 

Vnh 


m 

5 

wm 

- 

- 

1.5 

fffM 

_ 

mm 

_ 

a 

m 

10 

mm 

- 

- 

3 

a 

- 


- 

B 

Output Drive Current: 
N-Channel 

idn 



5 

0.124 

_ 

_ 

0.1 

HB!1 

_ 


_ 

_ 


■ 

1951 

m 

0.31 

Tj 


0.25 


_ 


_ 

_ 

P-Channel 

»dp 


m 

5 

-0.075 

- 1 

- 


BBS 

- 


- 

- 

mA 

HI 

ESI 

rm 



_ 

BTTE1 

; WHS 

w 



_ 


Input Current 1 1 

EJ 

__ 

- 


- 

- 

B 


- 

Lz- 

- 

pA 

HEH 


174 






































CD4034A 


File No. 575 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C and C L = 15 pF 

Typical Temperature Coefficient for all values of Vpp = 0.3%/°C. (See Appendix for Waveforms) 


CHARACTERISTICS 

SYMBOLS 

TEST 

CONDITIONS 

CD4034AD, CD4034AK 

UNITS 

CHARAC- 

TERISTIC 

CURVES 
& TEST 
CIRCUITS 



Min. 

Typ. 

KM 


Propagation 

Delay Time 

X PHU 

*PLH 


5 

- 

600 

1200 


mu 

10 

- 

gg] | 

480 

Transition 

Time 

MTHL' 

*TLH 


5 

_ 

n 

750 

ns 


10 

- 

BftM 

300 

Minimum Clock 

Pulse Width 

%L- 

tWH 


5 

- 


400 

ns 


10 

- 


175 

Minimum High-Level 

AE, P/S, A/S 

Pulse Width 

tWH 


5 

_ 

on 

480 

ns 

n 

10 

- 

KB 

195 

Clock Rise' 

and Fall Time 

Hi 


5 

•- 

- 

15 

JUS 


10 

i 

- 

- 

15 

Set-Up Time 

- 


5 

- 

IfcktlM 

500 

ns 

1 

10 

- 


200 

Maximum Clock 

Frequency 

f CL 


5 

1.5 

wm 

_ 

MHz 

bh 

10 

K33H 

5 

- 

Input Capacitance 

C| 

Any Input 


- 

5 

- 

pF 

■HH 


If more than one unit is cascaded, t r CL should be made less than or equal to the sum of the fixed propagation delay at 15 pF (see chart above) 
and the transition time of the output driving stage for the estimated capacitive load. 


"a“ data lines 



Fig.2— Functional and terminal assignment diagram for 
CD4034AK and CD4034AD. 


175 


























































CD4034A 


File No. 575 



Table I Truth Table for Register Input-Levels and the Resulting Register Operation (L = Low Level, H = High Level, X = Don't Care) 


"A" Enable 

P/S 

A/B 

A/S 

Operation* 

HHHI 

L 

L 

mm 

Serial Mode; Synch. Serial Data Input, "A" Parallel Data Outputs Disabled 

BHHH 

L 

mm 

ma 

Serial Mode; Synch. Serial Data Input, "B" Parallel Data Output 

B 

WEB 

L 


Parallel Mode; "B" Synch. Parallel Data Inputs, "A" Parallel Data Outputs Disabled 

HUH 

mm 

L 

mm 

Parallel Mode; "B" Asynch. Parallel Data Inputs, "A" Parallel Data Outputs Disabled 

FjjHjf 

H 

H 

L 

Parallel Mode; "A" Parallel Data Inputs Disabled,"B" Parallel Data Outputs, Synch Data 
Recirculation 

|gf§H 

H 

H 

H 

Parallel Mode; “A” Parallel Data Inputs Disabled, "B" Parallel Data Outputs, Asynch 

Data Recirculation 

H 

L 

L 

X 

Serial Mode; Synch. Serial Data Input, "A” Parallel Data Output 

H 

L 

mm 

K9 

Serial Mode; Synch. Serial Data Input, "B” Parallel Data Output 

H 

■a 


L 

Parallel Mode; "B” Synch. Parallel Data Input, "A" Parallel Data Output 

H 

mm 

mm 

H 

Parallel Mode; "B" Asynch. Parallel Data Input, "A" Parallel Data Output 

H 

■a 

MM 

L 

Parallel Mode; "A" Synch. Parallel Data Input, "B" Parallel Data Output 

H 


LJLj 

H 

Parallel Mode; "A” Asynch. Parallel Data Input, "B" Parallel Data Output 


* Outputs change at positive transition of clock in the serial mode and when the A/S control input is "low in the parallel mode. 


176 



































CD4034A 


File No. 575 




23 

22 

21 

20 

19 

18 

17 



TEST PERFORMED WITH 
THE FOLLOWING SE- 
QUENCE OF HIGH (HI AND 
LOW LEVEL <U INPUTS 
SI S2 S3- S4 S5 

L H H L H 

L H H H L 

H L H L L 

H L H H L 

H H L L H 

L L L H H 



92CS-I9206 


Fig.g-Quiescent device current test circuit. 


5 V OR 10 V 



Fig. 10— Noise immunity test circuit. 


V D d 

t uuun 


A PARALLEL 
DATA 


V D0 

1 uuim 

A PARALLEL 
DATA 


“a" ENABLE > 


uniurmi 


P/S>— 
A/S> — 
• CL >— 


muHfe 



92CS-I9208 


Fig. 11- 16-Bit parallel in /parallel out. parallel p jg 12 - 1 6-Bit serial in/gated parallel out register, 

in/serial out, serial in/parallel out. 
serial in /serial out register. 



TIMING DIAGRAM 

iriririrTrirTrTrirTririrTrT - 
mni — inrTfinrTnnniirw 


<2 ir 

CLOCK Tnjuinjiniuinjii^^ 

p/s 

OUTPUTI 


TJLJTJilrUTJlJX^ 

_ f| = f 2 * H-- f i < f 2 -H 


92CS-I9203 


# WHEN f| = f 2 ,t w IS PROPORTIONAL TO THE PHASE OF f t WITH RESPECT TO 1z 

92CS- 19204 


Fig. 13 - Frequency and phase comparator. 


178 






File No. 575 


CD4034A 


SHIFT LEFT OUTPUT 



A "'High” ("Low") on the shift Left/Shift Right input' allows serial 
data on the Shift Left Input (Shift Right Input) to enter the register 
on the positive transition of the clock signal. A "high" on the "A" 
Enable Input disables the "A" parallel data lines on Reg. 1 and 2 and 
enables the "A" data lines on registers 3 and 4 and allows parallel data 


92CM-I92I3 

into registers 1 and 2. Other logic schemes may be used in place of 
registers 3 and 4 for parallel loading. 

When parallel inputs are not used Reg. 3 and 4 and associated logic 
are not required. 

*Shift left input must be disabled during parallel entry. 


Fig . 14 — Shift right /shift left with parallel inputs. 


MEMORY 

UNIT 


I 


SI A/B A/S CL 


PERIPHERAL 

UNIT 


L. 


J 


TTTT 

1111 


SI A/B A/S CL 


BUS LINES 
(SINGLE) 


DOUBLE -BUS SYSTEM (ENABLE INPUTS ON BOTH SIDES) 


1 AE P/S 1 




2 

X(l) 

2 

3 

REG 

3 

4 

* £ 

4 

3 

5 

6 


5 

6 


CD4034A 


7 


7 

8 

a, V 
SI % sc 

8 

L 


SI 'B 'S CL 


tttt 


TO 2nd 
|- BUS 
SYSTEM 


1111 


SI A/B A/S CL 


M ! 


ARITHMETIC 

UNIT 


__J 


92CM- 19197 


The “A" enable (AE) and A/B signals control all combinations of 
transfer between the registers and bus systems. 

Fig. 15 — Single- and double-bus systems. 


179 












CD4034A 


File No. 575 



Fig. 16~N -stage shift register with fixed serial output line. 


SAMPLE /HOLD > ■ - 

i mini i 

SERIAL DATA > » 

AE 1 8 

' ^“PARALLEL DATA / 

SI 

V DD 

A/S >■■ » 

A/B CP4034A 

A/S 

CLOCK > » 

CL 

/ ^"PARALLEL DATA \ 

P/S 1 8 


TO DISPLAY ETC 


92CS- 19214 


Fig.17~ Sample and hold register— serial /parallel in— parallel out. 


180 





File No. 568 


Digital Integrated Circuits 

Monolithic Silicon 

CD4035AD 
CD4035AE 
CD4035AK 

COS/MOS 4-Stage Parallel In/ 

Parallel Out Shift Register 

with J-K Serial Inputs and True/ 

Complement Outputs 


APPLICATIONS: 

■ Sequence generation, control circuits, code conversion 

■ Counters, Registers, Arithmetic-Unit Registers, Shift 
Left - Shift Right Registers, Serial-to-Parallel/Parallel-to- 
Serial conversions. 

RCA-CD4035A* is a four-stage clocked serial register having 
provisions for synchronous parallel inputs to each stage and 
serial inputs to the first stage via JK logic. Register stages 2, 

3, and 4 are coupled in a serial "D" flip-flop configuration 
when the register is in the serial mode (Parallel/Serial 
control low). 

Parallel entry via the "D" line of each register stage is 
permitted only when the Parallel/Serial control is "high”. 

In the parallel or serial mode information is transferred on 
positive clock transitions. 

When the True/Complement control is "high", the True 
contents of the register are available at the output terminals. 

When the True/Complement control is "low", the outputs 
are the complements of the data in the register. The True/ 

Complement control functions asynchronously with respect 
to the clock signal. 

JR input logic is provided on the first stage serial input to 
minimize logic requirements particularly in counting and 
sequence-generation applications. With JK inputs connected 
together, the first stage becomes a "D" flip-flop. An 
asynchronous common reset is also provided. 

CD4035A types are supplied in the 16-lead flat pack, and in 
both the 16-lead ceramic and plastic dual-in-line packages. 

’Formerly developmental type TA5876 


FEATURES: 

■ 4-Stage clocked shift operation 

■ Synchronous parallel entry on all 4 stages 

■ JK inputs on first stage 

*■ Asynchronous True/Complement control on all outputs 

■ Reset control 

■ Static flip-flop operation; Master-slave configuration 

■ Buffered outputs 

■ Low-Power Dissipation — 5 pW typ. (ceramic) 

■ High speed — to 5 MHz 


MAXIMUM RATINGS, Absolute-Maximum Values: 

Storage-Temperature Range — 65°Cto+150 °C 

Operating Temperature Range: 

Ceramic Package Types -55°Cto+125 °C 

Plastic Package Types -40°C to +85 °C 

DC Supply-Voltage Range 

(VdD“ v SS> -0.5 V to +15 V 

Device Dissipation (Per Pkg.) 200 mW 

All Inputs VSS^V|<Vdq 

Recommended 

DC Supply Voltage (V DD - V$$). 3 to 15 V 

Recommended 

Input Voltage Swing Vqd to Vgs 




Solid State 
Division 


9-74 


181 





CD4035A 


File No. 568 


STATIC ELECTRICAL CHARACTERISTICS (All inputs 


v ss < v, <v DD ) 


(Recommended DC Supply Voltage (Vqq - V 55 ) . '. 3 to 15 V) 






LIMITS 


CHARAC- 

CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 


CD4035AD, CD4035AK 

UNITS 

TERISTIC 

CURVES 

8c TEST 
CIRCUITS 




v 0 

VDD 

-55°C 

25°C 

125°C 





Volts 

Volts 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 


Fig. No. 

Quiescent Device 




5 

- 

- 

5 

- 

0.3 

5 

- 

- 

300 



Current 

'L 



10 

- 

- 

10 

- 

0.5 

10 

- 

- 

600. 

JUA 

11 

Quiescent Device 




5 

- 

- 

25 

- 

1.5 

25 

- 

- 

1500 



Dissipation Package 

PD 



10 

- 

- 

100 

- 

5 

100 

- 


6000 

jUW 

4 

Output Voltage 




5 

- 

- 

0.01 

- 

0 

0.01 

- 

- 

0.05 



Low Level 

v OL 



10 

- 

- 

0.01 

- 

0 

0.01 

- 

- 

0.05 

V 

- 





5 

4.99 

- 

- 

4.99 

5 

- 

4.95 

- 

_ 



High Level 

v OH 



10 

9.99 

- 


9.99 

10 

- 

9.95 

- 

- 

V 

- 

Noise Immunity 



0.8 

5 

1.5 

- 

- 

1.5 

2.25 

- 

1.4 

- 

- 



(All Inputs) 

Vnl 


1 

10 

3 

- 

- 

3 

4.5 

- 

2.9 

- 

- 

v 

12 

For definition, 
see Appendix 



4.2 

5 

1.4 

- 

- 

1.5 

2.25 

- 

1.5 

- 

- 


< 

z 

X 


9 

10 

2.9 

- 

- 

3 

4.5 

- 

3 

- 

- 

V 


Output Drive 

Current: 



0.5 

5 

0.62 

_ 

_ 

0.50 

1 

_ 

0.35 

_ 

_ 



N Channel 

IdN 


0.5 

10 

1.55 

- 

- 

1.25 

2.5 

- 

0.87 

- 

- 

mA 

— 




4.5 

5 

-0.31 

- 

- 

-0.25 

-0.5 

- 

-0.17 

- 

- 



P Channel 

>D P 


9.5 

10 

-0.81 

- 

- 

-0.65 

-1.3 

- 

-0.45 

- 

- 

mA 

- 

Input Current 

»l 




- 

- 

- 

- 

10 

- 

- 

- 

- 

PA 

- 



Fig. 1 -Typical Propagation Delay Time vs. Load Capacitance. 



LOAD CAPACITANCE (C L ) — pF 

92CS-I9969 

Fig. 2 -Typical Transition Time vs. Load Capacitance. 


182 




CD4035A 


File No. 568 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V SS < V, < Vp D ) 

(Recommended DC Supply Voltage (Vpp - V55) 3 to 15 V) 


CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 

LIMITS 

UNITS 

CHARAC- 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 
Fig. No. 

CD4035AE 


v 0 

Volts 

V DD 

Volts 

-40°C 

25°C 

85°C 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Quiescent Device 

Current 

•l 



5 

- 

- 

50 

- 

0.5 

50 

- 

- 

700 

JUA 

11 

10 

- 

- 

ICO 

- 


100 


- 

1400 

Quiescent Device 

Dissipation Package 

Pd 



5 

_ 

_ 

250 

_ 

2.5 

250 

_ 

_ 

3500 

pw 

4 

10 

- 

- 

1000 

- 

10 

1000 

- 

- 

14000 

Output Voltage 

Low Level 

VOL 



5 

- 

- 

0.01 

- 

0 

0.01 

- 

- 

0.05 

V 

- 

10 

- 

- 

0.01 

- 

0 

0.01 

- 

- 

0.05 

High Level 

v OH 



5 

4.99 

- 

- 

4.99 

5 

- 

4.95 

- . 

_ 

V 

- 

10 

9.99 

- 

- 

9.99 

10 

- 

9.95 

- 

- 

Noise Immunity 
(All Inputs) 

For Definition 

See Appendix 

Vnl 


0.8 

5 

1.5 

- 

- 

1.5 

2.25 

- 

1.4 

_ 

_ 

V 

12 

1 

10 

3 

- 


3 

4.5 

- 

2.9 

- 

- 

Vnh 

4.2 

5 

1.4 

- 


1.5 

2.25 

- 

1.5 

- 

- 

V 

9 

10 

2.9 

- 

~ 

3 

4.5 

- 

3 

- 

- 

Output Drive 

Current: 

N Channel 

IdN 


0.5 

5 

0.43 


_ 

0.35 

1 


0.24 

7 ~ 


mA 

_ 

0.5 

10 

1.05 

- 

- 

0.85 

2.5 


0.59 

- 

- 

P Channel 

IdP 


4.5 

5 

-0.2 

_ 

_ 

-0.18 

-0.5 

_ 

-0.12 

_ 

_ 

mA 

- 

9.5 

10 

-0.56 

- 

- 

-0.45 

-0.31 

- 

-0.31 

- 

- 

Input Current 

ll 




l _ 

- 

- 

- 

10 

- 

- 

- 

- 

PA 

- 




92CS-I9970 

Fig. 3- Typical dock input frequency us. Vqq. Fig. 4 -Typical dissipation characteristics. 


183 




CD4035A 


File No. 568 




Fig. 6-Binary-to-BCD Converter. 


184 











File No. 568 


CD4035A 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°CandC L = 15 pF 

Typical Temperature Coefficient for all values of Vpp = 0.3%/°C (See Appendix for Waveforms) 


CHARACTERISTICS 

SYMBOLS 


LIMITS 

UNITS 

CHARAC- 

TERISTIC 

CURVES 

8t TEST 
CIRCUITS 
Fig. No. 

TEST 

CONDITIONS 

CD4035AD, CD4035AK 

CD4035AE 


VDD 

(Volts) 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

CLOCKED OPERATION | 

Propagation Delay Time: 

tPLH. 

tPHL 


5 

- 

250 

500 

- 

250 

700 

ns 

1 

10 

- 

ICO 

2C0 

- 

ICO 

300 

Transition Time: 

^HL. 

*TLH 


5 

_ 

100 

200 

_ 

100 

300 

ns 

' 

2 

10 

- 

50 

100 

- 

50 

150 

Minimum Clock 

Pulse Duration 

*WL. 

tWH 


5 

- 

200 

335 

- 

200 

500 

ns 

- 

10 

- 

100 

165 

- 

100 

250 

Clock 

Rise & Fall Time 

trCL* 

tfCL 


5 

- 

- 

15 

- 

- 

15 

Ms 

- 

10 

- 

- 

5 

- 

- 

_AJ 

Setup Time: 

J/R Lines 



5 

- 

250 

500 

- 

250 

750 

ns 

" 

10 

- 

100 

200 

- 

100 

250 

Parallel-In Lines 



5 

- 

100 

350 

_ 

100 

500 

10 

- 

50 

80 

_ 

50 

100 

Maximum Clock 

Frequency 

f CL 


5 

1.5 

2.5 

- 

1 

2.5 

- 

MHz 

3 

10 

3 

5 

- 

2 

5 

- 

Input Capacitance 

C| 

Any Input 

- 

5 

- 



5^ 

- 

pF 

- 

RESET OPERATION | 

Propagation Delay Time: 

tPHL. 

tPLH 


5 

- 

250 

500 

- 

250 

700 

ns 

- 

10 

- 

100 

200 

- 

100 

300 

Minimum Reset Pulse 

Duration 

tWL. 

tWH 


5 

- 

200 

400 

- 

200 

500 

ns 

- 

10 

- 

100 

175 

- 

100 

200 


If more than one unit is cascaded t r CL should be made less than 
or equal to the sum of the fixed propagation delay time at 1 5 pF 
and the transition time of the output driving stage for the 
estimated capacitive load. 


Q| Qz 03 04 



Fig. 7—BIDEC Logic. 



92CS-I9974 

Fig. 8-Shift Left/Shift Right Register. 





CD4035A 


File No. 568 



Fig. 9 (a)— Double Sequence Generator. 


Using a control line (E) two different state sequences can be generated. 
For example, suppose the following two sequences are desired on 
command (control line E) 


Control = 

E = 

0 



1 


Q 1 

q 2 

Q3 

q 4 


Q 1 

q 2 

q 3 

q 4 


A 

B 

c 

D 


A 

B 

c 

D 

0 

0 

0 

0 

0 

15 

1 

1 

1 

1 

1 

1 

0 

0 

0 

14 

0 

1 

1 

1 

2 

0 

1 

0 

0 

13 

1 

0 

1 

1 

5 

1 

0 

1 

0 

10 

0 

1 

0 

1 

10 

0 

1 

0 

1 

5 

1 

0 

1 

0 

4 

0 

0 

1 

0 

11 

1 

1 

0 

1 

9 

1 

0 

0 

1 

6 

0 

1 

1 

0 

3 

1 

1 

0 

0 

12 

0 

0 

1 

1 

6 

0 

1 

1 

0 

9 

1 

0 

0 

1 

13 

1 

0 

1 

1 

2 

0 

1 

0 

0 

11 

1 

1 

0 

1 

4 

0 

0 

1 

0 

7 

1 

1 

1 

0 

8 

0 

0 

0 

1 

14 

0 

1 

1 

1 

1 

1 

0 

0 

0 

12 

0 

0 

1 

1 

3 

1 

1 

0 

0 

8 

0 

0 

0 

1 

7 

1 

1 

1 

0 


Fig. 9 (b) -State Sequences. 


Units 

Register 


Tens 

Register 


Shift 

Shift 

Shift 

Add* 3 to Units Decade & Shift 
Shift 

Add* 3 to Units Decade & Shift 


1 

(1 

0 

1 

(1 


1 

1) 

0 

0 

1) 


* From Left to Right 


Fig. 10— Example of Binary-to-BCD Conversion. 


Using Couleur's Technique (BIDEC) A , a binary number 
(most significant bit, MSB) first is shifted and processed, 
such that the BCD equivalent is obtained whenthelastbinary 
bit is clocked into the register. The CD4035A, with the 
correct conversion logic, can also be used as a BCD-to-binary 
converter. 


a The basic rule is: If a 4 or less is in a decade, shift with the next 
clock pulse; if a 5 or greater is in a decade, add 3 and then shift at 
the next clock pulse. For more information refer to "IRE 
TRANSACTIONS ON ELECTRONIC COMPUTERS". Dec. 1958, 
Pages 31 3-31 6. 


186 



File No. 568 


CD4035A 


TEST CIRCUITS 



92CS -I9976RI 


Fig. 12— Noise immunity. 


187 





File No. 613 

Digital Integrated Circuits 

Monolithic Silicon 

CD4036AD CD4039AD 
CD4036AK CD4039AK 

COS/MOS 4-Word by 8- Bit 
Random- Access NDRO Memory 

Binary Addressing CD4036AD, CD4036AK 

Direct Word- Line Addressing CD4039AD, CD4039AK 

Special Features: 

■ COS/MOS logic compatibility at all input and output terminals 

■ Memory bit expansion 

■ Memory word expansion via Wire-OR capability at the 8 INPUT-BIT 
and 8 OUTPUT-BIT lines 

■ Memory bypass capability for all bits 

■ Buffering on all outputs 

■ CD4036A- on-chip binary address decoding, separate READ 
INHIBIT and WRITE controls ■ Access Time-200 ns(Typ) at Vdd=10 V 

■ CD4039A-Direct word-line addressing 

RCA type CD4036A is a single monolithic integrated circuit Applications: 

containing a 4-word x 8-bit Random Access NDRO Memory. Digital equipment where low power dissipation and/or high 
Inputs include 8 INPUT-BIT lines, CHIP INHIBIT, WRITE, noise immunity are primary design requirements. 

READ INHIBIT, MEMORY BYPASS, and 2 ADDRESS ■ Channel Preset Memory in digital frequency-synthesizer 
inputs. 8 OUTPUT-BIT lines are provided. circuits 

All input and output lines utilize standard COS/MOS inverter ■ General-purpose and scratch-pad memory in COS/MOS and 
configuration's and hence can be directly interfaced with other low-power systems. 

COS/MOS logic devices. 

CHIP INHIBIT allows memory word expansion by WIRE- 
ORing of multiple CD4036A packages at either the 8-bit 
input and/or output lines (See Fig. 15). With CHIP INHIBIT 
"high", both READ and WRITE operations are inhibited on 
the CD4036A. With CHIP INHIBIT "low", information can 
be written into and/or read continuously from one of the 
four words selected by the binary code on the two address 
lines. With CHIP INHIBIT "low", a "high" WRITE signal and 
a "low" READ INHIBIT signal activate WRITE and READ 
operations, respectively, at the addressed word location 
(See Fig.4). 

The MEMORY BYPASS signal, when "high", allows shunting 
of information from the 8 INPUT-BIT lines directly to the 8 
OUTPUT-BIT lines without disturbing the state of the 4 
words. During the bypass operation input information may 
also be written into a selected word location, provided the 
CHIP INHIBIT is "low" and the WRITE is "high". The 
READ operation is deactivated during the BYPASS oper- 
ation because information is fed directly from the 8 
INPUT-BIT lines jo the 8 OUTPUT -BIT lines. 

RCA type CD4039A is identical to the CD4036A with the 
exception that individual address-line inputs have been 
provided for each memory word in place of the binary 


BIT INPUTS 



BIT OUTPUTS 

92CS- 19935 


Fig. 1 — CD4036A — Logic block diagram. 



□vkm] 

Solid State 
Division 


188 


9-74 





File No. 61S 


CD4036A, CD4039A 


ADDRESS, CHIP INHIBIT, and READ INHIBIT inputs. 
When Wire-Oring multiple CD4039A packages for memory 
word expansion, an individual CD4039A is selected by 
addressing one of its word locations. The READ operation is 
activated whenever a word location is addressed (via a "high" 
signal— see Fig. 5). 

These devices will be supplied in two different 24-lead 
ceramic packages; the CD4036AK and CD4039AK in the 
flat-pack, and the CD4036AD and CD4039AD in the 
dual-in-line package. 


MAXIMUM RATINGS, Absolute-Maximum Values: 

Storage Temperature Range —65 to +150 

Operating Temperature Range . . . —55 to +125 

DC Supply Voltage Range 

(Vqd - v ss) -0.5 to +15 

Device Dissipation (Per Pkg.) .... 200 

All Inputs V$S ^ V|^Vqd 

Recommended DC Supply Voltage 

(VDD - V S S) 3 to 15 

Lead Temperature (During soldering) 

At distance 1/16 ±1/32 inch 
(1.59 ±0.79 mm) from case 
for 10 seconds max 265 


STATIC ELECTRICAL CHARACTERISTICS (All inputs Vss < V, < V DD ) 

(Recommended DC Supply Voltage (Vqq — V 55 ) 3 to 15 V) 


CHARACTERISTIC SYMBOL 


Quiescent Device 
Current 

Quiescent Device 

Dissipation/Package 



CHARAC- 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 


■9BHB33K91 


a 


IW— Til 


■an 


iMWBMWZMEM 


m\ 


gSHHHIBlIffil 


91 

rroi 


■ 

m\ 




wm\ 

row 



189 














CD4036A, CD4039A File No. 613 

DYNAMIC ELECTRICAL CHARACTERISTICS at Ta = 25°C and Cl = 15 pF 
Typical Temperature Coefficient for all values of Vdd = 0.3%/°C 


CHARACTERISTICS 

SYMBOLS 

TEST 

CONDITIONS 


CD4036AD, CD4036AK 
CD4039AD, CD4039AK 

UNITS 

CHARAC- 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 

vdd 

Volts 

Min. 

Typ. 

Max. 

Read Delay Time: 
(Access time) 

Read Inhibit (Rl) 

trd 

OUTPUT TIED 
THROUGH 100 kQ 

TO Vss for DATA 
OUTPUT "HIGH" 

AND TO Vdd for 

DATA OUTPUT 
"LOW" 

5 

_ 

375 


Eg 

m 

■a 

- 



Chip Inhibit (Cl) 

5 

_ 



19 

■9 

Hi 

- 

'msm 


Memory Bypass 
(MB) 

5 

- 

■ 


ns 

MM 

■a 

- 

b 

300 

Addressl (ADD) 

mm 

- 


^ [»!»!»■ 

ns 


MEM 

- 



Write Set-up Time2 

tws 


5 

wirm 


- 

ns 

4,5 

■a 

■tmw 

50 

- 

Write Removal Time^ 

tWR 


5 

0 

0 


ns 

mm 

ma 

0 

0 

- 

Write Pulse Duration 

tw 


5 


75 

_ 

ns 

4,5 

ma 

d 

HEEH 

- 

Data Set-up Time^ 

tDS 



- 

0 

0* 

ns 

4,5 

u m 

- 

0 

0* 

Data Overlap Tinned 

tDO 


5 

JBSSM 

50 

— 

ns 

4,5 

m 

WEM 


- 

Output Transition Time 

tTHL. 

tTLH 


5 

- 

MEi«i«1B 


ns 

9 

m 



w 

Input Capacitance 

C| 

Any Input 


- 

5 


pF 



1. For CD4036A only, remove 100-k£2test condition and write all 1's in word one, and all 0's in word two, or vice-versa. 

2. Delay from change of ADDRESS or CHIP-INHIBIT signals to application of WRITE pulse. 

3. Delay from removal of WRITE pulse to change of ADDRESS or CHIP-INHIBIT signals. 

4. Values for CD4036AD & 4036AK only. 

5. The time that DATA signal must be present before the WRITE pulse removal. 

* Max. indicates satisfactory operation if tQg equals or exceeds this value. 

6. The time that DATA signal must remain present after the WHITE pulse removal. 

• Min. indicates satisfactory operation if tQQ equals or exceeds this value. 


Write 
(Pin 2) 

Read 

Inhibit 
(Pin 21) 

Memory 
Bypass 
(Pin 11) 

Chip 
Inhibit 
(Pin 22) 

Operating Mode 

X 

X 

L 

H 

Chip Inhibited (Outputs float) 

X 

X 

H 

H 

Input/Output Shunted to output; 

No Reading from Memory; 
Information in Memory 

Undisturbed 

L 

X 

H 

L 

H 

X 

H 

L 

Input/Output Shunted to output; 

No Reading from Memory; 

Write Data into Addressed Word 

L 

L 

L 

L 

Read Data from Addressed Word 

Write Deactivated 

L 

H 

L 

L 

Read/Write Deactivated 
(Outputs float) 

H 

L 

L 

L 

Read from Memory while 

Writing Data into 

Addressed Word 

H 

H 

L 

L 

Write Data into Addressed Word 
Read Deactivated (outputs float) 


Fig.2 - Operating-mode truth table. 


A1 

Pin 1 

A0 

Pin 23 

Addressed 

Word 

L 

L 

Word 1 

L 

H 

Word 2 

H 

L 

Word 3 

H 

H 

Word 4 


L = Low-Level Voltage, 
H = High-Level Voltage 


Fig. 3 — Address truth table. 


190 































AMBIENT TEMPERATURE 
TYPICAL TEMPERATURE 
AT ALL VALUES OF V DD = 

(T A )=25 # C 

COEFFICIENT 

D.3 %/“C 


■■■■ 

■■■■ 

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SSSSSSS? 

■■■ 

■■■ 

■■■ 

■■■ 

H? 

■■■ 

■■■ 

ss s 


■■■■■■ 

■■■■■■ 



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is:! 


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SSS 

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issisassssss:!^:: 

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!■■■■■■■■■■■■■■■■■■■*■■■■■■■■■■■■■! 

■■■■■■ 


LOAD CAPACITANCE (C L )— 

Fig.8— Typical read delay time 


LOAD CAPACITANCE (Cl) — I 

Fig.9— Typical transition time 


■CHANNEL DRAIN CURRENT (I D p) — mA 






CD4036A, GD4039A 


File No. 613 



TEST CIRCUITS 




Fig. 1 1 -Quiescent current (CD4036A ) . Fig. 12— Quiescent current (CD4039A). 


5 V OR 10 V 3.5 V OR 7 V 



Fig. 13— Noise immunity. 






File No. 613 


CD4036A, CD4039A 



SEE APP. NOTE ICAN-6498 - "DESIGN OF FIXED AND PROGRAMMABLE COUNTERS USING THE RCA CD4018A 

COS/MOS PRESETTABLE DIVIDE-BY-'N' COUNTER" AND ICAN-6716, "LOW POWER DIGITAL FREQUENCY 
SYNTHESIZERS UTILIZING COS/MOS IC'S". 


Switches shown 
are GRAYHILL 
2-pole switches 
50CY23133. CEN- 
TRALAB PA160, 
or equivalent can 
also be used. 


Switches (left to 
right) read 5-3-2. 
The equivalent val- 
ue of "N" for 
these switch po- 
sitions (from the 
Table below) is 
3-1-0 or N= 13. 


N 


Value 

(Front 

panel 

notation) 


Switch 

Positions 


0 2 

1 3 

2 4 

3 5 

4 6 

5 7 


7 9 

8 10 

9 1 


| 92CM- 19947 


Fig. 14— Three-decade programmable -r N counter with 4-channei preset memory settings for frequency synthesizers. 


The divide-by-N counter system shown in Fig.1 4 is program- 
mable from 2 to 999. Four counter-preset words, selected 
by means of the rotary switches, can be stored in the 
CD4039A devices and can be read into each CD4018A by 


simply addressing the proper word. Note that the CD4029A 
(see Bulletin File No. 503) Presettable Up/Down Counter 
with BCD decade counting can also be used to perform the 
basic counting function. 


193 












File No.576 


□UOB//D 

Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4037AD, CD4037AE 
CD4037AF, CD4037AK 



COS/MOS Triple AND-OR 
Bi-Phase Pairs 

Applications: 

For use in digital equipment where low-power 
dissipation, low package count, and/or high 
noise immunity are primary design 
requirements. 


a Split-Phase (Bi-Phase) Communication Systems, 
a Disc, Drum, and Tape Digital Recording Systems. 
■ Plated Wire and Core Memory Systems, 
a High-to-low logic level converter. 


RCA CD4037 A consists of three AND-OR pairs driven by 
common control signals A and B. 

Each circuit has a data input (C), and two output terminals 
(D and E) that provide outputs in accordance with the truth 
table shown in Fig. 2. The circuit is useful for coding or 
decoding signals for split-phase (Bi-phase) communication 
systems, magnetic recording, and plated wire and core memory 
systems. A separate Vcc terminal is provided to allow level 
conversion to any voltage from 3 volts to VqD- 

CD4037AD is supplied in a 14-lead ceramic dual-in-line 
package, CD4037AE in a 14-lead plastic dual-in-line package, 
CD4037AF in a 1 6-lead dual-in-line ceramic frit-seal package, 
and CD4037AK in a 14-lead ceramic flat package. 


Features: 

□ Outputs compatible with low-power TTL systems, 
o High current sink and source (1.6 mA typ.) capability 
at Vdd= Vcc “ 10 v and Vqs = 0.5 V. 
n Input protection against electrostatic effects, 
a Microwatt quiescent power dissipation: Pq = 0.5 jiW/ 
ceramic pkg. (typ.), Pp = 2 juW/plastic pkg. (typ.) at 
V D D = 10 V 


MAXIMUM RATINGS, Absolute-Maximum Values: 


Storage Temperature Range — 65°C to +150 °C 

Operating Temperature Range: 

Ceramic Package Types — 55°C to +125 °C 

Plastic Package Types — 40°C to +85 °C 

DC Supply Voltage Range (Vqq — Vgs) .... —0.5 V to +15 V 

Dissipation: 

Per Package 200 mW 

Per Output 100 mW 

All Inputs V 55 <CV| ^ Vpp 

For Vcc 3 <V cc <V D d 

Recommended DC Supply Voltage 

(Vdd “ V SS) 3 to 15 V 


CAUTION: V cc VOLTAGE LEVEL MUST BE EQUAL TO OR 
LESS POSITIVE THAN V DD 


9-74 


195 






File No. 576 CD4037A 

STATIC ELECTRICAL CHARACTERISTICS (All inputs V S S < V ( < V DD ) 

(Recommended DC Supply Voltage (Vp D - Vgg) 3 to 15 V) 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V S S < V ( < V DD ) 

(Recommended DC Supply Voltage (Vp D - V 55 ) 3 to 15 V) 







LIMITS 


CHARAC- 

CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 

CD4037AD, CD4037AF, CD4037AK 

UNITS 

TERISTIC 

CURVES 

81 TEST 
CIRCUITS 



V 0 

V CC 

1 

— 55°C 

25°C 

125°C 




Volts 

Volts 

Volts 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min.' 

Typ. 

Max. 


Fig. No. 





5 

- 

- 

5 

- 

0.03 

5 

- 

- 

300 

pA 

9 

Current 

'l 



10 

- 

- 

10 

- 

005 

10 

- 

- 

600 

Quiescent Device 

P D 



5 

- 

- 

25 

- 

0.15 

25 

- 

- 

1500 

pW 


Dissipation/Package 



10 

- 

- 

100 

- 

0.5 

100 

- 


6000 


Output Voltage: 



5 

5 

- 

- 

0.01 

- 

0 

0.01 

- 

- 

0.05 



Low- Level 

V OL 


10 

- 

- 

0.01 

- 

0 

0.01 

- 

- 

0.05 



High-Level 



5 

5 

4.99 

- 

- 

4.99 

5 

- 

4.95 

- 

- 



V OH 


10 

10 

9.99 

- 

- 

9.99 

10 

- 

9.95 


- 

V 


Noise Immunity 


0.8 

5 

5 

1.5 

- 

- 

1.5 

2.25 

- 

1.4 

- 

- 



(All Inputs) 

For Definition, 

See Appendix 

V NIL 

1.0 

10 

10 

3 

- 

- 

3 

4.5 

- 

2.9 

- 

- 



V NI H 

4.2 

5 

5 

1.4 

- 

- 

1.5 

2.25 

- 

1.5 

- 

- 

V 


9.0 

10 

10 

2.9 

- 

- 

3 

4.5 

- 

3 

- 

- 



Output Drive Current: 

i d n 

0.5 

5 

5 

0.85 

- 

- 

0.7 

1.2 

- 

0.45 

- 


mA 


N-Channel 

0.5 

10 

10 

1.3 

- 

- 

1.1 

2 

- 

0.7 

- 



P-Channel 


4.5 

5 

5 

-0.65 

- 

- 

-0.55 

-1 

- 

-0.35 

- 

- 

mA 


'd p 

9.5 

10 

10 

-0.9 

- 

- 

-0.75 

-1.6 

- 

-0.45 | 

- 



Input Current 

•l 


- 

- 

- 


10 

- 

- 

- 

- 

pA 

- 







LIMITS 


CHARAC- 

CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 

CD4037AE 

UNITS 

TERISTIC 
CURVES 
& TEST 



V 0 

V CC 

V DD 

— 40°C 

25°C 

85°C 


CIRCUITS 



Volts 

Volts 

Volts 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 


Fig. No. 

Quiescent Device 




5 

- 

- 

50 

- 

0.1 

50 

- 

- 

700 

pA 


Current 

'l 



10 

- 

- 

100 

- 

0.2 

100 

- 

- 

1400 


Quiescent Device 




5 

- 

- 

250 

- 

0.5 

250 

- 

- 

3500 

pW 


Dissipation/Package 

P D 



10 

- 

- 

1000 

- 

2 

1000 

- 

- 

14000 


Output Voltage: 




5 

- 

- 

0.01 

- 

0 

0.01 

- 

- 

- 



Low-Level 

V OL 



10 

- 

- 

0.01 

- 

0 

0.01 

- 

- 

- 



High-Level 



5 

5 

4.99 

- 

- 

4.99 

5 

- 

4.95 

- 

- 



V 0H 


10 

10 

9.99 

- 

- 

9.99 

10 

- 

9.95 

- 

- 



Noise Immunity 


0.8 

5 

5 

1.5 

- 

- 

1.5 

2.25 

- 

1.4 

- 

- 



(All Inputs) 

V N.L 

1.0 

10 

10 

3 

- 

- 

3 

4.5 

- 

2.9 

- 

- 



For Definition, 

See Appendix 

V NIH 

4.2 

5 

5 

1.4 

- 


1.5 

2.25 

- 

1.5 

- 

- 

V 

10 


9.0 

10 

10 

2.9 

- 


3 

4.5 

- 

3 

- 

- 



Output Drive Current: 

! d N 

0.5 

5 

5 

0.4 

- 

- 

0.35 

0.7 

- 

0.3 

- 

- 

mA 


N-Channel 

0.5 

10 

10 

0.65 

- 

- 

0.55 

1.1 


0.45 

- 

- 


P-Channel 

1 _ p 

4.5 

5 

5 

-0.35 

- 

- 

-0.3 

-0.55 

- 

-0.2 

- 

- 

mA 


'D r 

9.5 

10 

10 

-0.5 

- 

- 

-0.4 

-0.75 

- 

-0.3 

- 

- 


Input Current 

'l 


" 

- 

- 

- 

10 


- 

- 

- 

pA 

- 


197 





CD4037A 


File No. 576 


DYNAMIC ELECTRICAL CHARACTERISTICS at Ta = 25°C, C L = 15 pF, and V C C = 5 V 
Typical Temperature Coefficient for all values of Vqq = 0.3%/°C 


CHARACTERISTICS 

SYMBOLS 

TEST 

CONDITIONS 

LIMITS 

UNITS 

CHARAC- 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 
Fig. No. 

CD4037AD, 

CD4037AK, 

CD4037AF 

CD4037AE 


V DD 

(Volts) 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Propagation Delay Time: 

A and B Inputs 

tPHL 

t PLH 


5 

- 

225 

450 

- 

325 

650 

ns 

6,8 

10 

- 

75 

150 

- 

100 

200 

C Inputs 

tPHL 


5 

- 

250 

500 

- 

350 

700 

ns 

10 

- 

75 

150 

- 

100 

200 

l PLH 


5 

- 

225 

450 

- 

325 

650 

10 

_ 

90 

180 

_ 

125 

250 

Transition Time: 

High-to-Low Level 

*THL 


5 

- 

40 

80 

- 

60 

120 

ns 

4,8 

10 

- 

15 

30 

- 

20 

40 

Low-to-High Level 

tTLH 


5 

- 

75 

150 

- 

100 

200 

ns 

5,8 




10 

- 

60 

120 

- 

90 

180 



Input Capacitance 

C| 

Any Input 


- 

5 

- 

- 

5 

- 

pF 

- 


I 



l 


i 


NRZ OATA 



Fig.2— Logic diagram and truth table. 


DECODING WAVEFORMS 92CS I9227 

Fig.3— Coding and decoding waveforms. 



92CS- 19,224 


Fig.4— Typical transition time vs Ci_. 



92CS-I9225 

Fig. 5— Typical transition time vs C[_. 


198 





POWER DISSIPATION (P D ) PER AND-OR CIRCUIT 


File No. 576 


CD4037A 




AMBIENT TEMPERATURE (T A )« 25 # C ffl 

§§ 

|g 

55 

|g 

tn 



- $ 

tF 

3 


pp 

PP 

F 



p 


p| 

TtP 

Pr 

l 


ALL VALUES Of- V D Q » 0.3 7./-C 

3 



fP 

P 

:p 

5 



3 


iitt 



; ; PTTT 




-f- 




a. 

^ 400 

I 

| 

55 


s 

3t r 





5 

g 

l 

g 


rrr; 

X 

a. 

* 

H 



p 



P 

P 



j: 

P 

55 


5 


ii 


P 



p 

P 

P 

pp 


i 

p 

P 


H 300 

f 

-TT 


p 

pi 



gft 

55 

pp 

rp 

ft 

P 

P 


< 

_l 

Q 200 

f 

1 

H 

\ 

5H! 

•Hi: 

!i!H 

11 

KK 

1 

il 

•an 

ii 

pp 

1 

s 

i 

I 


z 

o 

r 

§ 

0 

Ir 

ISSil 

IIISI 


H 

jg 

H 

ii 

ilii| 


I 

H 

H 


< 

| 

s 

:: 

IP 

iiili 

jrfll 

ii 


Ifll 

:::: 

Ilfs 

:| 


p 

HP 


1 ' 00 

I 

g 

II 

55 

11 

iliii 



Ill i 


:: 

;5 

i 




£ 


n 

i: 

;; 

issU 




f T : 

:::: 

:ks:ss :: 




-jrrr 



i 

g 

i 


M 

H 


::g 

11; 

§f 

1 J ; r 1 * 

11.1 Iliii £ 

i 

E 

P 

|g 



O 20 40 60 80 100 

LOAD CAPACITANCE (C L ) — pF 

92CS- 19223 


Fig.6— Typical propagation delay time vs C[_. 



Fig. 7— Typical dissipation characteristics. 



Fig.8— Waveforms for measurement of dynamic characteristics. 


TEST CIRCUITS 



V DD 



92CS- I9232RI 


Fig.9— Quiescent device current. 


Fig. 10— Noise immunity (at T/\ = 25° C). 








Solid State 
Division 


File No. 624 

Digital Integrated Circuits 

Monolithic Silicon 

CD4040AD CD4040AE 
CD4040AF CD4040AK 



COS/MOS 12-Stage Ripple-Carry 
Binary Counter/Divider 

Features: 

■ Medium-speed operation .... 5-MHz (typ.) input pulse rate at 

vdd-Vss = 10 V 

■ Low "high"- and "low"- level output impedance 750 £2 

(typ.) at Vdd~ v SS = 10 V and Vqs = 0 5 v 

■ Common reset 

■ Fully static operation 

■ All 12 buffered outputs available 

■ Low-power TTL compatible 


RCA-CD4040A consists of an input-pulse-shaping circuit and 
12 ripple-carry binary counter stages. Resetting the counter to 
the all-O's state is accomplished by a high-level on the reset 
line. A master-slave flip-flop configuration is utilized for each 
counter stage. The state of the counter is advanced one step in 
binary order on the negative-going transition of the input 
pulse. All inputs and outputs are fully buffered. 

The CD4040A is supplied in a 16-lead dual-in-line ceramic 
welded-seal package (CD4040AD),a 16-lead dual-in-line plastic 
package (CD4040AE), a 16-lead dual-in-line ceramic frit-seal 
package (CD4040AF), or a 16-lead flat pack (CD4040AK). 


MAXIMUM RATINGS, Absolute-Maximum Values: 


Storage-Temperature Range —65 to +150 °C 

Operating-Temperature Range: 

Ceramic-Package Types -55 to +125 °C 

Plastic-Package Types -40 to +85 °C 

DC Supply- Voltage Range: 

(VdD~ v SS) -0.5 to +15 V 

Device Dissipation (Per Package) 200 mW 

All Inputs Vss<V|<Vdd 

Recommended 

DC Supply-Voltage (Vqd ~ Vss)- • 3 to 15 V 

Recommended 

Input- Voltage Swing Vqd to Vss 

Lead Temperature (During Soldering) 

At distance 1/16" ±1/32" (1.59 ±0.79 mm) 

from case for 1 0 s max + 265°C 


Applications: 

■ Frequency-dividing circuits 

■ Time-delay circuits 

■ Control counters 



■ R = HIGH DOMINATES (RESETS ALL STAGES) 

• ACTION OCCURS ON NEGATIVE GOING 
TRANSITION OF INPUT PULSE. COUNTER 
ADVANCES ONE BINARY COUNT ON EACH 
NEGATIVE 4 TRANSITION (4096 TOTAL 

BINARY COUNTS). 92CM-20748RI 

Fig. 1 — Logic diagram of CD 4040 A input pulse shaper and 
1 of 12 stages. 


200 


9-74 






File No. 624 


CD4040AD, CD4040AE 
CD4040AF, CD4040AK 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V SS^ V I< V DD> 

(Recommended DC Supply Voltage (Vpp — VCJ5) 3 to 15 V) 



STATIC ELECTRICAL CHARACTERISTICS (All inputs V SS <V, <V DD ) 

(Recommended DC Supply Voltage (Vqq - V 55) 3 to 15 V) 



201 

























CD4040AD, CD4040AE 
CD4040AF, CD4040AK 


File No. 624 


DYNAMIC ELECTRICAL CHARACTERISTICS, At T/\ = 25°C, V$S = OV, Cl = 15 pF ( unless otherwise specified ), 

and input rise and fall times = 20 ns, except t r CL and tfCL. Typical Temperature Coefficient for all values of Vqq = 0.3%/° C. 


CHARACTERISTIC 

SYMBOL 

| In put- Pulse Operation 

Propagation Delay 

tPHL, 

Time 

tPLH 

Transition Time 

tTHL. 


tTLH 

Min. Input-Pulse Width 

tWL. 

tWH 

Input-Pulse 

*r0. 

Rise & Fall Time 

tf0 

Max. Input-Pulse 

f 0 

Frequency 

Input Capacitance 

C| 

| Reset Operation 

Propagation Delay 

Time 

tPHL 

Minimum Reset 

tWH 

Pulse Width 


TEST CONDITIONS CD4040AK, AD, AF 



UNITS NOTE 




1250 

600 

ns 

1250 

600 

ns 


Measured from the 50% level of the negative clock edge to the 
50% level of either the positive or negative edge of the Q1 out- 
put (pin 9); or measured from the negative edge of Q1 through 
Q11 outputs to the positive or negative edge of the next higher 
output. 


2. Maximum input rise or fall time for functional operation. 

3. Measured from the positive edge of the reset pulse to the nega 
tive edge of any output (Q1 to Q12.). 


[ambient TEMPERATURE (T a ) = 25*C 
TYPICAL TEMP. COEFFICIENT AT ALL VALUES OF V GS = -0.3%/ o C 


(GATE - TO - SOURCE VOLTAGE (V 6s )*l5Vk 


DRAIN- TO -SOURCE VOLTAGE (V os )- 




2.5 5 7.5 10 12.5 15 

DRAIN - TO - SOURCE VOLTAGE <V 0S )-V 

92CS-2I5I0 


AMBIENT TEMPERATURE (T A ) *25°C 

TYPICAL TEMP COEFFICIENT AT ALL VALUES OF Vgs*- 0.3%/ o C 


Fig.2 — Typical n-channe I drain characteristics. 


Fig.3 — Typical p-channel drain characteristics. 


ffl 


















































File No. 572 


TOQB//0 

Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4041AD, CD4041 AE ,CD4041 AK 



COS/MOS Quad True/Compiement 

Buffer 


APPLICATIONS 

■ High Current Source/Sink Driver 

■ COS/MOS-to-DTL/TTL Converter 

■ Display Driver 

■ MOS Clock Driver 

■ Resistor Network Driver (Ladder or Weighted R) 

■ Buffer 

■ Transmission Line Driver 


RCA COS/MOS type CD4041A* is a Quad True/ 
Complement Buffer consisting of n- and p- channel units 
having low-channel resistance and high-current (sourcing and 
sinking) capability. The CD4041A is intended for use as a 
buffer, line driver, or COS/MOS-to-TTL driver. It can be used 
as an ultra-low power resistor-network driver for A/D and 
D/A conversion, as a transmission-line driver, and in other 
applications where high noise immunity and low-power dissi- 
pation are primary design requirements. 

The CD4041A is supplied in a 14-lead dual-in-line ceramic 
package (CD4041AD), a 14-lead dual-in-line plastic package 
(CD4041 AE), or a 14-lead flat pack (CD4041 AK). 

•Formerly Dev. No. TA6031 


MAXIMUM RATINGS, Absolute-Maximum Values: 


Storage Temperature Range 

— 65°C to +150 

°C 

Operating Temperature Range:' 

Ceramic Package Types 

— 55°C to +1 25 

°C 

Plastic Package Types 

— 40°C to +85 

°C 

DC Supply Voltage Range 

(V DD -V SS ) 

-0.5 V to +15 

V 

Device Dissipation (Per Pkg.) 

200 

mW 

Average Dissipation Per Output 

100 

mW 

Allowable Input Rise and Fall Time 

vs Supply and Frequency 

See Fig. 17 


All Inputs 

Vss<V|<V DD 


Recommended 

DC Supply Voltage 4 Vqq - V ss ) . . 

3to15 

V 

Recommended 

Input Voltage Swing 

Vopto Vss 



Special Features 

True Output 

■ High Current Source and Sink Capability 
8 mA (typ.) @ Vqs = 0.5 v * V DD = 10 V 

3.2 mA (typ.) @ Vqs = 0.4 V, V DD = 5 V (two TTL loads) 

Complement Output 

■ Medium Current Source and Sink Capability 

3.6 mA (typ.) @ Vqs = 0.5 V, V D p = 10 V 

1.6 mA (typ.) @ Vqs * 0.5 V, Vqd = 5 V 



VDD 


-O COMPLEMENT 


Fig. 1—CD4041 A schematic diagram. 


9-74 


205 






CD4041A 


File No. 572 


STATIC ELECTRICAL CHARACTERISTICS (All inputs Vss < V, < V DD ) 

(Recommended DC Supply Voltage (Vqq — V 35 ) 3 to 15 V) 







LIMITS 


CHARAC 

CHARACTERISTIC 

SYMBOL 

CONDITIONS 


CD4041AD, CD4041AK 

UNITS 

TERISTIC 

CURVES & 




v 0 

Volts 

V D D 

Volts 

-550C 

25°C 

125°C 

TEST 

CIRCUITS 

Fig. No. 




Min. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Max. 


Quiescent Device 

>1 

Inputs 


5 

- 

1 

- 

0.005 

1 


60 

pA 

19 



to 

Ground 

or 


10 


2 

- 

0.005 

2 

- 

120 


Quiescent Device 



5 

- 

5 

- 

0.025 

5 

- 

300 

nW 


Dissipation/Package 

r D 

V DD 


10 

- 

20 

- 

0.05 

20 

- 

1200 


Output Voltage: 
Low-Level 

V OL 



5 

- 

0..01 

- 

0 

0.01 

- 

0.05 



of 50 


10 

- 

0.01 

- 

0 

0.01 

- 

0.05 


10, 1 1 

High-Level 


COS/MOS 

Inputs 


5 

4.99 

- 

4.99 

5 

- 

4.95 

- 


v OH 


10 

9.99 

- . 

9.99 

10 

- 

9.95 

- 



Noise Immunity • 



0.95 

5 

1.5 

- 

1.5 

2.25 

- 

1.4 

- 



(All Inputs) 

For definition , 
see Appendix 

V NL 


2.9 

10 

3 

- 

3 

4.5 

- 

2.9 

- 

v 

20 



3.6 

5 

1.4 

- 

1.5 

2.25 

- 

1.5 



V NH 


7.2 

10 

2.9 

- 

3 

4.5 

- 

3 


V 


Output Drive Current: 


True 

0.4 

5 

2.1 

- 

1.6 

3.2 


1.2 

- 


2.6. 

N 'Chsnnd 


Output 

0.5 

10 

6.25 

- 

5 

10 

- 

3.5 

- 

mA 



i d n 

Comple- 

0.5 

5 

1 

- 

0.8 

1.6 

-■ 

0.55 

- 

4.8. 



Output 

0.5 

10 

2.5 

- 

2 

4 

; 

1 ~ 

1.4 

- 





True 

4.5 

5 

-1.75 

- 

-1.4 

-2.8 

- 

-1 

- 


3. 7. 

P-Channel 


Output 

9.5 

10 

-5 

- 

-4 

-8 

■ - 

-2.8 

- 

mA 


•d p 

Comple- 

4.5 

5 

-0.75 

- 

-0.6 

-1.2 

- 

-0.4 

- ' 

5.9. 



Output 

9.5 

10 

-2.25 

- 

-1 .8 

-3.6 

- 

-1 .25 

" 



Input Current 

'l 

Any Input 

- 

- 


10 

- 

~ 

- 

[ PA 



• Values shown are for true output. 



MAXIMUM AVERAGE 
DISSIPATION 

PER OUTPUT ( IOO mW)*:: 

§j 

1 

±±t±: AMBIENT TEMPERATURE 
SHE j (T a )= 25°C 









l III llttttttlltltltllltlllllitl) 

TO j j| jj re ||||H| jjjUjj jj|| 

Mt VDD f 

100 

< 90 

E 

J. 80 

*0 

£370 

H 

2 60 
tt 

tr 

350 

| 

I 

l 

j 


1 

! 


z 

<40 

Q 

30 

20 

10 

I 

I 

1 

VGS 

1 

=5V 

s 

i 

1 

; ; ; | yss*- 

: : : I : : : " : : OTHER INPUTS 
GROUNDED 


0 5 10 15 

DRAIN -TO-SOURCE VOLTAGE (V DS )-V 

*SEE FIG. 17 FOR TRANSITION TIME LIMITATIONS 92CS-20036 


Fig. 2— Typical n-channel drain charac - 
teristics-true output. 



92CS -20037 

Fig. 3— Typical p-channel drain charac- 
teristics-true output. 




File No. 572 


CD4041A 


STATIC ELECTRICAL CHARACTERISTICS (All inputs 

(Recommended DC Supply Voltage (V^q - V 55). 


V SS < V, <V DD ) 
3 to 15 V) 




111 

!! 

:::::: 

w 

ill! 
::: : : 

j!fli { 



■■ 


SSSS5S SSSSSSSr^a' 



11 

1 

!::!:! 

HI 


il 1 H 





||: 


sUHiii 



f JTTJf S : : : : : : 


~ : i 4 i v D d ^ : 11 mill 

1 

Hill 

jjj 

° : OTHER INPUTS GRQUNDEd| — 

-50 ffltitliUWUtlWIttmtmmi) inn 
GATE-TO-SOURCE VOLTAGE tVQsj; 

■ 

■111 


DRAIN-TO- SOURCE VOLTAGE (V DS ) -V 
l FIG. 17 FOR TRANSITION TIME LIMITATIONS 

Fig. 4— Typical n-channel drain charac- 
ter istics-comp/ement output. 


DRAIN-TO-SOURCE VOLTAGE (V DS )-V 

92CS-2 

Fig. 5— Typical p-channel drain charac- 
ter istics-complement output. 


207 








CD4041A File No. 572 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C and C L = 15pF 

Typical Temperature Coefficient for all values of V DD = 0.3%/° C (See Appendix for Waveforms) 


CHARACTERISTIC 

SYMBOL 


LIMITS 

UNITS 

CHARAC- 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 
Fig. No. 

TEST 

CONDITIONS 

CD4041 AD, 
CD4041AK 

CD4041AE 


VDD 

(Volts) 

RfllN. 

TYP. 

MAX. 

MIN. 

TYP. 

MAX. 

Propagation Delay Time: 
High*to-Low Level 

tPHL 

True 

Output 

5 

_ 

m 

HW 

_ 

m 


ns 


10 

- 

EH 

urn 

- 

EH 

Will 

Complement 

Output 

5 


IH1 

nu 



MEM 

ns 

H 

10 


El 

mm 


El 

O 

Low-to-High Level 



5 

- 

mm 


- 

EH 

mem 

ns 

14 

10 

- 

■a 

mm 

- 

m 

U 

Complement 

Output 

5 

- 

eh 


- 

EH 

MEM 

ns 


10 

- 

o 

O 

- 

El 

60 

Transition Time: 
High-to-Low Level 



5 

- 

El 

40 

- 

El 

60 

ns 

12 

mm 

- 

■El 

El 

- 

■El 

40 

Complement 

Output 

5 

- 

EH 

El 

- 

El 

80 

ns 

13 

10 

- 

El 

40 

- 

El 

l^iJl 

Low-to-High Level 

l TLH 

True 

Output 

5 

- 

rea 

40 

- 

Mil 


ns 

12 

10 

- 

IE1 

El 

- 

El 

40 

Complement 

Output 

5 

- 

Ei 

■m 

- 

eh 

75 

ns 

MEM 

mm 

- 

EH 

mm 

- 

EH 

El 

IHfignH 

C| 

Any Input 


— 

5 

— 

— 

_L 

— 

PF 

■hh 


DYNAMIC ELECTRICAL CHARACTERISTICS (Driving TTL.DTL) AT T A = 25°C, V DD -Vss = 5V,C L = 15pF (True Output) 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

LIMITS 

UNITS 

TYPICAL 
CHARAC- 
TERISTICS 
CURVES 
Fig. No. 


Driving 

TTL,DTL 

CD4041AD 

CD4041AK 

CD4041AE 

MIN. 

TYP. 

MAX. 

MIN. 

TYP. 

MAX. 

Propagation Delay Time: 

High-To-Low Level 

*PHL 

R l = 2kft 

Med. 

Power 

- 

75 

150 

- 

75 

175 

ns 

- 

R l = 20k£2 

Low 

Power 

- 

75 

150 

- 

75 

175 

Low-To-High Level 

l PLH 



- 

B 

n 

- 

□ 


ns 

- 


Low 

Power 

- 


1 

- 

85 

200 

Transition Time 

l THL = 
l TLH 



- 


^^1 

- 

20 

75 

ns 

- 

R l = 20kn 

Low 

Power 

- 

20 

50 

- 

20 

75 


208 































OUTPUT VOLTAGE (V 0 ) -V DRAIN CURRENT (I D ) 


[■Eli] 


i3flS 



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:::::: 

ill 



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EisiiniyiSnr'IiSf::::!:::::::: 3 .::::::::::::::::::::::: 

ililillin?! 

::::::::::::::: 

IISI: 

ill 

ss 


lili 

hli 

gjii 

|g| 





AMBIENT TEMPERATU 
(T A )=25°C 

nT 'll lxit rtXD 

ill 

Vo 4i ae H-fy^rnfrri' 

4^VGs j -5y^ff-- 
JCD404I AD,AK:? 

in 

SIssmsss 

P 

III!? 

m 

all 

11 

■■—■a 

iliillilli 

SH 

1 

m 

m 




l 

! 

jj-gj 

i! 

;:sn 

1 


gggggggl"!! 

22122k!! 

? 

i: '.ill 


11 


1 

HilP 

11 


ill 

I! 

•is 

u mm ™n ;jgW«5WgW5jii 

iiiiiiii 

ill 

iiiiijii 

i ii 

i 11:11 

1 

II 

II 

iiiii 

::::: 

11 

I 

i 

III! 


m 

si 




IMlMinlnlllililM 




! III! 


::::::::::: ::•: 


Sslllll 






CD404IAD.AK :} 
CMO^IAE^i 


fc AMBIENT TEMPERATURE 
3(T A )=25°C 


DRAIN -TO -SOURCE VOLTAGE (V DS )-V 


Fig. 8— Minimum n-channel drain char- 
acteristics-compiement output. 


liililsiililllilj 


^^rssssssssss^^H 


?! 


mm 


Sffii 


nu 






AVERAGE 

£ GATE-TO-SOURCE VOLTAGE (V G s)=-I5 DISSIPATION PER OUTPUT 

t nn i f 11 n i [ 1 1 n i n hh i n r n T f m 1 i ittFiVm? i 


DRAIN-TO-SOURCE VOLTAGE (V DS )-V 

Fig. 9— Minimum p-channel drain char- 
acteristics-complement output. 


■ SUPPLY VOLTAGE (Vpo) = 15 V 4 


is::: 


isiisss 


::::::: ::::::: 


E 

I AMBIENT TEMPERATURE 
(T A ) = 25 # C 


■■■■■■■■■■ 


(■■■■■■■■■■■■I 


■■■■■■■■■I 


«■■■■■■■■ 




::::: 




is:::::::::::::: 


INPUT VOLTAGE (Vjl-V 

Fig. 10— Minimum and maximum 
transfer characteristics-true 
output. 


C AMBIENT TEMPERATURE 
IT A )=25»C 




i: 


SSu 


INPUT VOLTAGE IVj) -V 

Fig. 11— Minimum and maximum 
transfer characteristics- 
complement output. 


19 







CO4041A 


File No. 572 


AMBIENT TEMPERATURE 
(T A ) = 25°C 






.tfl . 














:=s "" 








10 20 30 40 50 60 1 

LOAD CAPACITANCE (C|_)-PF 


Fig. 12-Typical transition time vs. 
Cfj-true output 


AMBIENT TEMPERATURE 
(T A ) - 25° C 


10 20 30 40 50 60 70 80 90 

LOAb CAPACITANCE (C L )-PF 

92CS- 20047 

Fig. 13— Typical high-to-low level 
transition time vs. C L - 
complement output. 


AMBIENT TEMPERATURE ' 

■ i T*L**k^ 


AMBIENT TEMPERATURE | 

(T A ) = 25*C .$4; 

I I 


10 20 30 40 50 60 70 80 90 

LOAD CAPACITANCE (C L )-PF 

92CS- 20048 

Fig. 14— Typical low-to-high level 

propagation delay time vs. 
C^-true output. 


10 20 30 40 50 60 1 

LOAD CAPACITANCE (C L )-PF 


70 80 90 

92CS -20049 


Fig. 15— Typical low-to-high level 
propagation delay time vs. 
C ^-complement output. 


4 hAMBIENT TEMPERATURE (T M )« 25° CH 


mmo/m ■■■ i mmt 


MAXIMUM DISSIPATION PER PACKAGE 







AMBIENT TEMPERATURE 

«A>"25*C + 1 1 1 -H 


FREQUENCY (f) Hz 

92CS -20050 

RISE AND FALL TIME-NS 

92CS -20051 

Fig. 16— Typical power dissipation vs. 
frequency per output pair. 

Fig. 17— Typical power dissipation vs. 
input rise and fall time per 
output pair. 











File No. 572 CD4041A 

TYPICAL APPLICATIONS 


A. Ultra-Low Power D/A Converter 



For resolution and accuracy of ± 1/2 least significant bit (LSB), 
choose the values for R (shown in Table I) where R equals the value 
of the external ladder resistor plus the switch source impedance. 


TABLE I. RESISTANCE VALUES AT V D D“VSS = 5V ' 
T A =25°C 


RESOLUTION 

ACCURACY OF 1/2 LSB 

R min 

(ft) 

4 bit 

±3.25% of full scale 

3.5 k 

6 bit 

±0.8% of full scale 

14 k 

8 bit 

±0.2% of full scale 

56 k 

10 bit 

±0.05% of full scale 

224 k 

12 bit 

±0.0125% of full scale 

896 k 


B. Transmission Line Driver 

Drive 100 pF load at 75 ns delay (typ.) Vdd-Vss = 10V 


These values have been tabulated for Vqd = 5V and V$s = 0V. For 
different supply (reference) voltages, the switch source impedance 
must be computed and added to the value of R shown in Table I. 


TABLE II. ON RESISTANCE VALUES 
AT V DS = 0.1V, T A = 25°C 


Vdd-Vss 

Rn 

Rp 

(Volts) 

(ft) 

(ft) 

5 

175 ±50 

200 ± 75 

10 

75 ± 25 

90 ± 30 


C. CD4031 A (64-Stage Static Shift Register) Clock Driver 
(80pF Load) 

t r = tf = 40 ns (typ.), Vdd~VsS = 10V 


TEST CIRCUITS 


V DD = IOV 




92CS - 22850RI 


Fig. 19— Quiescent device current. 


Fig. 20— Noise immunity. 


211 









Solid State 
Division 


File No. 589 

Digital Integrated Circuits 

Monolithic Silicon 

CD4042AD, CD4042AE 
CD4042AF, CD4042AK 


COS MOS Quad 

Special Features: 

■ Medium Speed Operation . . . 
tpHL = tPLH = 50 ns (typ) at 
Vdd = 10 V and C L = 15 pF 

■ Clock Polarity Control 

■ Q and Q Outputs D| 

■ Common Clock 

■ Low Power TTL Compatible 


Applications: 

■ Buffer Storage 

■ Holding Register 

■ General Digital Logic 
RCA-CD4042A types contain four latch circuits, each 
strobed by a common clock. Complementary buffered out- 
puts are available from each circuit. The impedance of the Inl- 
and P-channel output devices is balanced and all outputs are 
electrically identical. 


D| 

□ 

□ 

□ 

c 

°« n 

4 O 

u 
5j n 

0 2 


° 2 n 

7 o 

~° 3 1 

=1 


Q ? Q 

iaO 

d 

° 3 o 


14 0 

CLOCK 


«4_0 



PhA 1 

so ' 


POLARITY 

-9 


V D0O^- 

v ss O^- 

92CS-20I9I 


Clocked "D” Latch 



Information present at the data input is transferred to out- 
puts Q and Q during the CLOCK level which is programmed 
by the POLARITY input. For POLARITY = O the transfer 
occurs during the O CLOCK level and for POLARITY = 1 the 
transfer occurs during the 1 CLOCK level. The outputs follow 
the data input providing the CLOCK and POLARITY levels 
defined above are present. When a CLOCK transition occurs 
(positive for POLARITY = O and negative for POLAR- 
ITY = 1) the information present at the input during the 
CLOCK transition is retained at the outputs until an opposite 
CLOCK transition occurs. 


POLARITY 




L. 



92CS-20I90 


CLOCK 

POLARITY 

Q 

0 

0 

D 

_r 

0 

LATCH 

i 

1 

D 

~L 

1 

LATCH 


CD4042A types are supplied in 16-lead ceramic flat-packs, Fig.l -Logic block diagram & truth table. 

plastic dual-in-line packages, and both welded-seal and frit- 
seal ceramic dual-in-line packages. 


MAXIMUM RATINGS, Absolute-Maximum Values: 


Storage Temperature Range: — 65°C to +150 

Operating Temperature Range: 

Ceramic Package Types — 55°C to +125 

Plastic Package Types -40°C to +85 

DC Supply Voltage Range 

(Vdd — v ss) _0 ’ 5 V to + 15 

Device Dissipation (Per Pkg.) 200 

All Inputs Vss < V| < Vqd 

Recommended DC Supply Voltage 

(Vdd - Vss) 3 to 15 

Recommended Input Voltage Swing . _ . Vdd t0 V SS 


Lead Temperature (During Soldering: 

At distance 1 /1 6 ±1 /32 in. (1 .59 ±0.79 mm) 
from case for 10s max 


°C 

°C 

°C 

V 

mW 


V 


OC 


+ 265 






File No. 589 CD4042A 

STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < V| < V DD ) 

(Recommended DC Supply Voltage (Vq D - Vgg) 3 to 15 V) 


CHARACTERISTIC 

SYMBOL 

.... 

LIMITS 

UNITS 


CONDITIONS 




VDD 

Volts 

— 55°C 

25°C 

125°C 

u 


us 

SB 


^23 


Quiescent Device 
Current 

■ 

Inputs 

to 

Ground 

or 

V DD 

5 

- 

1 

- 


i 

- 

60 

mA 

8 

10 

- 

2 

- 


2 

- 

120 

Quiescent Device 
Dissipation/Package 

n 

5 

- 

5 

- 


5 

- 

IQBI 


- 

10 

- 

Efl 

- 

0 05 

20 

- 

1200 

Output Voltage: 
Low-Level 

V 0L 

Fan-out 
of 50 
CQS/MOS 
Inputs 

5 

- 

Efj|| 

- 

0 


- 

0.05 

H 

~ 

KB 

- 


- 

0 


- 

CE3I 

High-Level 




- 

BO 

5 




■ 

S3 


- 


10 

- 

9 95 

- 

Noise Immunity ^ 

(All Inputs) 

For Definition, 

See Application 

m 

V Q = 0;95V 

• 

KB 

- 

B 

bbibi 


1 4 

_ 

■ 

9 

V 0 = 2.9V 

KB 

3 

- 


45 


2 9 

- 


V 0 = 3.6 V 

5 

mm 


mm 

a 


15 

- 

■ 

V 0 = 7.2V 

10 

mm 

- 

3 

4.5 

- 

3 


Output Drive Current: 

N-Channel 


V 0 = 0.5V 

H 

D 

- 

0.4 


- 

0 27 

B 

fl 

2. 4 

V 0 = 0.5V 

D 


■ 

■ 

■ 

■ 

0 7 

B 

P-Channel 

>D P 

V Q = 4.5V 

H 

Q 


m 

-1 

- 


- 

B 

B 



-1.15 

■ 


■ 

fl 

-0 6 

- 

Input Current 

•l 

Any Input 


- , 

- 

- 

10 

- 

- 


■ai 

■ ■ 


♦ For inverter output only. 



AMBIENT TEMPERATURE (T A ) * 25°C 

TYPICAL TEMPERATURE COEFFICIENT FOR I 0 =-0.3% /°C 








T 


t 

TT 

TT 

TT 

TT 

TT 

TT 

T~ 

T 

TT 

TT 

TT 

T 









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44 

TT 

44 

44 

T 

4 

44 

44 

TT 

T 









-- 

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x 

4 

TT 

TT 

TT 

TT 

44 

44 

4- 

4 

44 

44 

44 

T 








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G 

XT 


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UR 

CE 

VO 

LTA 

GE 

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it 

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tr 

tc 

■ 

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rt 








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rn 

■ 

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0 2.5 5 7.5 10 12.5 15 

DRAIN -TO -SOURCE VOLTAGE (V DS ) 

92CS- 20186 


DRAIN -TO -SOURCE VOLTAGE (V DS ) — V 

-15 -10 -5 0 



::: 




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II 








II 

II 

T 






1-25 J 


in 




ii 

in 

II 








II 

II 

TI 








AME 

rYF 

IE 

ID 

MT 

XL 

T 

TE 

IMF 

MP 

ER 

ER/ 

ATL 

XTU 

RE 

RE 

( 

C 

r A> 

DEf 

FI 

>5 

:ie 

°C 

N1 


OR 


8 

-0 

37 

./• 

C L 


- -30 


92CS- 20187 


Fig.2—Typ. n-channel drain characteristics. 


Fig.3—Typ. p-channel drain characteristics. 




























CD4042A File No. 589 

STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < v | < V DD> 

(Recommended DC Supply Voltage (Vqq — Vgg) 3 to 15 V) 



TEST 

CONDITIONS 



vdd 

Volts 


Quiescent Device 
Current 


Quiescent Device 
Dissipation /Package 



Input Current 


♦ For inverter output only. 


AMBIENT TEMPERATURE (T A ) = 25°C h 

TYPICAL TEMPERATURE COEFFICIENT FOR I D = - 0.3% /°C t 


(GATE - TO - SOURCE VOLTAGE (V GS H5V|- 


DRAIN- TO -SOURCE VOLTAGE (V DS )— V 
-15 -10 -5 


J CD4042AD.CD4042AK. 
j CD4042AF 


>.5 5 7.5 10 12.5 15 

DRAIN - TO - SOURCE VOLTAGE (V DS ) 


AMBIENT TEMPERATURE (T A ) = 25 °C 

TYPICAL TEMPERATURE COEFFICIENT 

FOR I D = - 0.3% / ®C ( 1 ( H- =t = =. 

11 i 1 m ! 1 I 1 1 1 1 1 1 1 1 1 1 rTTTTrr ' ■ 

15 V =r = = - =r - 

— 

ov 

GATE-TO-SOURCE VOLTAGE (Vgs) 






Fig.4—Min. n-channe! drain characteristics. 


Fig.5—Min. p-channel drain characteristics. 














































File No. 589 


DYNAMIC ELECTRICAL CHARACTERISTICS at Ta = 25<>C, Vss = OV, Cl = 15pF, and input rise and fall times = 20 ns, 
Typical Temperature Coefficient for all values of Vnn = 0.3%/°C. (See Appendix for Waveforms) except t r CL and tfCL. 


TEST CONDITIONS 
I V DD 



Clock 

Rise & Fall Time 


Set-Up Time 


Input Capacitan 


| LIMITS | 

1 CD4042AD.CD4042AK 
\ CD4042AF 

CD4042AE 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

\mm 


_ 



IB 

mm 

WMM 

- 

75 

KEM 

- 


_ 

BQSME2SBI 

- 

BUSHES 

- 

mm 

f 1 

_ 


_ 


- 

m 

mm 

_ 

— 

wsm \ 

- 

- 

15 

5 


- 

15 

5 

- 

IB 

dSfl 

_ 

50 

125 

_ 

E9 

50 

_ 

K9 

60 

- 

6 

- 

- 

• 

- 



m 

gamHiijLjjj 

<PERATURE(Ta)- 

25 # C 

Eiilliisililiilil 

mm 

iiii iiiiiiiii iiiiiiii 

::::: 

i:ts: 

liii 

ii 

iiii 

:::: 

iiiliiiiiiiiliilii 

I 

iiiiliiii iiiiiiii 

liljljjj jlpl 

ill 

mill 

tiiiiiiii 

ill 

iiiiiiii 

iiiiiiii 

mu 

1 400: 

2 

300 : 

laaes SaSSSS^B SasaSast 

HI! si 

ill Hill Hill 
illllill Hill 

lyggg ssiiiii 

iiililliiillHiilliliiiil 

ii 

BICaBiBHRSIBI SfiBI 

11111 i 

25 iSSS 
::::::::::::: •■■■ 


iiiiii 

:::::: 

11 

iiiiiiiiiiiii s!ss 

SaBaSeaiaalSii liii 

aSeaeSSSSaSSS 355! 

sbc« 

Iiiiiiiiiiiii liii 

a. 

o 

tr. 

a. 

: 

i jjiijii 

ill 

iiiiiiii 

nil 

pi 

ft::::::; 

Hi 

?~jj«jj!S!SiiS5 | SSSS 

iiiiiiiiiiiiiiiiiii 


SUPPLY VOLTAGE (V DD )-V 


Fig.6— Typical propagation delay time vs. Vqq. 



A 0011100 
B 01 101 1 1 
C 0000001 


Fig.8 — Quiescent device current. 



Fig. 9 — Noise Immunity 




















File No. 590 


Digital Integrated Circuits 

Q i*H Qt * Monolithic Silicon 

Division CD4043AD,CD4043AE,CD4043AK, 

CD4044AD,CD4044AE,CD4044AK 



COS/MOS Quad 3- State 
R/S Latches 

Quad NOR R/S Latch - CD4043A 
Quad NAND R/S Latch - CD4044A 


Special Features: 

■ Medium Speed Operation 

■ 3-Level Outputs with Common 
Output Enable 

■ Separate Set and Reset Inputs 
for Each Latch 

■ Low Power TTL Compatible 

■ NOR and NAND Configurations 


Applications: 

■ Holding Register in Multi- 
Register System 

■ Four Bits of Independent 
Storage with Output Enable 

■ Strobed Register 

■ General Digital Logic 


RCA-CD4043A types are quad cross-coupled 3-state 
COS/MOS NOR latches and the CD4044A types are quad 
cross-coupled 3-state COS/MOS NAND latches. Each latch has 
a separate Q output and individual SET and RESET inputs. 
The Q outputs are gated through transmission gates controlled 
by a common ENABLE input. A logic "1" or "high" on the 
ENABLE input connects the latch states to the Q outputs. A 
logic "0" or "low" on the ENABLE input disconnects the 


MAXIMUM RATINGS, Absolute-Maximum Values: 


Storage Temperature Range: — 65°C to +150 

Operating Temperature Range: 

Ceramic Package Types — 55°C to +125 

Plastic Package Types — 40°C to +85 

DC Supply Voltage Range 

(V DD - V SS ) -0.5 V to +15 

Device Dissipation (Per Pkg.) 200 

All Inputs V S s < V| < V DD 

Recommended DC Supply Voltage 

(Vdd - V SS> 3 to 15 

Recommended Input Voltage Swing V DD to VSS 

Lead Temperature (During Soldering: 

At distance 1 /16±1 /32 in. (1 .59 ±0.79 mm) 

from case for' 10s max +265 


latch states from the Q outputs, resulting in an open circuit 
condition on the Q outputs. The open circuit feature allows 
common bussing of the outputs. The logic operation of the 
latches is summarized in the truth table below shown in Fig.1. 

The CD4043A and CD4044A are supplied in 16-lead dual-in- 
line ceramic packages (CD4043AD and CD4044AD), 16-lead 
ceramic flat packs (CD4043AK and CD4044AK), and 16-lead 
dual-in-line plastic packages (CD4043AE, CD4044AE). 


°C 

°C 

oc 

V 

mW 


V 


OC 


CD4044A TERMINAL DIAGRAM 



92CS-20222 


9-74 


216 







File No. 590 


CD4043A, CD4044A 


CD4043A- NOR 



S R E Q 

x x o oc* 

0 0 I NC + 

10 1 I 

0 110 

1 I I A 
* OPEN CIRCUIT 

+ NO CHANGE 

A DOMINATED BY S= I INPUT 


CD4044A-NAND 


[~~ ONE OF FOUR LATCHES”) 



*OPEN CIRCUIT 
+ NO CHANGE 


AA DOMINATED BY R = 0 INPUT 


92CS- 20211 92CS-202I2 

Fig. 1 — Logic diagrams & truth tables. 



92CS-202I3 92CS-202I4 


Fig.2— Schematic diagram— CD4043A. Fig.3— Schematic diagram— CD4044A. 


217 



CD4043A, CD4044A File No. 590 

STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < V, < V DD ) 

(Recommended DC Supply Voltage (Vqq - V 55) 3 to 15 V) 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < V, < V DD ) 

(Recommended DC Supply Voltage (Vqq - V 55) 3 to 15 V) 


CHARACTERISTIC 

SYMBOL 


♦ LIMITS 


CHARAC 

TERISTIC 

CURVES ft 
TEST 
CIRCUITS 

Fsg No 

CONDITIONS 


CD4043AD, CD4043AK, CD4044AD, CD4044AK 

UNITS 


v D d 

Volts 

— 55°C 

250 c 

1250 c 

|^B 


12 

bb 

(22 

j2jfH 

(j 


■ 

■ 

Inputs 

to 

Ground 

or 

V DD 

5 

- 

1 

- 

jim 

1 

- 

60 

tiA 

D 

WDM 

- 

2 

- 


2 

- 

MEM 

Quiescent Device 
Dissipation/Package 

m 

5 

- 

5 

- 


5 

- 

BE3I 


- 

mm 

- 

mm 



mm 

- 

1200 

Output Voltage: 
Low-Level 

V OL 

Fanout 
of 50 

5 

- 

mm 

- 

0 

ixa 


853 

■ 

- 

10 

- 


- 

0 

K3B 

- 

EE3I 

High-Level 

< 

0 

1 

COS/MOS 

Inputs 

5 

(qb 

- 

EB 

5 

- 

mm 

- 

V 

mm 

KEE3 

- 


WKflM 

- 

wm 

- 

Noise Immunity 
(All Inputs) 

For definition, 
see Appendix 

V NL 

V 0 « 0 95V 

• 

1.5 

- 

1 5 

BB 

- 

■fl 

- 

V 

■ 

V 0 = 2.9V 

mm 

3 

- 

3 

45 

- 

mm 

- 

I 

Z 

> 

Vq = 3.6 V 

• 

1.4 

- 

1 5 

BBS 

- 

■B 

- 

■ 

V 0 = 7.2V 

mm 


— 

n 

KB 

- 

WO 

■ 

Output Drive Current. 

N -Channel 

l 0 N 

Vq = 0.5V 

fl 


i 

B 

B 

B 

m 

B 

B 

■ 

V 0 = 0.5V 

10 

0.61 

■ 


■ 

B 

IQ 

B 

P -Channel 

•d p 

V 0 1 4.5V 

5 

-0.22 

B 

b 

B 

B 


B 

( 

■ 


10 


B 

B 

B 

B 

201 

B 

Input Current 

•l 

Any Input 

- 


_ 


,0 

- 

L_^J 

- 

PA 

^ 1 


DR AIN -TO- SOURCE VOLTAGE (Vos) — V 




Fig.4—Typ. n-channel drain characteristics. 


Fig.5—Typ. p-channel drain characteristics. 









































CD4043A, CD4044A 


File No. 590 

STATIC ELECTRICAL CHARACTERISTICS (All inputs V SS <V|<V DD ) 

(Recommended DC Supply Voltage (V DD - V55) 3 to 15 V) 


LIMITS 































CD4043A, CD4044A 


File No. 590 


DYNAMIC ELECTRICAL CHARACTERISTICS at Ta = 25°C, Vgs = OV, Cl = 15pF, and input rise and fall times = 20 ns, 

except t r CL and tfCL. 





LIMITS 


CHARAC- 

TERISTIC 

CURVES 

CHARACTERISTICS 

SYMBOLS 

TEST CONDITIONS 

CD4043AD.CD4043AK 

CD4044AD.CD4044AK 

CD4043AE, CD4044AE 

UNITS 




vdd 

(Volts) 








un 

BBS 


|QJ| 

ESI 



Fig. No. 

Propagation Delay Time 

t PHL< 


5 

- 

BUM 


_ 

KE 9 

KE9 



tPLH 


mrm 


■a 

yiUJI 

- 

mm 


mm 

8 


tTHL» 


5 

- 

ca 

EJ 

_ 



mm 

HI 

tTLH 


10 

- 

mm 

T71 

- 

50 

125 

mM 


tWH(S). 


5 

_ 

80 

IES3I 

_ 

80 

■m 



Pulse Width 

tWH(R) 


10 

~ 

K3 


_ 

40 

■m 

ns 

m 

Input Capacitance 

Cl 


- 

- 

• 

- 

- 

5 


PF 

■ 




Fig.8—Typ. propagation delay time vs. C[_. 


Fig.9-Typ. transition time vs. C/_. 



92CS-2020I 


Fig. 10—Typ. dissipation characteristics. 



















File No. 614 


Digital Integrated Circuits 

Monolithic Silicon 

CD4045AK CD4045AE CD4045AD 


COS/MOS 21 -Stage Counter 


Applications: 

■ Digital equipment in which ultra-low dissipation and/or 
operation using a battery source are primary design requirements. 

■ Accurate timing from a crystal oscillator for timing applications 
such as wall clocks, table clocks, automobile clocks, and digital 
timing references in any circuit requiring accurately timed outputs 
at various intervals in the counting sequence. 

■ Driving miniature synchronous motors, stepping motors, or 
external bipolar transistors in push-pull fashion. 

RCA-CD4045A is a timing circuit consisting of 21 counter 
stages, two output-shaping flip flops, two inverter output 
drivers, three 5.5 V zener diodes (providing transient pro- 
tection at 16.5 V), and input inverters for use in a crystal 
oscillator. This device may be operated over a 3 to 15 V 
supply voltage range. The CD4045A configuration provides 
21 flip-flop counting stages, and two flip-flops for shaping 
the output waveform for a 3.125% duty cycle. Push-pull 
operation is provided by the inverter output drivers. 

The first inverter is intended for use as a crystal oscillator/ 
amplifier. However, it may be used as a normal logic 
inverter if desired. 

A crystal oscillator circuit can be made less sensitive to 
voltage supply variations by the use of source resistors. In 
this device, the sources of the p and n transistors have been 
brought out to package terminals. If external resistors are 
not required, the sources must be shorted to their respective 

Maximum Ratings, Absolute-Maximum Values: 

Storage-Temperature Range 
Operating-Temperature Range: 

Ceramic packages 

Plastic package 

DC Supply Voltage Range (Vqd - V$s) 

Device Dissipation: 

(per package, including zener diodes) 

All Inputs 

Recommended DC Supply 
Voltage Range (Vqd _V SS^ 

Recommended Input Voltage Swing 
Peak Zener Diode Current 

(decay T = 80 ms) 


— 65°C to + 150°C 

— 55°C to + 125°C 
— 40°C to + 85°C 
-0.5 to + 15 V 

200 mW 
VSS < v l < V DD 


VqD to V SS 


Lead Temperature (During soldering): 

At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) 

from case for 10 seconds max 265 °C 


NOTE 1: To minimize power dissipation in the zener diodes, 
and to ensure device dissipation less than 200 mW, 
a 150 ft current-limiting resistor must be placed in 
series with the power supply for Vqd > 13 V. 

NOTE 2: Observe power supply terminal connections. Vqd 
is terminal No.3 and V§s is terminal No.14 (not 16 
' and 8 respectively, as in all other CD4000A Series 
16-lead devices). 


Features: 

■ Operation from 3 to 15 volts 

■ Microwatt quiescent dissipation 

2.5 /iW (typ.) @ VpD = 5V; 10 juW (typ.) @ Vqd = 10 V 

■ Very-low operating dissipation 

1 mW (typ.); @ Vpp = 5 V, f</> = 1 MHz 

■ Output drivers with sink or source capability 

7 mA (typ.) @ Vo = 0.5 V, Vqd = 5 V (sink) 

5 mA (typ.) @ Vo = 4.5 V, Vpo = 5 V (source) 

■ Medium speed (typ.). . . . f0 = 5 MHz @ Vdd = 5 V 

f0= 10 MHz @ Vdd= 10 V 

■ 16.5 V zener diode transient protection 

on chip for automotive use 

substrates (S p to Vdd, S|\| to Vss)- See Fig. 1. 
CD4045A types are supplied in a 16-lead flat pack, and in 
both 16-lead ceramic and plastic dual-in-line packages. 



□UQBZd 

Solid State 
Division 


222 


9-74 






H E 31 H »E [ t E Ufil lE [I E Urfil il 



HSBBjsiflifliiBflBS 

HBBBBb 



L EXTERNAL . 
COMPONENTS 




|« — I SEC "j 


Fig. 1 —CD4045A and outboard components in a typical 21-stage counter application. 


10* PLASTIC PACKAGE- 
CERAMIC PACKAGE — 


— AMBIENT TEMPERATURE <T A 1*25°C 


■pUg 



AMBIENT TEMPERATURE (Ta 1*25*C 
TYPICAL TEMPERATURE COEFFICIEN 
AT ALL VALUES OF V6S*“ 0-3 y * /< 



INPUT FREQUENCY (f*) — Hz 


DRAIN-TO-SOURCE VOLTAGE (V D s»-V 


Fig. 2— Typical dissipation vs input frequency (21 counting stages). 


Fig. 3— Typical n-channel drain characteristics. 






CD4045AK, CD4045AE, CD4045AD 


File No. 614 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V SS <V|<V DD ) 

(Recommended DC Supply Voltage (Vqq - V 55) 3 to 15 V) 


CHARACTERISTIC 

SYMBOL 


LIMITS 



TEST CONDITIONS 

CD4045AD, CD4045AK 


V DD 

Volts 

-55°C 

25°C 

| 125°C 




Typ 


n 


Quiescent Device 
Current 

'L 


5 


m 



m 


900 

]UA 

1 1 

10 

_ 

m 

- 

1 

wm 

- 


Quiescent Device 
Dissipation/Package 

Pd 


5 




0.0025 


_ 

m 

mW 


10 



- 

0.01 

BEE! 

- 

15 

Output Voltage: 
Low-Level 

v OL 

Driving 

COS/MOS 

5 


139 

- 

0 

0.01 


0.05 



10 

- 

0.01 

- 

0 

0.01 


0.05 

High-Level 

v OH 

5 

EB 1 

- 

4.99 

5 


4.95 


V 


10 

iEl 


9.99 

10 

_ 

9.95 


Noise Immunity 
(All Inputs) 

V NL 


5 

mm 


1.5 

2.25 


1.4 


V 




10 

3 


3 

4.5 


2.9 


V N H 


vo 

Volts 

5 

m 


1.5 

2.25 


1.5 


12 

10 

tn 


3 

4.5 


-3 


Output Drive Current 
N-Channel 

i d n 


0.5 

5 

wm 


3.5 

7 


2.5 


mA 



0.5 

10 

m 


5.5 

1 1 


3.9 


P-Channel 

•dp 


4.5 

5 



-2.5 

-5 


-1.8 


mA 


9.5 

10 

-5.6 


-4.5 

-9 


-3.2 


Input Current 

•l 


- 



10 

- 



PA 


Zener Breakdown 
Voltage 

V (BR)Z 

1 1 00 /XA 

13.3 

17.8 

13.5 

16.5 

18 

13.7 

18.2 

V 

7 









CHARAC- 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 
Fig .No . 

CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 


UNITS 





V DD 









Volts 




ifjj 





Quiescent Device 
Current 




5 


50 


1 

50 


700 

JUA 



<L 



10 

- 

100 

- 

2 

100 

- 

1400 

11 


Pd 



5 


0.25 


0.005 

0.25 


3.5 

mW 


Dissipation/Package 



10 


1 

- 

0.02 

1 

- 

14 


Output Voltage: 
Low-Level 

v OL 



5 


0.01 

- 

0 

0.01 

- 

0.05 



Driving 


10 


0.01 

- 

0 

0.01 

- 

0j05 





COS/MOS 


5 

4.99 


4.99 

5 


4.95 


V 


High-Level 

v OH 



10 

9.99 

_ 

9.99 

10 


9.95 





V NL 



5 

1.5 


1.5 

2.25 


1.4 




Noise Immunity 



10 

3 


3 

4.5 


2.9 

- 



(All Inputs) 

Vnh 


v 0 

5 

1.4 


115 

2.25 


1.5 


V 

12 



Volts 

10 

2.9 


3 

4.5 

- 

3 



Output Drive Current 
N-Channel 



0.5 

5 

2.2 


1.8 

7 


1,3 

_ 



I d N 


0.5 

10 

3.5 


2.8 

11 


2.0 


mA 


P-Channel 

'dp 


4.5 

5 

-1.6 


-1.3 

-5 

- 

-0.9 

- 




9.5 

10 

-2.8 

.... J 

-2.3 

-9 


-1.6 


mA 


Input Current 

'I 



1 


10 

i 



pA 


Zener Breakdown 
Voltage 

V (BR)Z 

1 100 /iA 

13.3 

17.8 

13.5 

16.5 

18 

13.6 

18.1 

V 

7 


224 












File No. 614 CD4045AK, CD4045AE, CD4045AD 

DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, V SS = 0 V, C L = 15 pF, and input rise and fall times = 20 ns, except t r 0 and t f 0 
Typical Temperature Coefficient for all values of Vqq = 0.3%/°C. 





LIMITS 


CHARAC 

TERISTIC 

CHARACTERISTICS 

SYMBOLS 

TEST CONDITIONS 

CD4045AD,CD4045AK 

CD4045AE 

UNITS 

CURVES 

8, TEST 
CIRCUITS 
Fig. No. 




V DD 

(Volts) 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 


Propagation Delay Time 

01 to y or y id out 

'PHL- 


5 


2.2 

4.4 


2.2 

5.5 


8 

’PLH 


10 


1.2 

2.4 


1.2 

3.3 

/Js 

Transition Time 

*TH L> 


5 


450 

800 


450 

900 

ns 

9 

•TLH 


10 


375 

650 


375 

750 

Minimum Input- 

>WL- 


5 


100 

115 


100 

140 



Pulse Width 

>WH 


10 


50 

60 


50 

75 

ns 


Input Pulse 

1 , 0. 


5 



15 



15 

V* 


Rise & Fall Time 

t,0 


10 



10 



10 


Maximum Input-Pulse 
Frequency 



... ■% . 

4.4 

5 


3.5 

5 




<m 0 


10 

8.5 

10 


6.5 

10 


MH/ 

10 

Input Capacitance 

C| 

Any Input 


b 



5 


PF 




92CS- 20897 

Fig. 4— Minimum n-channel drain characteristics. 


DRAIN TO SOURCE VOLTAGE (V D sl-V 



Fig. 6 — Minimum p-channel drain characteristics. 


DRAIN TO SOURCE VOLTAGE (Vds'~ V 



Fig. 5— Typical p-channel drain characteristics. 



Fig. 7 — Typical zener diode characteristics. 


225 








(0J TO y OR y+d OUT ) PROPAGATION DELAY TIME 
_ (, PHL'’PLH 1_ M S 


CD4045AK, CD4045AE, CD4045AP 


File No. 614 



6 8 10 12 14 

SUPPLY VOLTAGE (V 0D )-V 

92CS-20955 



52 55 :H5 4m AMBIENT TEMPERATURE (Ta>-25*C 
55 55 TYPICAL TEMPERATURE COEFFICIENT 
o nW wTm 1) iTTTn I nn AT all values of vpp» o.3%/*c 

10 20 30 4 0 50 60 70 £ 

LOAD CAPACITANCE (C|J— pF 


Fig. 8— Typical propagation delay ($j to y or y+d out) vs Vqq. 


Fig. 9— Typical transition time vs Cq. 


•2| AMBIENT TEMPERATURE (Ta>*25*C 


°2 4 6 






6 8 10 12 14 16 

SUPPLY VOLTAGE (V D0 )—V 

92CS-20903 



Fig. 10-Minimum f m 0 vs Vqq for CD4045AD and. CD4045AK. 


Fig. 11 — Quiescent device current test circuit. 


1 

<#>| 16 

2 

'5 

3 

14 

4 

13 

5 

12 

6 

II 

7 

10 

8 

9 


o — O 

1.5 V OR 3 V 


92CS-22889RI 

Fig. 12 — Noise immunity test circuit. 








File No. 637 


Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4046AD CD4046AE 
CD4046AK CD4046AH 







PHASE 

PULSES 

l« 


16 

V DD 

PHASE COMP 

I CUT 

2 


15 

ZENER 

COMPARATOR 

IN 

3 


14 

SIGNAL IN 

VCO OUT 

4 

TOP 

13 

PHASE COMP 

T H OUT 

INHIBIT 

3 

VIEW 

12 

R2T0 V SS 

ci(i) — 

6 


II 

Rl TO V ss 

CK2) 

7 


K> 

DEMODULATOR 

OUT 

v S s— 

8 


9 

VCO IN 

TERMINAL ASSIGNMENT 

C04046AD 

C04046AE 

C04046AK 





92CS-Z07J7 


COS/MOS Micropower 
Phase-Locked Loop 


Features: 

■ Very low power consumption . . 70 pW (typ.) at VCO f o =10 kHz. Vqd =5 V 

■ Operating frequency range up to 1.2 MHz (typ.) at Vqq= 10 V 

■ Wide supply-voltage range Vqd — V$s = 5 to 15 V 

■ Low frequency drift . . 0.06%/°C (typ.) at VqD = 10 V 

■ Choice of two phase comparators . 1. Exciusive-OR network 

2. Edge-controlled memory network with 
phase-pulse output for lock indication 

■ High VCO linearity 1% (typ.) 

■ VCO inhibit control for ON-OFF keying and ultra-low standby 
power consumption 


The RCA-CD4046A COS/MOS Micropower Phase-Locked 
Loop (PLL) consists of a low-power, linear voltage-controlled 
oscillator (VCO) and two different phase comparators having a 
common signal-input amplifier and a common comparator in- 
put. A 5.2- V zener diode is provided for supply regulation if 
necessary. The CD4046A is supplied in a 16-lead dual-in-line 
ceramic package (CD4046AD), a 16-lead dual-in-line plastic 
package (CD4046AE), and a 16-lead flat pack (CD4046AK). 
It is also available in chip form (CD4046AH). 

VCO Section 

The VCO requires one external capacitor Cl and one qr two 
external resistors (R1 or R1 and R2). Resistor R1 and capaci- 
tor Cl determine the frequency range of the VCO and resistor 
R2 enables the VCO to have a frequency offset if required. 
The high input impedance (lO^fi) of the VCO simplifies the 
design of low-pass filters by permitting the designer a wide 
choice of resistor-to-capacitor ratios. In order not to load the 
low-pass filter, a source-follower output of the VCO input 
voltage is provided at terminal 10 (DEMODULATED OUT- 
PUT). If this terminal is used, a load resistor (Rs) of 10 k Ct or 
more should be connected from this terminal to Vgg. If 
unused this terminal should be left open. The VCO can be 
connected either directly or through frequency dividers to the 
comparator input of the phase comparators. A full COS/MOS 
logic swing is available at the output of the VCO and allows 
direct coupling to COS/MOS frequency dividers such as the 
RCA-CD4024A,CD4018A,CD4020A.CD4022A. or CD4029A. 
One or more CD4018A (Presettable Divide-by-N Counter) or 
CD4029A (Presettable Up/Down Counter), together with the 
CD4046A (Phase-Locked Loop) can be used to build a micro- 
power low-frequency synthesizer. A logic 0 on the INHIBIT 
input "enables" the VCO and the source follower, while a logic 
1 "turns off" both to minimize stand-by power consumption. 


a Source-follower output of VCO control input 
(Demod. output) 

b Zener diode to assist supply regulation 

Applications: 

■ FM demodulator and modulator 

■ Frequency synthesis and multiplication 

■ Frequency discriminator ■ Tone decoding 

■ Data synchronization b FSK - Modems 

■ Voltage-to-frequency conversion ■ Signal conditioning 

(See I CAN-61 01 for application information and 
circuit details) 



Fig. 1 — COS/MOS phase-locked loop block diagram. 


227 








CD4046AD, CD4046AE, CD4046AK, CD4046AH 


File No. 637 


Phase Comparators 

The phase-comparator signal input (terminal 14) can be direct- 
coupled provided the signal swing is within COS/MOS logic 
levels [logic "0” < 30% (Vdd~ v SS)/ logic "1" > 70% 
(Vdd—Vss)) ‘ ^ or sma ^ er sw * n 9 s the signal must be capaci- 
tively coupled to the self-biasing amplifier at the signal input. 
Phase comparator I is an exclusive-0 R network; it operates 
analagously to an over-driven balanced mixer. To maximize 
the lock range, the signal- and comparator-input frequencies 
must have a 50% duty cycle. With no signal or noise on the 
signal input, this phase comparator has an average output 
voltage equal to Vqd/ 2. The low-pass filter connected to the 
output of phase comparator I supplies the averaged voltage to 
the VCO input, and causes the VCO to oscillate at the center 
frequency (f Q ). 

The frequency range of input signals on which the PLL will 
lock if it was initially out of lock is defined as the frequency 
capture range (2f c ). 

The frequency range of input signals on which the loop will 
stay locked if it was initially in lock is defined as the frequency 
lock range (2f[_).The capture range is < the lock range. 

With phase comparator I the range of frequencies over which 
the PLL can acquire lock (capture range) is dependent on the 
low-pass-filter characteristics, and can be made as large as the 
lock range. Phase-comparator I enables a PLL system to remain 
in lock in spite of high amounts of noise in the input signal. 

One characteristic of this type of phase comparator is that it 
may lock onto input frequencies that are close to harmonics of 
the VCO center-frequency. A second characteristic is that the 
phase angle between the signal and the comparator input varies 
between 0° and 1 80°, and is 90° at the center frequency. Fig. 2 
shows the typical, triangular, phase-to-output response charac- 



92CS-20009 


SIGNAL INPUT (TERM. 14) 

VCO OUTPUT (TERM 4). 
COMPARATOR INPUT 
(TERM 3) 


VCO INPUT (TERM. 9)« 
LOW- PASS FILTER 
OUTPUT 


JT-TLTLT 


•v DD 


— Vss 

92CS-2O0I0RI 


Fig. 3 — Typical waveforms for COS/MOS phase-locked loop em- 
ploying phase comparator / in locked condition of f Q . 


duty cycles of the signal and comparator inputs are not im- 
portant since positive transitions control the PLL system uti- 
lizing this type of comparator. If the signal-input frequency is 
higher than the comparator-input frequency, the p-type out- 
put driver is maintained ON continuously. If the signal-input 
frequency is lower than the comparator-input frequency, the 
n-type output driver is maintained ON continuously. If the 
signal- and comparator-input frequencies are the same, but the 
signal input lags the comparator input in phase, the n-type out- 
put driver is maintained ON for a time corresponding to the 
phase difference. If the signal- and comparator-input frequen- 
cies are the same, but the comparator input lags the signal in 
phase, the p-type output driver is maintained ON for a time 
corresponding to the phase difference. Subsequently, the capa- 
citor voltage of the low-pass filter connected to this phase 
comparator is adjusted until the signal and comparator inputs 
are equal in both phase and frequency. At this stable point 
both p- and n-type output drivers remain OFF and thus the 
phase comparator output becomes an open circuit and holds 
the voltage on the capacitor of the low-pass filter constant. 
Moreover the signal at the "phase pulses" output is a high level 
which can be used for indicating a locked condition. Thus, 
for phase comparator II, no phase difference exists between 
signal and comparator input over the full VCO frequency 
range. Moreover, the power dissipation due to the low-pass 
filter is reduced when this type of phase comparator is used 
because both the p- and n-type output drivers are OFF for most 
of the signal input cycle. It should be noted that the PLL lock 
range for this type of phase comparator is equal to the capture 
range, independent of the low-pass filter. With no signal 
present at the signal input, the VCO is adjusted to its lowest 
frequency for phase comparator II. Fig. 4 shows typical wave- 
forms for a COS/MOS PLL employing phase comparator II in 
a locked condition. 


Fig.2 — Phase-comparator / characteristics 
at low-pass filter output. 

teristic of phase-comparator I. Typical waveforms for a COS/ 
MOS phase-locked-loop employing phase comparator I in 
locked condition of f 0 .is shown in Fig. 3. 

Phase-comparator II is an edge-controlled digital memory net- 
work. It consists of four flip-flop stages, control gating, and a 
three-state output circuit comprising p- and n-type drivers hav- 
ing a common output node. When the p-MOS or n-MOS 
drivers are ON they pull the output up to Vqd or down to 
Vss» respectively. This type of phase comparator acts only on 
the positive edges of the signal and comparator inputs. The 


SIGNAL INPUT (TERM. 14) 


VCO OUTPUT (TERM 4 ) * 
COMPARATOR INPUT 
(TERM 3) 

PHASE COMPARATOR II 
OUTPUT (TERM. 13) 


VCO INPUT (TERM. 9) = 

* LOW-PASS FILTER 
OUTPUT 

PHASE PULSE (TERM. I ) 



NOTE: DASHED LINE IS AN OPEN-CIRCUIT CONDITION 92CS-200IIRI 

Fig.4 — Typical waveforms for COS/MOS phase-locked loop em- 
ploying phase comparator II in locked condition. 


228 



File No. 637 CD4046AD, CD4046AE, CD4046AK, CD4046AH 


DESIGN INFORMATION 

This information is a guide for approximating the values of 
external components for the CD4046A in a Phase-Locked- 
Loop system. The selected external components must be 
within the following ranges: 


10 kft < R1, R2, R$ < 1 MS2 
Cl > 100 pF at Vqd> 5 V; 

Cl > 50 pF at Vqd > 10 V 

In addition to the given design information refer to Fig. 5 
for R1, R2, and Cl component selections. 


CHARACTERISTICS 

USING PHASE COMPARATOR 1 

USING PHASE COMPARATOR II 

VCO WITHOUT OFFSET 

R 2 “ 00 

VCO WITH OFFSET 

VCO WITHOUT OFFSET 
r 2 - - 

VCO WITH OFFSET 

VCO Frequency 

f MAX 

fo 

f MIN 

7fL 

f MAX 

1 MIN 

i 

f MAX 

»0 

^ f MIN 


f MAX 

f|flN 

— i ” 

i 

V 0D /2 V 00 

VCO INPUT VOLTAGE 


V DD' 2 V D0 

VCO INPUT VOLTAGE 

V 0D /2 V DD 

VCO INPUT VOLTAGE 


Voo 72 v dd 

VCO INPUT VOLTAGE 

92CS-200I2SI 

For No Signal Input 

VCO in PLL system will adjust to center frequency, f 0 

VCO in PLL system will adjust 
to lowest operating frequency, f m j n 

Frequency Lock Range,2f l 

2 f|_ = full VCO frequency range 

2 f L = fmax - fmin 

Frequency Capture 

Range, 2fc 

Loop Filter 
Component 

Selection 

IN R3 OUT 

O-A/W* O (D.I2) 

7l«R3C2 4=C2 2f C ^ 

_L ^ 7T V 71 

fC = fL 

IN R3 OUT 

O — VW-t — o 

< R4 For 2 f c , see Ref. (2) 

ic2 

_j_ 92CS-2I90I 

Phase Angle between 

Signal and Comparator 

90° at center frequency <f 0 ), approximating 0° and 
180° at ends of lock range (2f |_) 

Always 0° in lock 

Locks on Harmonics of 
Center Frequency 

Yes 

No 

Signal Input Noise 
Rejection 

High 

Low 

VCO 

Component 

Selection 

— Given: fj, 

— Use f Q with Fig.5a to 
determine R1 and Cl 

— Given: f and f|_ 

— Calculate f m j n from 
the equation 

fmin = fo — fL 

— Use fmin withFig. 5b 
to determine R2 and Cl 

fmax 

— Calculate 

•min 

from the equation 
fmax fo + fL 

fmin f o~ f L 
f max . 

— Use-^ — — with 

Fig. 5c to determine 
ratio R2/R1 to obtain 
R1 

- Given: f max 

- Calculate f D from 
the equation 

f max 

f°“ 2 

- Use f Q with Fig. 5a to 
determine R1 and Cl 

— Given: f m j n & f ma x 

— Use f m j n with Fig.5b 
to determine R2andC1 

fmax 

— Calculate t 

T min 

f max _ „ 

— Use 1 with Fig.5c 

T min 

to determine 
ratio R2/R1 to 
obtain R.1 


For further information, see 

(1) F. Gardner, "Phase-Lock Techniques'*. John Wiley and Sons, New York, 1966 

(2) G. S. Moschytz, "Miniaturized RC Filters Using Phase-Locked Loop", BSTJ, May, 1965. 


229 





































CD4046AD, CD4046AE, CD4046AK, CD4046AH . 


File No. 637 


ELECTRICAL CHARACTERISTICS AT Ta = 25°C 



'CO Section 

perating Supply Voltage 

vdd-Vss 

As fixed oscillator only 

Phase-lock-loop operation 




R1=10kft | Cl = 100 pF 
R2 = °° 

VCO| N *= V DD 


Frequency Range 


Temperature-Frequency Stability : 
No Frequency Offset 
f MIN = 0 


Frequency Offset 
fMIN^ 


Input Resistance of VCOjn 
(T erm 9) 


i/CO Output Voltage (Term 4) 
Low Level 




VCO Output Drive Current: 
n-Channet (Sink) 


Source-Follower Output 
(Demodulated Output): 

Offset Voltage (VCO|N-VqEm) 


Linearity 



VCOin = 2.5 V ±0.3 V, R1 >10 kft 

5 1 

= 5 V ± 2.5 V, R1 >40Q kfi 

10 

= 7.5 V ±5 V, R1 * 1 MfZ 

15 

%/°C oc 1 


5 

R2 = °° f'VoD 


10 



15 

%/°Ccc — ! — 


5 

10 

f*V D o 




15 


5,10,15 



5,10,15 

Driving COS/MOS-Type j 

5 

Load (e.g. Term 3 


10 

Phase Comparator Input) 

15 



5,10,15 



5 


v 0 

10 


VOLTS 

15 


0.5 

5 


0.5 

10 


4.5 

5 


9.5 

10 




230 












































File No. 637 


CD4046AD, CD4046AE, CD4046AK, CD4046AH 


ELECTRICAL CHARACTERISTICS AT Ta = 25°C 


CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 


LIMITS 

CD4046AD, CD4046AK 
CD4046AE 

UNITS 

CHARAC- 

TERISTIC 

CURVES 

8. TEST 
CIRCUITS 
FIG. NO. 


v 0 

VOLTS 

Vdd 

VOLTS 

MIN. 

TYP. 

MAX. 

PHASE COMPARATOR Section j 

Operating Supply Voltage 

V DD~ V SS 

Amplifier Operation 

_ 

5 

- 

15 


- 

Comparators only 


3 

~ 

15 

V 

~ 

Total Quiescent Device Current: 

Term. 14 Open 

II 

Term. 15 open 

Term. 5 at Vqq 

Terms. 3 & 9 at Vgs 

5 

10 

- 

25 

200 

55 

410 

HA 

- 

Term. 14 at Vss or V DD 

5 

10 

: 

5. 

25 

15 

60 

Term. 14 (SIGNAL IN) 

Input Impedance 

Z 14 


5 

10 

15 

i 

0.2 

2 

0.4 

0.2 

— 

m£1 


AC-Coupled Signal Input 

Voltage Sensitivity 



5 

10 

15 

~ 

200 

400 

700 

400 

800 

mV 

7 

DC-Coupled Signal Input 
and Comparator Input 

Voltage Sensitivity: 

Low Level 



5 

10 

15 

1.5 

3 

4.5 

2.25 

4.5 

6.75 



- 

High Level 



v 0 

VOLTS 

5 

10 

15 

- 

2.75 

55 

8.25 

3.5 

7 


- 

Output Drive Current: 

n-Channel (Sink) 

I d n 

Phase Comparator 
I& IlTerm. 2 & 13 

0.5 

0.5 

5 

10 

0.43 

1.3 

0.86 

2.5 


mA 

- 

Phase Pulses 

0.5 

0.5 

5 

10 

0.23 

0.7 

0.47 

1.4 


- 

p-Channel (Source) 

Id p 

Phase Comparator 
I& II Term. 2 & 13 

4.5 

9.5 

5 

10 

-0.3 

-0.9 

-0.6 

-1.8 



Phase Pulses 

4.5 

9.5 

5 

10 

-0.08 

-0.25 

—0.16 

-0.5 




. MAXIMUM RATINGS, Absolute-Maximum Values: 


Storage Temperature Range 1 .... -65°Cto+150 °C 

Operating Temperature Range: 

Ceramic Package Types — 55°Cto+125 °C 

Plastic Package Types — 40°C to +85 °C 

DC Supply Voltage Range 

(Vqd-Vss) -0.5 V to +15 V 

Device Dissipation (Per Pkg.) . 200 mW 

All Inputs Vss^V|<VdD 

Lead Temperature (During soldering): 

At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) 

from case for 10 seconds max. . . 265 °C 


231 




VCO POWER DISSIPATION (P D ) 




VCO TIMING CAPACITOR (CI)-uF VC0 

92CS-2I883 

Fig. 5(a) — Typical center frequency vs Cl for R1 = 10 kSl, Fig.5(b) — Typical frequenc] 

and 1 MSI. and 1 MSI. 

NOTE: Lower frequency values are obtainable if larger values of Cl 
than shown in Figs. 5(a) and 5(b) are used. 


VCO TIMING CAPACITOR (CI)-^F 

92CS- 21884 

Fig.5(b) — Typical frequency offset vs Cl for R2= 10 kSl, 100 kSl 
and 1 MSI. 



6[- AMBIENT TEMPERATURE (T A ) = 25°C 
T VCO|N=V 0D /2,R2*© 



R2/RI 

Fig.5(c) - Typical f max /f min vs R2/R1. 


- AMBIENT TEMPERATURE (T A )=25°C 
~ VCO |N S V $S 

: l _ 







Cl = 50 pF 
'/*F 

*n pP 



i m f 

50 pF 

!: 

2 - 

1 1 1 1 

- 1 fiF 

1 1 1 l_ 


Rl-Kft 

Fig.6(a) — Typical VCO power dissipation at center frequency 
vs R1. 


- AMBIENT TEMPERATURE (T A ) = 25°C 
~ VC0|N = V DD /2, RI = R2 = 00 

: i 







r P 

: 



I L 

1 ■ JL 1 

1 1 1 l_ 


R2-K SI 92CS-2I887 Rs - 

Fig. 6(b) - Typical VCO power dissipation at f mjp vs R2. Fig. 6(c) - Typical source follower power dissipation vs R s . 

NOTE: To obtain approximate total power dissipation of PLL system for no-signal input 
P D (Total) = P D (f Q ) + P D (f M | N ) + P D - Phase Comparator I 

P D (Total) = P D (f|\/i|[u) - Phase Comparator II 













File No. 623 



Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4047AD CD4047AE CD4047AK 



COS/MOS Low-Power 
Monostable/Astable Multivibrator 

Special Features: 

■ Low power consumption: special COS/MOS oscillator configuration 

■ Monostable (one-shot) or astable (free-running) operation 

■ True and complemented buffered outputs 

■ Only one external R and C required 

Monostable Multivibrator Features: 

■ Positive- or negative-edge trigger 

■ Output pulse width independent of trigger pulse duration 


RCA-CD4047A consists of a gatable astable multivibrator 
with logic techniques incorporated to permit positive or 
negative edge-triggered monostable multivibrator action having 
retriggering and external counting options. 

Inputs include +Trigger, —Trigger, Astable, Astable, Retrigger, 
and External Reset. Buffered outputs are Q, Q, and Oscillator. 
In all modes of operation an external capacitor must be con- 
nected between C-Timing and RC-Common terminals, and an 
external resistor must be connected between the R-Timing and 
RC-Common terminals. 

Astable operation is enabled by a high level on the Astable 
input. The period of the square wave at the Q and Q outputs 
in this mode of operation is a function of the external com- 
ponents employed. "True" input pulses on the Astable input 
or "Complement" pulses on the Astable input allow the circuit 
to be used as a gatable multivibrator. An output whose period 
is half of that which appears at the Q terminal is available at 
the Oscillator Output terminal. However, a 50% duty cycle is 
not guaranteed at this output. 


R 



92CS- 20026R2 

Fig. 1 — CD4047A logic block diagram. 


■ Retriggerable option for pulse width expansion 

■ Long pulse widths possible using small RC components by 
means of external counter provision 

■ Fast recovery time essentially independent of pulse width 

■ Pulse-width accuracy maintained at duty cycles approaching 
100% 

Astable Multivibrator Features: 

■ Free-running or gatable operating modes 

■ 50% duty cycle 

■ Oscillator output available 

■ Good astable frequency stability: 

frequency deviation = ±2% + 0.03%/°C @100 kHz* 

= ±0.5% + 0.015%/°C @ 10 kHz* 

COS/MOS Features: 

■ Microwatt quiescent power dissipation: 0.5/iW(Typ) 

■ High noise immumity: 45% of supply voltage (Typ) 

■ Wide operating-temperature range: ceramic package 
types, — 55°C to + 125°C; plastic package types, — 40°C 
to +85°C 

Applications: 

Digital equipment where low-power dissipation and/or high 
noise immunity are primary design requirements: 

■ Frequency discriminators ■ Envelope detection 

■ Timing circuits ■ Frequency multiplication 

h Time-delay applications ■ Frequency division 


* Circuits "trimmed" to frequency; Vqq = 10 V ± 10%. 


234 


9-74 









File No. 623 CD4047AD, CD4047AE, CD4047AK 


A high level should be applied to the external reset whenever 
Vqd is applied or removed. In the monostable mode positive- 
edge triggering is accomplished by application of a leading-edge 
pulse to the "+Trigger" input and alow level to the "—Trigger" 
input. For negative-edge triggering a trailing-edge pulse is 
applied to the "—Trigger" and a high level is applied to the 
"+Trigger". Input pulses may be of any duration relative to the 
output pulse. The multivibrator can be retriggered (on the 
leading edge only) by applying a common pulse to both the 
"Retrigger" and "+Trigger" inputs. In this mode the output 
pulse remains "high" as long as the input pulse period is shorter 
than the period determined by the RC components. 

An external countdown option can be implemented by 
coupling "Q" to an external "N" counter (e.g. CD4017A) 
and resetting the counter with the trigger pulse. The counter 
output pulse is fed back to the Astable input and has a dura,- 
tion equal to N times the period of the multivibrator. 

A high level on the External Reset input assures no output 
pulse during an "ON" power condition. This input can also 
be activated to terminate the output pulse at any time. 

This device is supplied in a 14-lead flat pack (CD4047AK), a 
14-lead dual-in-line ceramic package (CD4047AD), or a 14-lead 
dual-in-line plastic package (CD4047AE). It is also available 
in chip form (CD4047AH). 


MAXIMUM RATINGS, Absolute-Maximum Values: 
Storage-Temperature Range . . . —65 to +150 °C 

Operating-Temperature Range: 

Ceramic Package Types .... —55 to +125 °C 

Plastic Package Types —40 to +85 °C 

DC Supply-Voltage Range 

(Vdd-Vss) -0.5 to +15 V 

Device Dissipation (Per Pkg.) . . . 200 mW 

All Inputst Vss^Vi^Vqd V 

Recommended 
DC Supply Voltage 

(Vdd-Vss) 3toi5 v 

Recommended 

Input Voltage Swing Vqd to V$S V 


t In normal operation of the CD4047A, signals at terminal 3 
may go above Vqd or below Vss> therefore a different 
gate-oxide protection circuit is used that is only 30 per cent 
as effective as the static-discharge protection at other termi- 
nals in the device. Additional care in following the guidance 
of I CAN-6000 is advised for this device. 


CD4047A FUNCTIONAL TERMINAL CONNECTIONS 

NOTE: IN ALL CASES EXTERNAL RESISTOR BETWEEN TERMINALS 2 AND 3* 
EXTERNAL CAPACITOR BETWEEN TERMINALS 1 AND 3* 



TERMINAL CONNECTIONS 


OUTPUT PERIOD 

FUNCTION 

TO Vqd 

TO V S S 

INPUT PULSE 

TO 

OUTPUT PULSE 
FROM 

OR 

PULSE WIDTH 

Astable Multivibrator: 

Free Running 

4, 5, 6, 14 

7, 8, 9, 1 2 


10, 11, 13 

t/\(10,1 1 )=4.40 RC 

True Gating 

4, 6, 14 

7, 8, 9, 12 

5 

10, 11, 13 

t A (13)=2.20 RC 

Complement Gating 

6, 14 

5, 7. 8, 9, 12 

4 

10, 11, 13 

Monostable Multivibrator: 

Positive-Edge Trigger 

4, 14 

5, 6, 7, 9, 12 

8 

10, 11 


Negative-Edge Trigger 

4, 8, 14 

5, 7, 9, 12 

6 

10, 11 

tjvi ( 1 0, 1 1 )=2.48 RC 

Retriggerable 

4, 14 

5, 6, 7. 9 

8, 12 

10, 11 

External Countdown* 

14 

5. 6, 7, 8, 9, 12 

- 

10, 11 



* Input Pulse to Reset of External Counting Chip 
External Counting Chip Output to Terminal 4 
A See Text. 


235 




CD4047AD, CD4047AE, CD4047AK 


File No. 623 



** MODIFIED INPUT PROTECTION 
CIRCUIT TO PERMIT LARGER 
INPUT- VOLTAGE SWINGS 


Fig. 2 — CD4047A logic diagram. 


AMBIENT TEMPERATURE (T A W25°C 
TYPICAL TEMPERATURE COEFFICIENT AT ALL VALUES [ 
OF V GS = -0.3 •/./•C 





GATE -TO 

-SOURCE VOLTAGE '( Vge)'« ' 1 5 

V 

ssssssssssss: 

■SSSSSSSSSSSSS 

■■BBBBBBBBBBBBBBBBBI 

■BBBBBBBBBBBBBBBBBBI 

■■BBBBBBBBBBBBBBBBBI 


:::r;ss:ss£.« 

sssssssssssss 



SiSSSSSEEKSS 





DRAIN-TO-SOURCE VOLTAGE <Vds>— V 

92CS-2I386 


AMBIENT TEMPERATURE (T A )»25°C 
TYPICAL TEMPERATURE COEFFICIENT AT ALLVALUESI 
OF Vgs*-Q- 3 %/ j C - 


ft GATE-TO-SOURCE VOLTAGE ( V 6S ) = 15 VT 


ISSaS 88888 

■BB^BBBBBBBBBBI 
mwAummmm 
VJBBBBBB 
-4BBBBBC= 

IFWIHII 


muammmmuumummm 


s sssssssssssss: 

MMSSSSSSSSSl 

ssssssssssss 


sssssssssssssssl 


DRAIN-TO-SOURCE VOLTAGE (Vds>— V 


Fig. 3 — Typical n-channel drain characteristics for Q and Q buffers. Fig.4 — Minimum n-channel drain characteristics for Q and Q buffers. 


236 





File No. 623 CD4047AD, CD4047AE, CD4047AK 


STATIC ELECTRICAL CHARACTERISTICS (All inputs . V S S < V, < V DD ) 

(Recommended DC Supply Voltage (Vqq — V<jg) 3 to 15 V) 


STATIC ELECTRICAL CHARACTERISTICS (All inputs . V S S < V, < V DD ) 

(Recommended DC Supply Voltage (Vqq — V<jg) 3 to 15 V) 


CHARACTERISTIC 

SYMBOL 

TEST 

LIMITS 

UNITS 

CHARAC- 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 
Fig. No. 

CONDITIONS 

CD4047AD, CD4Q47AK 


v 0 

Volts 

VDD 

Volts 

-55°C 

25°C 

125°C 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Quiescent Device 
Current 



H 

_ 

_ 

5 

_ 

FliFI 

5 

- 

- 

KiTiM 

pA 


El 

- 

- 

EM 

- 


EM 

- 

- 

600 

Quiescent Device 
Dissipation Package 



5 

_ 

_ 

wm 

_ 


wm 

- 

- 

1500 



KB 

- 

- 

ITTil 

- 

OX 

100 

- 


Em 

Output Voltage 

Low Level 



6 

_ 

_ 

Hjflj 

- 


IfflTI 

_ 

- 

fiTT^ 



El 

- 

- 

wm 

- 

0 

fiTTl 

- 

- 


High Level 

VOH 


5 

KE9 

- 


1CS1 

5 

- 


- 


V 


10 

9.99 

- 

- 

9.99 

10 

- 

9.95 

- 

- 

Noise Immunity 
(All Inputs) 

v NL 

VNH 


4.2 

5 

1.5 

_ 

_ 

1.5 

2.25 

- 

1.4 

_ 

_ 

V 


9 

10 

3 

- 

- 

3 

4.5 

- 

2.9 

- 

- 

0.8 

5 

1.4 

_ 

_ 

1.5 

2.25 

- 

1.5 

_ 

_ 

V 

1 

10 

2.9 

- 

- 

3 

4.5 

- 

3 

- 


Output Drive Current 
(Q, Q Outputs) 
N-Channel 

IqN 

idP 


0.5 V 

5 

0.5 

_ 

_ 

0.4 

0.8 

_ 

0.28 

_ 

_ 



0.5 V 

10 

1.25 

- 

- 

1 

2 

- 

0.7 

- 

- 

P-Channel 

4.5 V 

5 

-0.5 

- 

- 

-0.4 

-0.8 

- 

-0.28 

- 

- 


m 

9.5 V 

10 

-1.25 

- 

- 

-1 

-2 

- 

-0.7 


- 

Input Current 

l| 

Any Input 


- 

- 


- 

10 


- 

- 

- 


M 1 


DRAIN-TO-SOURCE VOLTAGE (Vos' — V DRAIN-TO- SOURCE VOLTAGE (Vds> — V 




Fig-5 — Typical p-channel drain characteristics for Q and Q buffers. Fig.6 — Minimum p-channel drain characteristics for Q and Q buffers. 


237 








CD4047AD, CD4047AE, CD4047AK 


File No. 623 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < V l < V DD> 

(Recommended DC Supply Voltage (Vqq — Vgg) 3 to 15 V) 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < V l < V DD ) 

(Recommended DC Supply Voltage (Vqq — Vgg) 3 to 15 V) 




TEST 


LIMITS 


CHARAC- 

TERISTIC 

CHARACTERISTIC 

•SYMBOL 

CONDITIONS 

CD4047AE 

UNITS 

CURVES 

8i TEST 
CIRCUITS 

| 

Vo 



25°C 

85°C 




■ 

Volts 



ESI 

ESI 


BIB 

1223 

i!M 

mb 

jesm 


Fig. No. 

Quiescent Device 



WM 

- 

_ 

C9 

_ 

eh 

EE 

_ 

_ 

31 






10 

- 

- 

| EU 

- 

ETl 

Brtu 

- 

- 

EU 

33 | 

Quiescent Device 



5 

_ 

_ 


- 

wm 

WWW 

_ 

_ 



■ 

Dissipation Package 


m 

- 

- 


- 

3 


- 

- 

KBtHil 


Output Voltage 



5 

- 

- 


- 

n 

rm 

_ 

_ 



■ 

Low Level 


IB 

- 

- 

qq 

- 

mi 


- 

- 

IT 

V 


High Level 



n 

iwsn 

- 

- 

4.99 

5 

- 

4.95 

- 

- 


■ ■ 


El 

EEE1 

- 

- 

KTEEl 

ma 

- 

32^3 

- 

- 





■ 

wm 

m 

ra 

- 

_ 

■9 

ffEl 

_ 

Mn 

_ 

_ 


■ 

Noise Immunity 
(All Inputs) 

1 

9 

E3 

3 

- 

- 

3 

ESI 

- 

m 

- 

- 


B 


I 

rm 

il 

1.4 

_ 

_ 

m 

E HI 

_ 

mb 

_ 

_ 


1 

> 

m 

2.9 

- 

- 

3 

mi 

- 

3 

- 

- 


Output Drive Current 


■ 


m 

WRI 

_ 

_ • 



_ 


_ 

_ 


mm 

(Q, Q Outputs) 
N-Channel 

I 


a 

ft 

- 

- 

KB 

H 

- 


- 

- 

Hi 

P-Channel 


1 



BPS 

- 

- 

cbi 

BfTl 

- 



- 



1 

HETB 

m 

-0.85 


- 


-2 

- 

32 

- 

- 

■■I 

Input Current 



■ 

- 

- 

- 


m 

- 

- 

- 

- 




f 

'x 

CL 

UJ 

AMBIENT TEMPERATURE (Ta)*25*C 

TYPICAL TEMR COEFFICIENT AT ALL VALUES OF V| 

DD 

•0.3 %/*C 






44 

44 





-- 


















tt 

H 





: 


::: 



:: 












■ 

■ 





:: 


::: 


:: 

:: 








piooo 

5 

Q 800 



■ 

■ 









::: 


MB 

:: 





IBI 

IBI 





■ 








III 

iii 


is: 

:: 






tt 






■ 

s 



TT 


++- 

f+ 

VO 

4-4- 

LTA 

+4-4- 

GE 

vnn> 

*5 

V 





Ml 


z 

o 

5 600 





;; 


■■l 

■■1 




== 

[1 


m 

W 

s 

I 





S 






■i 


■■1 



■■i 




■■i 

(■■i 

■■ 

II 


IBI 

IBI 

IBI 

IBI 


i 

o 











li 


■ 

■■i 

is- 

si 

» 

ii 

ii! 

Isl 

SE! 

Ss! 

1 











■■ 



■■i 


ss 

IB 

Bl 

IBI 





a. 400 

UJ 











", 


tt 

m 

tt= 

Ut 

SE 

t 








— ■ 

--- 







--- 

it 

m 

■■■ 

■■■ 


M 









[si 

is: 

■ 1 


IBI 

■5! 


Ml 

— 

tt 

m 

111 

IBB 

5 







HIGH-L 

c 

o 



■■i 

Ml 

■1 

■■1 

■■1 

■li 

mi 

iii 

iii 

iii 

i 

■Si 

■55 

■Si 

M 


IBI 

IBI 

IBI 

IBI 




Ml 

Ml 

■1 

Ml 

Ml 

TT 

44 

44 

m 

■■i 

■ 

■■i 


■■i 



SS! 

IBI 



•I 



0 

g 

i! 

Ml 

0 

TT 

■Si 

SS! 

■SS 

is: 

S 

■Si 

Ml 

SSI 



IBI 

ss: 

ss: 

IBI 

1 

0 



IC 


■ 

20 


3( 


■ 

*0 


5C 


60 

-i-i. 

7 

0 


8C 


C 

>0 


LOAD CAPACITANCE (Ci) — pF 

92CS-2I439 

Fig.7 — Typical low-to-high level propagation delay time vs. load 
capacitance for Q and Q buffers. 



238 



















File No. 623 


CD4047AD, CD4047AE, CD4047AK 


DYNAMIC ELECTRICAL CHARACTERISTICS atT A = 25°C, V S s = 0 V, C L = 15 pF 
Typical Temperature Coefficient at all values of Vdd = 0.3%/°C 


CHARACTERISTICS 

SYMBOLS 


LIMITS 

UNITS 

TEST CONDITIONS 

CD4047AK 

CD4047AD 

CD4047AE 


Vdd 

(Volts) 

MIN. 



MIN. 

TYP. 

MAX. 

Propagation Delay Time; 
Astable, Astable 

to 

Osc. Out 



5 


200 

400 


200 

550 

ns 


- 


200 

- 

100 

275 

Astable, Astable 

to 

Q, Q 



5 

_ 



_ 


1200 

10 

- 

250 

500 

- 

250 

650 

+Trigger, -Trigger 

to 

Q, Q 

l PHL, 


5 

_ • 

700 

1200 

_ 



10 

- 

300 

600 

- 


800 

+Trigger, Retrigger 

to 

Q, Q 

tpLH 


5 

_ 

300 

600 

. 

300 

800 

10 

- 

175 

300' 

- 



External Reset 

to 

Q, Q 



m 


300 

600 


300 

800 

10 

- 

125 

250 

- 


350 

Transition Time: 

Q, Q 

t THL, 

'TLH 


5 

- 

75 

125 

- 

75 

150 

ns 

10 

- 

45 

75 

- 

45 


Osc. Out 


5 

- 



- 



10 

- 

45 


- 



* 

Minimum Input Pulse 
Duration (any input) 



5 

- 



- 


1300 

ns 

10 

- 

200 

400 

- 

200 

600 

+T rigger, R etrigger,— T rigger 

Rise & Fall Time 

— 


5 

- 

- 

15 

- 

- 

15 

MS 

10 

- 

- 

5 

- 

- 

5 

Average Input 

Capacitance 

C| 



- 

n 

- 

- 

B 

- 

pF 


* Input pulse widths below the minimum specified may cause malfunction of the unit. See Application Note ICAN-6230. 


I. Astable Mode Design Information 

A. Unit-to-Unit Transfer-Voltage Variations 

The following analysis presents worst-case variations 
from unit-to-unit as a function of transfer-voltage 
(Vtr) shift (33%-67% Vdd) f° r free-running (as- 
table) operation. 


TERMINAL 13. 


TERMINAL 10 


Ta/2 I U/2 


Fig. 9 — Astable mode waveforms. 


M 


— RC In 


VTR 

v dd + v T r 


t2 = — RC In 


V DD- V TR 
2V DD - V TR 


tA = 2 (tj + t2> 

(Vjr) (V DD - V TR ) 

= -2 RC In— 

(Vdd + v tr) (2Vqd - v tr) 


Typ: Vt R = 0.5Vdd 

Min; Vy R = 0.33 Vdd 
M ax; Vj R = 0.67 Vdd 


tA = 4.40 RC 
t A = 4.62 RC 
t A = 4.62 RC 


thus if |t A = 4.40 RC | is used, the maximum variation will be 
(+5.0%, -0.0%). 


239 
























































CD4047AD, CD4047AE, CD4047AK 


File No. 623 


B. Variations Due to Vqd and Temperature Changes 
In addition to variations from unit*to*unit, the astable 
period may vary as a function of frequency with re- 
spect to Vqd an d temperature. Typical variations are 
presented in graphical form in Figs. 10 to 20 with 10 V 
as reference for voltage variation curves and 25°C as 
reference for temperature variation curves. 


SUPPLY VOLTAGE (V D o> — V 


92CS-2I442 



Fig. 11 — Typical Q-and-Q-period accuracy vs. supply voltage 
(medium frequency). 



+ 20 

mi 

:::C 

m 

1 

Hi: 

Hi: 

AMBIENT 

ASTABLE 

TEJ 

M0 

rfPERATURE (T A )=25°C 
)E 

Z 

bJ 




ii 

m 

Si 



iis 

1 

i 

ffH-H 


f 



| 

cr 




m 

m 

ii^ 

Hi: 

nil 

j 

i 

H 

(T 

ill 

rrrrrr r t it 


i 

1 



Hi: 

m 

m 

P 

Si 

:r4 

Tiff 

iM 


i 

: 

f 

<Hr 

c 

PF 

R 

Kfl 

o 

z 



p 

m 

m 

p 


I 

n 


| 

: A 

500 

>25 

10 

00 

47 

o 


Hi: 

tfj- 

nn 



% 


u 


i 

| C 

00 

0 

D 

22 

o : 
o 



hi? 

fjri 

:::: 

HH 





i 

Si: 




:p 


> 

s 


m 

St 

Tur 

iiS 

in* 

it 

p 

is 

n 



1 




I 

If 

| 

tr 

Z> 

O 


Sr 


"HJ 

m 

IKf! 

Ml 


i 

IS 

SS 


* 




1: 


I 

< 

Q 


H 

M 

[His 

nm 

n 

Ii 

mp 

m 

||||s! 

sH:si 

i 

is:?:: 

52* 

■s: 

I 

j|f 

| 

E 

s 

m 


1 

1 

ii 

::::: 

■ 

sssss 

111 

ii! 

ii 

55555 

i 

1 

ill 

1 

I 


jlj 

i 

::: 

s 

! A 

j 


05 10 15 


SUPPLY VOLTAGE (V DD ) — V 


Fig. 10 — Typical Q-and-Q-period accuracy vs. supply voltage 
( high frequency). 



SUPPLY VOLTAGE (V DD ) — V 


92CS-2I443 


Fig. 12 — Typical Q-and-Q-period accuracy vs. supply voltage 
(low frequency). 



SUPPLY VOLTAGE (V 0D ) — V 



Fig. 13 — Typical Q-and-Q-period accuracy vs. supply voltage 
(very low frequency). 


Fig. 14 — Typical Q-and-Q-period accuracy vs. frequency for 
Vqd variation of ± 10% from value indicated. 


240 





AMBIENT TEMPERATURE (T A ) — *C 


AMBIENT TEMPERATURE (Ta)—*C 


Fig. 19 — Typical oscillator-period accuracy vs. temperature 
(medium frequency). 


Fig.20 — Typical oscillator-period accuracy vs. temperature 
(high frequency). 





CD4047AD, CD4047AE, CD4047AK . 


File No. 623 


II. Monostable Mode Design Information 

The following analysis presents worst-case variations from 
unit-to-unit as a function of transfer-voltage (Vjr) shift 
(33% — 67% Vqd) for one-shot (monostable) operation. 


TERMINAL 8 


JL 


JL 


TERMINAL 13 Fritz I 1 trl t 2 

TERMINAL 10 _l I I I 

92CS- 20028 

Fig.21 — Monostable waveforms. 


VTR 

2V DD 


t M = (t-|* + t 2 ) 
tM = ~RC In 


(Vjr) (Vpp - VTR> 
(2VdD “ V TR) (2V D d> 


where t(y| = Monostable mode pulse width. Values for t|\/| are as 
follows: 


Typ; Vjr = 0.5 Vqd 
Min: Vjr = 0.33 V DD 
Max. Vjr = 0.67 V DD 
Thus if |t|yi = 2.48 RC | is used, the maximum variation will be 
(+9.3%, -0.0%). 


t M = 2.48 RC 
tM = 2.71 RC 
tM = 2.48 RC 


Note: 

In the astable mode, the first positive half cycle has a 
duration of Tm; succeeding durations are tA/2. 


In addition to variations from unit to unit, the monostable 
pulse width may vary as a function of frequency with 
respect to Vqd and temperature. These variations are 
presented in graphical form in Figs.22 to 27 with 10 V 
as reference for voltage variation curves and 25°C as refer- 
ence for temperature variation curves. 




SUPPLY VOLTAGE (V 0D ) — V 


SUPPLY VOLTAGE (V DD ) — V 


Fig.22 — Typical Q-and-Q-pulse-width accuracy vs. supply voltage 
<t M = 15, 60, 120 ns). 


Fig.23 — Typical Q-and-Q-pulse-width accuracy vs. supply voltage 
(t M = 0.5, 1, 10 ms). 



SUPPLY VOLTAGE (V DD )- 


9ZCS-2I430 


Fig.24 — Typical Q-and-Q-pulse-width accuracy vs. supply voltage 
(t M > 100 ms). 


AMBIEN 

MONOS 

T TEMP 
rABLE M 

ERATURE 

ODE 

(T A )= 2 

5 8 C 


















I 






a 


SUPF 

>LY VOLT/1 

1 5 V + 1 

IGE (V D i))‘ 
0 % | 

'15 VtlO% 


PI 


Pt' 


sag 


mrnmrn 

ihin 

_| — |_LL 


i in 


i i ii 


0 AND 0 -PULSE WIDTH— SECONDS 


Fig.25 — Typical Q-and-Q-pulse-width accuracy vs Q and ZI pulse 
width for a variation of ± 10% from value indicated. 


242 





File No. 623 


CD4047AD, CD4047AE, CD4047AK 



AMBIENT TEMPERATURE (T A )— °C 92CS-2I453 AMBIENT TEMPERATURE (T A ) — *C 92CS-2I454 

Fig. 26 - Typical Q-and-Q-pulse-width accuracy vs. temperature Fig.27 - Typical Q-and-Q-pulse-width accuracy range vs. temperature. 

( high frequency). 


+ TRIGGER 
RETRIGGER 
TERMINALS 8,12 


OSC OUTPUT 
TERMINAL I 3 


Q OUTPUT 
TERMINAL 10 



III. Retrigger Mode Operation 

The CD4047A can be used in the retrigger mode to ex- 
tend the output-pulse duration, or to compare the fre- 
quency of an input signal with that of the internal 
oscillator. In the retrigger mode the input pulse is applied 
to terminals 8 and 12, and the output is taken from 
terminal 10 or 11. As shown in Fig.28, normal mono- 
stable action is obtained when one retrigger pulse fs 
applied. Extended pulse duration is obtained when 
more than one pulse is applied. For two input pulses, 
tRE = t-j' + t-| + 2t2- For more than two pulses, 
tRE (Q OUTPUT) terminates at some variable time tp 
after the termination of the last retrigger pulse, tp is 
variable because tRE (Q OUTPUT) terminates after the 
second positive edge of the oscillator output appears at 
flip-flop 4 (see Fig.2). 

IV. External Counter Option 

Time tM can be extended by any amount with the use of 
external counting circuitry. Advantages include digi- 
tally controlled pulse duration, small timing capacitors 
for long time periods, and extremely fast recovery time. 
A typical implementation is shown in Fig. 29. The pulse 



92CS-20030RI 

Fig.29 — Implementation of external counter option. 


duration at the output is 

text = (N — 1) (tA) + (tM + tA/2) 
where t ex t = P ulse duration of the circuitry, and N is the 
number of counts used. 

V. Timing-Component Limitations 

The capacitor used in the circuit should be non-polarized 
and have low leakage (i. e. the parallel resistance of the 
capacitor should be an order of magnitude greater than 
the external resistor used). There is no upper or lower 
limit for either R or C value to maintain oscillation. 

However, in consideration of accuracy, C must be much 
larger than the inherent stray capacitance in the system 
(unless this capacitance can be measured and taken into 
account). R must be much larger than the COS/MOS 
"ON" resistance in series with it, which typically is 
hundreds of ohms. In addition, with very large values 
of R, some short-term instability with respect to time 
may be noted. 

The recommended values for these components to main- 
tain agreement with previously calculated formulas with- 
out trimming should be: 

C > 100 pF, up to any practical value, for astable 

modes; 

C > 1000 pF, up to any practical value for mono- 
stable modes. 

10 Kf2< R < 1 Mft, 


243 




POWER DISSIPATION (P D 


File No. 623 


CD4047AD, CD4047AE, CD4047AK 


VI. Power Consumption 

In the standby mode (Monostable or Astable), power 
dissipation will be a function of leakage current in the 
circuit, as shown in the static electrical characteristics. 
For dynamic operation, the power needed to charge the 
external timing capacitor C is given by the following 
formulae: 

Astable Mode: P = 2CV2f. (Output at terminal No. 
13) 

P = 4CV2f. (Output at terminal Nos. 
10 and 11) 

Monostable Mode: _ (2.9CV 2 ) (Duty Cycle) 

T 

(Output at terminal 
Nos. 10 and 11) 


The circuit is designed so that most of the total power is 
consumed in the external components. In practice, the 
lower the values of frequency and voltage used, the closer 
the actual power dissipation will be to the calculated 
value. 

Because the power dissipation does not depend on R, a 
design for minimum power dissipation would be a small 
value of C. The value of R would depend on the desired 
period (within the limitations discussed above). See 
Figs. 30—32 for typical power consumption in astable 
mode. 



Fig.30 — Power dissipation vs. output frequency (Vqq = 5 V). Fig.31 — Power dissipation vs. output frequency (Vqq = 10 V). 


TEST CIRCUITS 



Fig. 33 — Quiescent 

Fig.32 — Power dissipation vs. output frequency (Vqq = 15 V ). device current. Fig.34 — Noise immunity. 


244 








File No. 636 



Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4048AD CD4048AE CD4048AK 


BINARY CONTROL INPUTS 
FUNCTION CONTROL 



y2CS-22Z49 


COS/MOS Multi-Function 
Expandable 8-Input Gate 


Special Features: 

■ Medium-power TTL drive capability 
* Three-state output 

■ High-current source and sink capability 

9 mA (typ.) @ V DS = 0.5 V, V DD = 10 V 
o Many logic functions available in one package 


Applications: 

■ Selection of up to 8 logic functions 
n Digital control of logic 
» General-purpose gating logic 
— Decoding 
— Encoding 


RCA-CD4048A is an 8-input gate having four control inputs. 
Three binary control inputs — Ka, Kb, and Kc — provide the 
implementation of eight different logic functions. These func- 
tions are OR, NOR, AND, NAND, OR/AND, OR/NAND, 
AND/OR, and AND/NOR. 

A fourth control input — Kd — provides the user with 3-state 
outputs. When control input Kd is "high” the output is either a 
logic 1 or a logic 0 depending on the input states. When control 
input Kd is "low", the output is an open circuit. This feature 
enables the user to connect this device to a common bus line. 


In addition to the eight input lines, an EXPAND input is pro- 
vided that permits the user to increase the number of inputs to 
one CD4048A, (see Fig. 2). For example, two CD4048A's can 
be cascaded to provide a 16-input multifunction gate. When 
the EXPAND input is not used, it should be connected to V55. 

The CD4048A is supplied in a 16-lead dual-in-line ceramic 
package (CD4048AD), a 16-lead dual-in-line plastic package 
(CD4048AE), or a 16-lead flat pack (CD4048AK). 


NOR 




NAND 



AND 




Fig. 1— Basic logic configurations. 


9-74 


245 






CD4048AD, CD4048AE, CD4048AK File No. 636 

MAXIMUM RATINGS, Absolute-Maxim um Values: 

Storage-Temperature Range —65 to +150 °C 

Operating-Temperature Range: 

Ceramic Package Types —55 to +125 °C 

Plastic Package Types —40 to +85 °C 

DC Supply-Voltage Range (V DD — Vgg) —0.5 to +15 V 

Device Dissipation (Per Pkg.) 200 mW 

All Inputs V ss < V, < V DD 

Recommended 

DC Supply Voltage (V DD — Vgg) 3 to 15 V 

Recommended 

Input Voltage Swing Vpp to ^SS 

Lead Temperature (During Soldering): 

At distance 1/16 ± 1/32 in. (1 .59 ± 0.79 mm) 

from case for 10 s max 265 °C 



FUNCTION TRUTH TABLE 



TG 



Tz 

K b 


TG 


V‘ 


Kb 


OUTPUT 

FUNCTION 

BOOLEAN EXPRESSION 

Kal 

«<b 

*c 

UNUSED 

INPUT* 

NOR 

J= A+B+C+D+E+ F+G+H 

0 

0 

0 

V SS 

OR 

J=A+B+C+D+E+F+G+H 

, 0 

0 

1 

V SS 

OR/AND 

J=(A+B+C+D)*(E+F+G+H) 

0 

1 

0 

Vss 

OR/NAND 

J=|A+B+C+D)*(E+F+G+H) 

0 

1 

1 

Vss 

AND 

J=ABCDEFGH 

1 

0 

0 

V DD 

NAND 

J=ABCDEFGH 

1 

0 

1 

V DD 

AND/NOR 

J=ABCD+EFGH 

1 

1 

0 

V DD 

AND/OR 

J=ABCD+EFGH 

1 

1 

1 

V DD 

K(j= 1 Normal Inverter Action 

K d =0 High Impedance Output 


EXPAND lnput=0 



K c 1 3 CONFIGURATIONS 

Kd j SAME AS FOR "Kg INPUT 


el-*. 


•See Figs. 1 and 3. 


Transmission Gate Definition 
TG = Transmission Gate 
Input to Output is: 

a) A bidirectional low impedance when control input 
1 is "low" and control input 2 is "high" 

b) An open circuit when control input 1 is "high" 
and control input 2 is "low" 


IN 

T (1 

OUT 


1 U 



92CM-22251 R1 


Fig. 2— Logic diagram and truth table. 


246 












File No. 636 CD4048AD, CD4048AE, CD4048AK 


STATIC ELECTRICAL CHARACTERISTICS (AM inputs Vss<V,<V DD ) 

(Recommended DC Supply Voltage (Vqq — Vgg) 3 to 15 V) 


STATIC ELECTRICAL CHARACTERISTICS (All inputs Vss<V,<V DD ) 

(Recommended DC Supply Voltage (Vqq — Vgg) 3 to 15 V) 






LIMITS 


CHARAC- 

TERISTIC 

CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 



CD4048AD 

CD4048AK 




UNITS 

CURVES 

& TEST 

CIRCUITS 

Fig. No. 





— 55°C 

25° C 

125°C 





jjfll 




BIB 






Quiescent Device 

l L 


5 

- 

- 

1 

- 


1 

- 

- 

E9 


14 

Current 



10 

_ 

_ 

B 

_ 

BS 

B 

- 

- 



Quiescent Device 



5 

_ 

- 

5 

- 


a 

- 

- 

SOI 



Dissipation/Package 

P D 


10 

- 

- 

06 

- 

BO 

m 

- 

- 



Output Voltage: 

V OL 


5 

- 

- 


- 

0 


- 

- 




Low-Level 


10 

- 

- 

§9 


B 


- 

- 




High-Level 

v oh 


5 


- 

- 


5 

- 


- 

- 




10 


- 

- 

RUB 

wm 

- 


- 

- 



Noise Immunity 


wm 

5 

m 

- 


IB 

001 

- 

1.4 

- 

- 


,13 

(All Inputs) 

V NL 

9 

mm 

3 

- 

- 

B 


- 


- 

- 


For definition. 


0.8 


1.4 

- 

- 



- 

m 

- 

- 


13 

see Appendix 

V NH 

1 

10 


- 

- 



- 

m 

B 

- 


Output Drive Current: 
N-Channel 

\ d n 


H 

■ 

■ 

E 




n 

■ 

■ 


mm 

(Sink) 

BIBB 


m 



BUI 



m 

■ 



P-Channel 


4.6 

5 

El 

- 

- 

H 

-3.2 

- 

-i.i 

_ 

- 


7,8 

(Source) 


EM 

10 


- 

- 

m 

-9 

- 

BD 

_ 

- 



Applications of Expand Input 



J * (A + B + C + D)' (E4F + G+H)* (XI+X2+X3+X4) 
Fig. 3(a)— 12-input OR/AND gate. 




Fig. 3(c)— Actual-circuit logic configurations. 


OR FUNCTION 



J=Aj +B| +C| +D| +E| +F| +G| +H| +A2+B2+C2+D2+E2^”^2'*’®2'^2 
Fig. 3(b)— 16-input NOR gate. 


IMPLEMENTATION OF EXPAND INPUT FOR 9 OR MORE INPUTS 


OUTPUT 

FUNCTION 

FUNCTION 
NEEDED AT 
EXPAND INPUT 

OUTPUT BOOLEAN 
EXPRESSION 

NOR 

OR 

J=(A+B+C+D+E+F+G+H)+(EXP) 

OR 

OR 

J=(A+B+C+D+E+F+G+H)+(EXP) 

AND 

NAND 

J=(ABCDEFGH)*(EXP) 

NAND 

NAND 

J=(ABCDEFGH)-(EXPy 

OR/AND 

NOR 

J=(A+B+C+D)-(E+F+G+H)-(EXP) 

OR/NAND 

NOR 

J=(A+B+C+D)-(E+F+G+H)-TEXPT 

AND/NOR 

AND 

J=(ABCD)+(EFGH)+(EXP) 

AND/OR 

AND 

J=(ABCD)+(EFGH)+(EXP) 


Note: (EXP) designates the EXPAND function (i.e., X^X 2 + . . . .X N ). 


Fig. 3— Expansion logic and truth table. 


247 












CD4048AD, CD4048AE, CD4048AK 


File No. 636 


STATIC ELECTRICAL CHARACTERISTICS (All inputs 

(Recommended DC Supply Voltage (Vqjq - Vgg). 


v ss < v, <V DD ) 

3 to 15 V) 


CHARACTERISTIC SYMBOL 


Quiescent Device 
Current 

Quiescent Device 

Dissipation/Package 


Output Voltage: 
Low-Level 


Noise Immunity 
(All Inputs) 

For definition 
see Appendix 


TEST 

CONDITIONS 


Output Drive Current: 
N-Channel 




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HI 


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Hi 

Hi 

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Hi 

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HU 

HI 

BHUHBHMilll 

.HH 

HE 

EEOHIHIEEOHilHEH 

Hi 


BBBKIEBIHiH^ 



CHARAC- 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 
Fig. No. 



AMBIENT TEMPERATURE (T A )=25 

°c 





'A 







C L * 15 pF 

Cl= 50 pF 





INPUT FREQUENCY (fj) — Hz 

Fig. 4— Typical power dissipation as a 
function of input frequency. 


AMBIENT TEMPERATE 

TYPICAL TEMP COEFF 
II 1 1 1 1 II 1 1 1 It II 

- MAXIMUM AVERAGE 

I PKG. DISSIPATION (2 

f 1-H-l tft+H 

- \ -GAT 

ICIENT AT ALL VALUES OF Vgs=~0.3 %/°C- 
rrn i i 

00 mW) 

=>T0- SOURCE VOLTAGE (V gs )*I5V 


- -10 V 

bTvjbbbbbbb^b 

B'l'iBBBBBBBBBik 


I/BBBBBBBBBBB 

''■flBflErBBBBB 

jbbbbmSbbbb 

#r:===2S!EBBBB 

^BBBBBBBBBBBB 



DRAIN -TO-SOURCE VOLTAGE (V DS )-V 


Fig. 5— Typical n-channel drain characteristics. 




















File No. 636 


CD4048AD, CD4048AE, CD4048AK 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C and C L = 15 pF and 50 pF 
Typical Temperature Coefficient for all values of Vqq = 0.3%/°C 

C L = 15 pF 




* Max. Limits represent worst-case limits for worst-case modes of operation shown in Figs. 15, 16, and 17 


DYNAMIC ELECTRICAL CHARACTERISTICS, Driving TTL at T A = 25°C, V DD - V ss = 5 V, C L = 15 pF 
CD4048AD, CD4048AK 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

Driving One TTL Load 

LIMITS 




TYP. 

MAX. 

Propagation Delay Time: 

High-to-Low Level 

Vhl 

Series 54L, 74L 

- 

775 

- 

5 

12 

Series 54, 74 

- 

775 

- 

Low-to-High Level 

tpLH 

Series 54L, 74L 

- 

710 

- 

D 

Series 54, 74 

- 

600 

~ 


CD4048AE 



\9 





































LOAD CAPACITANCE (Cl)'PF 


Fig. 8— Minimum p-channel drain 
characteristics. 


Fig. 9— Typical propagation delay time as a 
function of load capacitance. 


AMBIENT TEMPERATURE (Ta)*25 # C 

TYPICAL TEMP COEFFICIENT AT ALL VALUES OF VdD*0.3 %/°C 



AMBIENT TEMPERATURE (T A )*25°C 1 

TYPICAL TEMP COEFFICIENT AT ALL VALUES OF VqD=0.3 %/ # C 

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aaaa 

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1 


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anaa 

am 

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LOAD CAPACITANCE (Cl) — pF 


LOAD CAPACITANCE (Cl) — pF 


Fig. 10 — Typical fow-to-high level transition 

time as a function of load capacitance. 


Fig. 11- Typical high-to-low level transition 

time as a function of load capacitance. 







File No. 636 . 


CD4048AD, CD4048AE, CD4048AK 


TEST CIRCUITS 


V DD 





Fig. 13 — Noise immunity, (can also be measured using one 
input; other inputs are tied to Vqq) 


92CS -22262 


Fig. 12— Test circuit and waveforms for propagation delay time 
(CD4048A driving 1 TTL load). 



H G F E K b 


0 0 0 0 0 


0 0 0 0 0 


92CS-22259 


Fig. 14— Quiescent device current. 

TEST CIRCUITS - DYNAMIC MEASUREMENTS 

Vqd 





4 -507. 


92CS-22263 


Fig. IS- t pLH - NAND. 


V D D 



Vss 


INPUT / —50% 


OUTPUT -f- \ - \ 50% 

*PHL " 

92CS-22264 


Vdd 



V SS 


OUTPUT 

'T^L 


—f — 

^ vV-Vi : 


90% 
- - 10 % 


92CS -22265 


Fig. 16— tpm_ — AND. 


Fig. 17- t JHL , t TLH - AND/NOR. 


251 








Solid State 
Division 


File No. 599 

Digital Integrated Circuits 

Monolithic Silicon 

CD4049A, CD4050A 


COS/MOS Hex Buffer/Converters 


A G ‘* 

A — - G*A 

B H=§ 

B H.B 

c i-e 

c i-e 

0 J.D 

0 J.D 

E K.r 

E K ' E 

F !!{>-? L.P 

F^.F 

vcc — ! — 
v ss - § - 

NC « 13 

Vcc — 

Vss- 2 — 

NC =13 

CD4049A 

9ZCS-20H6 

CD4050A 


CD4049AD \ 

CD4049AE l INVERTING 
CD4049AF ( TYPE 
CD4049AK ' 


Features: 

■ Direct Drive to 2 TTL Loads at 5 V, 
VCC = 5 V, Vol < 0.4 V, 

IpN > 3 mA 

h High Source and Sink Current 
Capability 

■ General COS/MOS Characteristics 


CD4050AD } 

CD4050AE ( NON-INVERTING 
CD4050AF ( TYPE 

CD4050AK / 


Applications: 

■ COS/MOS to DTL/TTL Hex Converter 

■ COS/MOS Current "Sink" or "Source" 
Driver 

■ COS/MOS High-to-Low Logic-Level 
Converter 


.The CD4049A and CD4050A are inverting and non-inverting 
hex buffers, respectively, and feature logic-level conversion 
using only one supply voltage (Vqq). The input-signal high 
level (Vj|_|) can exceed the Vqq supply voltage when these 
devices are used for logic-level conversions. These devices are 
intended for use as COS/MOS to DTL/TTL converters and 
can drive directly two DTL/TTL loads. (Vqq = 5 V, 
v OL < °- 4 v ' and ! D n > 3 mA -> 

Table 1 shows the range of voltage-supply levels that can be 
utilized for such logic level conversions. Conversion to logic- 
levels greater than +6 V is permitted provided that Vqq 
<V j|-|. At 15 V, the maximum allowable load capacitance 
is 5000 pF. 

The CD4049A and CD4050A are designated as replacements 
for CD4009A and CD4010A, respectively. Because the 
CD4049A and CD4050A require only one power supply, they 
are preferred over the CD4009A and CD4010A and should be 
us6d in place of the CD4009A and CD4010A in all inverter, 
current driver, or logic-level conversion applications. In these 
applications the CD4049A and CD4050A are pin compatible 
with the CD4009A and CD4010A respectively, and can be 
substituted for these devices in existing as well as in new 
designs. Terminal No. 16 is not connected internally on the 
CD4049A or CD4050A, therefore, connection to this termi- 
nal is of no consequence to circuit operation. 

The CD4049A and CD4050A are supplied in 16-lead dual in- 
line welded-seal ceramic packages (CD4049ADand CD4050AD), 
16-lead dual-in-line plastic packages (CD4049AE and 
CD4050AE), 16-lead dual-in-line frit-seal ceramic packages 
(CD4049AF and CD4050AF) and 16-lead flat packages 
(CD4049AK and CD4050AK). 


TABLE I 


FUNCTION 

COS/MOS 
VOLTAGE 
RANGE (INPUT) 

DTL/TTL 
VOLTAGE 
RANGE (OUTPUT) 

POWER SUPPLY 
VOLTAGE 
RANGE (Vcc) 

HEX LEVEL SHIFTER 

3-1 5 V 

3-6 V 

3-6 V 

HEX INVERTER 

HEX BUFFER 

3-1 5 V 

3-15 V 

3-15 V 


Vcc 



92CS-20II7 


Fig. 1—a) Schematic diagram of CD4049A. 1 of 6 identical units; 
b) Schematic diagram of CD4050A, 1 of 6 identical units. 


252 


9-74 






File No. 599 


CD4049A, CD4050A 


MAXIMUM RATINGS, Absolute-Maximum Values: 


Storaye-Temperature Range —65 to +150 °C 

Operating-Temperature Range: 

Ceramic Package Types —55 to +125 °C 

Plastic Package Types —40 to +85 °C 

DC Supply Voltage Range (Vqq—V 5 s) . —0.5 to +15 V 

Dissipation: 

Per Package 200 mW 

Per Buffer 100 mW 

All Inputs V ss < V, < 15 V 


Recommended Minimum DC Supply Voltage 

* v cc _v ss) 3 V 

Lead Temperature (During soldering): 

At distance 1 /1 6 ± 1 /32 inch (1 .59 ±0.79 mm) 

from case for 10 seconds max. 265 °C 

STATIC ELECTRICAL CHARACTERISTICS (All Inputs V S S < V| < 15 V) 

(Recommended DC Supply Voltage (Vcc — V SS) ■ 3 to 15 V) 


CHARACTERISTIC 

SYMBOL 


LIMITS 

UNITS 

TEST 

CONDITIONS 

CD4049AD, CD4049AK, CD4049AF 
CD4050AD, CD4050AK, CD4050AF , 


vo 

Volts 

Vcc 

Volts 

-55°C 

25°C 


25°C 1 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. ( 

Quiescent Device 
Current 

'L 

VlH= 

v cc 


5 

- 

- 

0.3 

_ 

0.01 

0.3 

_ 

_ 

20 

pA 

10 

- 

- 

0.5 

- 

0.01 

0.5 

- 

- 

30 

Quiescent Device 
Dissipation Package 

P D 

V|H= 

Vcc 


5 

_ 

_ 

1.5 

_ 

0.05 

1.5 

_ 

_ 

100 

juW 

10 

- 

- 

5 

- 

0.1 

5 

- 

- 

300 

Output Voltage 
Low-Level 

VOL 



5 

- 

- 

0.01 

- 

0 

0.01 

- 

- 

0.05 

V 

10 

- 

- 

0.01 

- 

0 

0.01 

- 

- 

0.05 

High-Level 

< 

o 

X 



5 

4.99 

_ 

- 

4.99 

5 

_ 

4.95 

_ 

_ 

V 

10 

9.99 

- 

- 

9.99 

10 

_ 

9.95 

_ 

_ 

Noise Immunity (All 
Inputs) 

CD4049A 

V NL 

V0H= 

3.6 V 

5 

1 



1 

2.25 


0.9 


' 

V 

V0H = 

7.2 V 

10 

2 



2 

4.5 


1.9 



CD4050A 

V0L= 

0.95 V 

5 

1.5 

■’ _ 

. 

1.5 

2.25 

_ 

1.4 

_ 

_ 

v 0L = 

2.9 V 

10 

3 

_ 

_ 

3 

4.5 

_ 

2.9 

_ 

_ 

CD4050A 

Vnh 

V0H = 

7.2 V 

10 

2.9 



3 

4.5 


3 



V0H = 

3.6 V 

5 

1.4 



1.5 

2.25 


1.5 



CD4049A 

For Definition, 

See Appendix 

V0L = 

2.9 V 

10 

2.9 



3 

4.5 


3 



V0L = 

0.95 V 

5 

1.4 



1.5 

2.25 


1.5 



Output Drive Current 

N-CHANNEL 

i d n 


0.4 

4.5 

3.3 

- 

- 

2.6 

5.2 

- 

1.8 

- 

- 

mA 

0.4 

5 

3.75 

- 

_ 

3.0 

6 

- 

2.1 

_ 

- 

0.5 

10 

10 

- 

- 

8 

16 

- 

5.6 

- 

- 

P-CHANNEL 

'd p 


4.5 

5 

-0.62 

- 

- 

-0.5 

-1 

- 

-0.35 

- 

- 

2.5 

5 

-1.85 

- 

- 

-1.25 

-2.5 

- 

-0.9 

- 

- 

.9.5 

10 

-1.85 

- 

- 

-1.25 

-2.5 

- 

-0.9 

- 

- 

Input Current 

•l 

VlH=V C c 



- 

- 

- 

- 

10 

- 

- 

- 

- 

pA 


253 




CD4049A, CD4050A File No. 599 


STATIC ELECTRICAL CHARACTERISTICS (All Inputs V S S<V|<15V) 

(Recommended DC Supply Voltage (Vcc “ Vss) 3 to 15 V) 






— 

LIMITS 

■ 

CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 

CD4049AE, CD4050AE 

UNITS 




Eii 


-40°C 


25°C 

85°C 





Wnnl 


U0 

PH! 

^23 

ns 

PHI 

^3 

1219 

PH 

mini 


Quiescent Device 




5 

- 

99! 

n 

- 

Mi Tfll 

mw 

- 

- 

wcm 


Current 



BH 

ESI 

- 

- 

5 

- 


5 

- 

- 

9E9 

Quiescent Device 




5 



mm 

_ 

ilH 

H3 

_ 

_ 

E 


Dissipation Package 



K9 

- 

99 

MUM 

- 

WEB 

mm 

- 

- 

EZH9 

Output Voltage 
Low-Level 

< 

o 

r— 



5 

_ 

- 

0.01 

_ 

0 

0.01 

_ 

- 

0.05 

V 




10 

- 

- 

0.01 

- 

0 

0.01 

- 

- 

0.05 


High-Level 

V 0H 



5 

4.99 


_ 

4.99 

5 

_ 

4.95 

- 

_ 

V 



10 

9.99 

- 

- 

9.99 

10 

- 

9.95 

- 

- 


Noise Immunity (All 
Inputs) 


voh= 

3.6 V 

5 

1 



1 

2.25 


0.9 




CD4049A 


V 0H = 

7.2 V 

10 

2 



2 

4.5 


1.9 




CD4050A 

V NL 

V0L= 

0.95 V 

5 

1.5 

_ 

_ 

1.5 

2.25 

_ 

1.4 


_ 



V0L= 

2.9 V 

10 

3 

_ 

_ 

3 

4.5 

_ 

2.9 

_ 

_ 

\/ 



V0H = 

7.2 V 

10 

2.9 



3 

4.5 


3 




CD4050A 


VOH = 

3.6 V 

5 

1.4 



1.5 

2.25 


1.5 




CD4049A 

Vnh 

VOL = 

2.9 V 

10 

2.9 



3 

4.5 


3 





V0L= 

0.95 V 

5 

1.4 



1.5 

2.25 


1.5 




Output Drive Current 



0.4 

4.5 

3.1 

- 

- 

2.6 

5.2 

- 

2.1 

- 

- 


N-CHANNEL 

i d n 


0.4 

5 

3.6 

- 

- 

3 

6.0 


2.5 

_ 

- 




0.5 

10 

9.6 

- 

- 

8 

16 

- 

6.6 

- 

- 





4.5 

5 

-0.6 

- 

- 

-0.5 

-1 

- 

-0.4 

- 

- 

mA 

P-CHANNEL 

IqP 


2.5 

5 

-1.5 

- 

- 

-1.25 

-2.5 

- 

-1 

- 

- 




9.5 

10 

-1.5 

- 

- 

-1.25 

-2.5 

- 

-1 

- 

- 


Input Current 

>1 

V|H=Vcc 



- 

- 

- 

- 

10 

- 

- 

- 

- 

PA 



. 92CS-20479 

Fig.2 — Min. & max. voltage transfer characteristics for CD4049A. 



92CS-20480 

Fig.3 — Min. & max. voltage transfer characteristics for CD4050A. 


254 













File No. 599 


CD4049A, CD4050A 


DYNAMIC ELECTRICAL CHARACTERISTICS at Ta=25°C, Cl= 15 pF, and input rise and fall time$=20 ns 
Typical Temperature Coefficient for all values of Vcc = 0.3%/oc . (See Appendix for Waveforms) 






LIMITS 


CHARAC- 



TEST 

CD4049AD, AE 

CD4050AD, AE 


TERISTIC 

CHARACTERISTIC 

SYMBOL 

CONDITIONS 

CD4049AF, AK 

CD4050AF, AK 

UNITS 

CURVES 




V CC 








CIRCUITS 




(Volts) 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 


Fig. No. 

Propagation Delay Time: 



5 

- 

15 

55 

_ 

55 

110 



High-to-Low Level 

*PHL 


10 

- 

10 

30 

- 

25 

55 

ns 

10,11 













Low-to-High Level 

X PLH 

V IH= V CC 

■1 

H 

H9 

M 

B 

11 









Bl 


B 




12,13 





■ 

■ 

■ 

■ 

■ 

■ 



Transition Time: 


V IH =V CC 

5 

■ 

bsi 

wm 

B 



Bl 


High-to-Low Level 



10 

m 


H 

1 



D 

14 

Low-to-High Level 

*TLH 

I 

ii 

< 

R 

5 

■ 

1 


B 



n 

15 




10 


30 

60 

- 

30 

60 



Input Capacitance 


CD4049A 

■ b 

■ 

15 

B 

B 


_ 

bb 


(Any Input) 

C| 

CD4050A 

1 

H 

5 

H 

■ 


- 

pi- 






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INPUT VOLTAGE (Vj)— V 

92CS-2048I 


Fig.4 — Min. & max. voltage transfer characteristics for CD4049A. 


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INPUT VOLTAGE (Vj)— V 

92CS-20482 


Fig. 5 — Min. & max. voltage transfer characteristics for CD4050A. 


255 









CD4049A, CD4050A 


File No. 599 


fffigfflSUPPLY VOLTAGE (V CC )«IOV^ 


^SUPPLY VOLTAGE (V CC )« 10 V p 


[f tilf i ll H25<,g: 

v cc = svftffl 


3 AMBIENT TEMPERATURE ( T A ) * - 55°C t 


PTOTOTO# ::; AMBIENT TEMPERATURE - 

: iti'n?! i?i ff " ; 1 (t a ) - 55Cc UHliull S 













Preliminary 



Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 
Preliminary CD4051AD, CD4051AE, CD4051AK 
Preliminary CD4052AD, CD4052AE, CD4052AK 
Preliminary CD4053AD, CD4053AE, CD4053AK 


Preliminary Data ' 


•_o, 

T 


.1 

PRELIM. 


CD405IA 

G_ 


_7 



SJ 


IN/OUT-[~§yf 

IN/OUT -T^l PRELIM| NARY 
CD4053A 

IN/OUT 


TR0l { t 1 


- ax OR oy OUT/IN 
-bx OR by OUT/ IN 
■ cx OR cy OUT/ IN 


COS/MOS Analog 
Multiplexers/Demultiplexers 

With Logic — Level Conversion 

CD4051A Single 8-Channel Multiplexer/Demultiplexer 
CD4052A Differential 4-Channel Multiplexer/Demultiplexer 
CD4053A Triple 2-Channel Multiplexer/Demultiplexer 

Applications: 

b Analog and digital multiplexing and demultiplexing 
a A/D and D/A conversion 
b Signal gating 


RCA COS/MOS Analog Multiplexers/Demultiplexers* Pre- 
liminary CD4051 A, CD4052A, and CD4053A are digitally 
controlled analog switches having low "ON" impedance and 
very low "OFF" leakage current. Control of analog signals up 
to 15 V p-p can be achieved by digital signal amplitudes of 3 to 
15 V. For example, if Vpp = +5 V, Vgg = 0 V, and V EE = 
—5 V, analog signals from —5 V to +5 V can be controlled by 
digital inputs of 0 to 5 V. The multiplexer circuits dissipate 
extremely low quiescent power over the full Vpp — Vgg and 
Vdd — V EE supply-voltage ranges, independent of the logic 
state of the control signals. When a logic "1" is present at the 
inhibit input terminal all channels are "OFF". 

CD4051A is a single 8-channel multiplexer having three 
binary control inputs. A, B, and C, and an inhibit input. The 
three binary signals select 1 of 8 channels to be turned "ON" 
and connect the input to the output. 

CD4052A is a differential 4-channel multiplexer having two 
binary control inputs, A and B, and an inhibit input. The two 
binary input signals select 1 of 4 pairs of channels to be turned 
on and connect the differential analog inputs to the differ- 
ential outputs. 

CD4053A is a triple 2-channel multiplexer having three 
separate digital control inputs. A, B, and C and an inhibit 
input. Each control input selects one of a pair of channels 
which are connected in a single-pole double-throw configuratioa 

These devices are supplied in a 16-lead dual-in-line ceramic 
package (CD4051AD, CD4052AD, and CD4053AD), a 16-lead 
dual-in-line plastic package (CD4051AE, CD4052AE, and 
CD4053AE), or a 16-lead flat pack (CD4051 AK, CD4052AK, 
and CD4053AK). 

* When the devices are used as demultiplexers, the “CHANNEL IN/ 
OUT" terminals are the outputs and the "COMMON OUT/IN” 
terminal(s) is (are) the input(s). 


Features: 

a Wide range of digital and analog signal levels: 

digital 3 to 15 V, analog to 15 V p-p 
b Low "ON" resistance: 8052 (typ.) over entire 15 V p-p 
signal-input range for Vpp — V EE = 15 V 
o High "OFF" resistance: input leakage ± 10 pA (typ.) @ 
V DD- V EE =10V 

b Logic-level conversion for digital addressing signals of 3 to 
15V (Vpp — Vgg = 3 V to 15 V) to switch analog 
signals to 15 V p-p (Vpp - V EE = 15 V) 
n Matched switch characteristics: ARqn = 5£2 (typ.) for 
V DD “ V EE = 15 v 

° Very low quiescent power dissipation under all digital- 
control input and supply conditions: 1 juW typ. @ 

V DD ~ V SS = V DD ” V EE = 10 v 
b Binary address decoding on chip 


TRUTH TABLE 


INPUT STATES 

"ON" CHANNELS ] 

INHIBIT 

c 

B 

A 

CD4051A 

CD4052A 

CD4053A 

0 

0 

0 

0 

0 

Ox, Oy 

cx, bx, ax 

0 

0 

0 

1 

1 

lx, 1 y 

cx, bx, ay 

0 

0 

1 

0 

2 

ro 

X 

10 

< 

cx, by, ax 

0 

0 

1 

1 

3 

3x, 3y 

cx, by, ay 

0 

1 

0 

0 

4 


cy, bx, ax 

0 

1 

0 

1 

5 


cy, bx, ay 

0 

1 

1 

0 

6 


cy.by, ax , 

0 

1 

1 

1 

7 


cy, by, ay 

1 

* 

* 

# 

NONE 

NONE 

NONE 


* = Don't care condition 


10-73 


259 






CD4051 A, CD4052A, CD4053A 

MAXIMUM RATINGS, Absolute Maximum Values 

Storage-Temperature Range — 65°C to +150°C 

Operating-Temperature Range 

Ceramic Packages — 55°C to +125°C 

Plastic Packages — 40°C to +85°C 

Dissipation Per Package 200 mW 

DC Supply Voltages 

v DD ” V SS ; V DD ~ V EE -0.5 to +15 V 

Digital Control Inputs . . .• Vgg <V| =^V DD 

Minimum Recommended Power Supply Voltages 

V DD “ V SS ; V DD “ V EE 3 V 

Lead Temperature (During soldering) 

At distance 1/16 ± 1/32 inch (1 .59 ± 0.79 mm) o 

from case for 10 seconds max 265 C 

Operating Precautions: 

1. R l ^ 100 $2 

2. Signal Input Current Capability < 25 mA 
OPERATING CONSIDERATIONS 

1. Handling 

All COS/MOSgate inputs have a resistor/diode gate protection 
network. All transmission gate inputs and all outputs have 
diode protection provided by inherent p-n junction diodes. 
These diode networks at input and output interfaces fully 
protect COS/MOS devices from gate-oxide failure (70 to 
100 volt limit) for static discharge or signal voltage up to 
1 to 2 kilovolts under most transient or low-current 
conditions. 

Although protection against electrostatic effects is provided 
by built-in circuitry, the following handling precautions 
should be taken: 

1 . Soldering-iron tips and test equipment should be grounded. 

2. Devices should not be inserted in non-conductive con- 
tainers such as conventional plastic snow or trays. 


Preliminary 

2. Operating 

Unused Inputs 

All unused input leads must be connected to either Vgg or 
V DD , whichever is appropriate for the logic circuit involved. 
A floating input on a high-current type, such as the 
CD4009A, CD4010A, not only can result in faulty logic 
operation, but can cause the maximum power dissipation of 
200 milliwatts to be exceeded and may result in damage to 
the device. Inputs to these types, which are mounted on 
printed-circuit boards that may temporarily become un- 
terminated, should have a pull-up resistor to Vgg or Vqq. 

A useful range of values for such resistors is from 0.2 
to 1 megohm. 

Input Signals 

Signals shall not be applied to the inputs while the device 
power supply is off unless the input current is limited to a 
steady state value of less than 10 milliamperes. 

Output Short Circuits 

Shorting of outputs to Vgg or Vpp can damage many of the 
higher -output-current COS/MOS types, such as the CD4007A, 
CD4009A, and CD4010A. In general, these types can all be 
safely shorted for supplies up to 5 volts, but will be damaged 
(depending on type) at higher power-supply voltages. For 
cases in which a short-circuit load, such as the base of a p-n-p 
or an n-p-n bipolar transistor, is directly driven, the device 
output characteristics given in the published data should be 
consulted to determine the requirements for a safe operation 
below 200 milliwatts. 


CHANNEL IN/OUT* 



Fig. 1 — Functional diagram preliminary CD4051A. 


* See operating precautions, above. 


260 





Preliminary 


CD4051A, CD4052A, CD4053A 


X CHANNELS IN/OUT* 

2 i 0^ 



* See operating precautions, P. 2. 


ELECTRICAL CHARACTERISTICS at T A = 25°C 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 











BMW 







1 

■H 






m 














jm 

1 


NOTE 1: All digital combinations on address inputs; all analog inputs 

v ee <v,<v dd 


261 














CD4051 A, CD4052A, CD4053A 


Preliminary 


ELECTRICAL CHARACTERISTICS at T A = 25°C 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 



CURVE 

& 

TEST 
CIRCUIT 
Fig. No. 

SIGNAL INPUTS (V js ) AND OUTP 

JTS (V os ) 





"ON" Resistance 

(Peak for Vss ^ V|s ^V DD ) 

r on 

R l = 10 kS2 

v ss = o 

(Any channel 
selected) 

V DD 

Vee 

Vjs 

80 

il 

5 

+7.5 V 

+ 15 V 

-7.5 V 

OR 

0 V 

- 

+5 V 

+ 10 V 

-5 V 

DR 

0 V 

- 

120 

+2.5 V 

+5 V 

-2.5 V 

DR 

0 V 

- 

270 

A "ON" Resistance 

Between Any 2 Channels 

^ON 

+7.5 V 

C 

+ 15 V 

-7.5 V 
)R 

0 V 

- 

5 

n 

- 

+5 V 

C 

+ 10 V 

-5 V 
)R 

0 V 

- 

10 

Sine Wave Response 
(Distortion) 


R l - 10 kS2 

Vss = o 

f,s 1 kHz 

+ 7.5 V 

+5 V 

+ 2.5 V 

-7.5 V 

-5 V 

-2.5 V 

5 V (p-p)* 

0.1 

0.2 

1 

% 


OFF Channel Leakage Current: 

Any Channel "OFF" 


v ss = o V 

+5 V 

(= V C ) 

- 5 V 


±0.01 

nA 

11 

All Channels "OFF" 

(Common OUT/IN) 

INHIBIT 

- +5 V 

v ss o v 

*5 V 

(= v c ) 

-5 V 

CD4051A 

CD4052A 

CD4053A 

±0.08 

±0.04 

±0.02 

12 

Frequency Response- 
Channel "ON" 

(Sine Wave Input) 


R|_ - 1 k<2 

V is 5 V (p-p) 

v S s o V 

v c V DD = +5 V, V EE = —5 V 

Vos 

20Los ,o— "~ 3dB 

40 

MHz 


Feedthrough 

Channel "OFF" 


Vqd ~ + 5V, V C = V EE = -5V 

Vos 

20L ° 9 .o— - 40dB 

1 

MHz 

Crosstalk Between any 2 

Channels 

(Frequency at - 40 dB) 


R L - 1 kS2 

V, s (A) - 5 V (p-p) 
V S s o V 

V C (A) = V DD = +5 V 

V C (B) = V EE = - 5 V 

V Q s 

20Lo!l ,0-^-- 40dB 

1 

MHz 


Capacitance. Input 

C IS 




5 



Output 
/Commont 
(OUT/IN / 

c os 


CD4051A 

30 


V DD ♦ 5 V 

V C = V EE “ - 5 v 

CD4052A 

18 

PF 

CD4053A 

10 





0.2 


Feedthrough 

C IOS 

v ss -ov 

Propagation Delay: 

Signal Input-to- 
Signal Output 

*PLH> 

l PHL 

Vc Vqq = + 10 V, V EE = 0 V, C L = 15 pF 

V, s =10 V*. Vss o V -= Inhibit 
t r , tf - 20 ns (input signal) 

10 

ns 


| CONTROL (Vc> INPUTS A. B. C. AND INHIBIT 



Noise Immunity 

(Any control input) 

V NL 

Vis = Vqq thru 1 
V EE = V SS 

kS 2 

V DD ~ v ss 10 V 

V DD "VSS = 5 V 

4.5 

2.25 


- 

V NH 

i,s -- io m a 

R l r 1 ki2 to V EE 

V DD - VSS - 10 V 

V DD - V SS = 5 V 

4.5 

2.25 

V 

Average Input Capacitance 

C| 

V DD = + 5 V V EE = —5 V 

Vss = 0 V Channel "OFF" 

5 

PF 

- 


❖ Square wave 

* Symmetrical about 0 volts. 


262 









Preliminary 


CD4051A, CD4052A, CD4053A 


ELECTRICAL CHARACTERISTICS at T A = 25°C 



• Time after inhibit is removed during which channel information is invalid 

♦ Square wave 


* Channel Overlap = Turn-on propagation delay, where channel overlap is 
defined as the duration after control signal change during which two 
channels may be on together. 



SIGNAL VOLTAGE (V ls ) — VOLTS 

92CS -22712 


Fig. 4(a) — Typical Channel "ON" resistance vs. signal voltage 
for preliminary CD4051A. 



SIGNAL VOLTAGE (V ls ) — VOLTS 

92CS-227I3 


Fig. 4(b) — Typical Channel "ON" resistance vs. signal voltage 
for preliminary CD4051A with supply voltage 
(Vdd ~ V EE) “ 5 V. 



SIGNAL VOLTAGE (V is ) — VOLTS 


92CS -22714 


Fig. 4(c) — Typical Channel "ON" resistance vs. signal voltage 
for preliminary CD4051A with supply voltage 
(V DD ~ V EE> = 10 v - 



-8 -6 -4 -2 0 2 4 § 8 

SIGNAL VOLTAGE (V Ls ) — VOLTS 

92CS-227I5 


Fig. 4(d) - Typical Channel "ON" resistance vs. signal voltage for 
preliminary CD4051A with supply voltage 
(V DD - V EE ) = IS V. 


263 










CD4051A, CD4052A, CD4053A 


Preliminary 



92CS -22716 


Fig. 5 — Channel “ON" resistance measurement circuit. 



92CS-227I7 

Fig. 6— Typical “ON" characteristics for 1 of 8 channels 
for preliminary CD4051A. 



92CS - 22718 


Fig. 7 - Typical dissipation (per package) vs. switching 
frequency for preliminary CD4051AD. 



92CS -22719 


Fig. 8 — Typical dissipation (per package) vs. switching 
frequency for preliminary CD4052AD. 



92CS- 22720 

Fig. 9 - Typical dissipation (per package) vs. switching 
frequency for preliminary CD4053AD. 


264 








Preliminary 


CD4051A, CD4052A, CD4053A 



(a) (b) (c) (d) 


The ADDRESS (digital-control inputs) and INHIBIT logic levels are:"0" = 

Vss and "1" = Vdq. The analog signal (through the TG) may swing from 
Ve£ to Vqq. 

Fig. 10 — Typical bias voltages. 


92CS-20088RI 


TEST CIRCUITS 



92CS - 22722 




Fig. 11 — OFF channel leakage current . . . any channel off. 





Fig. 12— OFF channel leakage current ... all channels off. 


92CS-22723 













CD4051A, CD4052A, CD4053A 


Preliminary 


TEST CIRCUITS 



VDDRJ- 

V SS CLOCK 


vee- 

— 17“ 

16 

OUTPUT 2 

15 

-T 

>— 3 

14 

IOK< 

s !5 4 

13 




VDD- 

5 

12 


h— 6 

II 

Vee- 

7 

10 

Vss- 


9 



Vss 



D TU 

ss CLOCK 



11 L VDD n_r 

IOh-Vcc-» U 


Fig. 13 — Turn-on propagation delay . . . control input to signal output. 


-|Vee iok|3 

J vJ D 



PRELIM 
OUTPUT CD405IA 


V DD_ . 

Veo -TLI 

ss CLOCK 

IN V EE - 



V DD_ , 

Vss 

ss cl i?F k vee- 


00 n i - 
Vss Ju 
Vee 



Vdd_ _ 
vss^- 

CLOCK 



Fig. 14 — Turn-on propagation delay . . . inhibit 
input to signal output. 


*PHL ** 

92CM- 22725 


266 










File No. 634 


OUCBZ/D 

Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4054AD CD4054AE CD4054AK 
CD4055AD CD4055AE CD4055AK 
CP4056AD CD4056AE CD4056AK 



COS/MOS Liquid-Crystal Display Drivers 

CD4054A — 4-Segment Display Driver 
CD4055A — BCD to 7-Segment Decoder/Driver with 
“Display-Frequency" Output 
CD4056A — BCD to 7-Segment Decoder/Driver with 
Strobed-Latch Function 

Features: 

■ Operation of liquid crystals with COS/MOS circuits 

provides ultra-low-power displays 

■ Equivalent AC output drive for liquid-crystal displays — 

no external capacitor required 
b Voltage doubling across display [(Vdd —Vee) = 15 V] 
results in effective 30 V (p-p) drive across 
selected display segments 


RCA-CD4055A and CD4056A are Single-Digit BCD-to-7- 
Segment Decoder/Driver circuits that provide level-shifting 
functions on the chip. This feature permits the BCD input- 
signal swings (Vdd to V§s) to be the same as or different from 
the 7-segment output-signal swings (Vdd to Vee)- For 
example, the BCD input-signal swings (Vdd to Vss)may be as 
low as 0 to —3 V, whereas the output-display drive-signal 
swing (Vqd to Vee) ma Y be from 0 to —15 V. 

The 7-segment outputs are controlled by the “Display-Fre- 
quency" (DF) input which causes the selected segment outputs 
to be "low", "high", or a "square-wave" output (for liquid- 
crystal displays). When the DF input is "low" the output 
segments will be "high" when selected by the BCD inputs. 
When the DF input is "high", the output segments will be 
"low" when selected by the BCD inputs. When a square wave 
is present at the DF input, the selected segments will have a 
square-wave output which is 180° out of phase with the DF 
input. Those segments which are not selected will have a 



Fig.2 — CD4054A Functional block diagram 


■ Low- or high-output level DC drive for other types 

of displays 

n On-chip logic — level conversion for different input- 
and output-level swings 

■ Full decoding of all input combinations: ‘"0—9, 

L, H, P, A, — ," and blank positions 
b Strobed-latch function — CD4054A and CD4056A 
b "Display-frequency" (DF) output for liquid-crystal 
common-line drive signal CD4054A and CD4055A 


Applications: 
b General-purpose displays 
■ Calculators and meters 
b Wail and table clocks 
b Industrial control 
panels 


■ Portable lab instruments 

■ Panel meters 

■ Auto dashboard displays 

■ Appliance control panels 



4-73 


267 






CD4054A, CD4055A, CD4056A 


File No. 634 


Maximum Ratings, Absolute-Maximum Values: 


Storage-Temperature Range . . . 

-65 to +150 

°C 

Operating-Temperature Range: 

Ceramic Package Types .... 

-55 to +125 

°C 

Plastic Package Types .... 

-40 to +85 

°C 

DC Supply-Voltage Range 

(Vdd- v ss> or (Vdd- v ee) • • 

—0.5 to +15 

V 

Device Dissipation (Per Pkg.) . . . 

All Inputs 

200 

Vss<V|<Vdd 

mW 



Fig.4 — Clock display: Vqq = 0 V, V§S * —5 V. VEE ~ —15 V, 
DF//\j * 30 Hz square wave 


square-wave output that is in phase with the input. The DF 
input square wave is required to provide equivalent ac drive to 
liquid-crystal displays such as RCA Dev. Nos. TA8054R, 
TA8054T, TA8055R, and TA8055T. DF square- wave repeti- 
tion rates for liquid-crystal displays usually range from 30 Hz 
(well above flicker rate) to 200 Hz (well below the upper 
limit of the liquid-crystal frequency response). The CD4055A 
provides a level-shifted high amplitude DF output which is re- 
quired for driving the common electrode in liquid-crystal dis- 
plays. The CD4056A provides a strobed latch function at the 
BCD inputs. Decoding of all input combinations on the 
CD4055A and CD4056A provides displays of 0 to 9 as well as 
"L, H, P, A, — ," and a blank position. 

The CD4054A provides level shifting similar to the CD4055A 
and CD4056A, independently strobed latches, and common 
DF control on 4 signal lines. The CD4054A is intended to 
provide drive-signal compatibility with the CD4055A and 
CD4056A 7-segment decoder types for the decimal point, 
colon, polarity, and similar display lines. A level-shifted high- 
amplitude DF output can be obtained from any CD4054A 
output line by connecting the corresponding input and strobe 
lines to a "low" and "high" level, respectively. The CD4054A 
may also be utilized for logic-level "up conversion" or "down 
conversion". For example, input-signal swings (Vdd t0 Vss) 
from +5 to 0 V can be converted to output-signal swings 


Minimum Recommended 
DC Supply Voltage (Vdd _v SS) or 

(Vdd-Vee) 3 V 

Lead Temperature (During Soldering) 

At distance 1/16 ± 1/32 inch 
(1.59 ± 0.79 mm) from case 

for 10 seconds max 265 °C 


’ ANALOG INPUTS (±5V) 

- 5 9 9 9 9 V DD- + 5V 



92CS-20096 R 1 

Fig. 5 — Digital (0.5 V) to bidirectional analog control 
(+5 to —5 V) level shifter 


(Vdd t0 Vee) of +5 to —5 V. The level-shifted function on all 
three types permits the use of different input- and output- 
signal swings. The input swings from a "low" level of Vss 
to a high level of Vqd while the output swings from a "low" 
level of Vee to the same "high" level of Vdd- Thus the input 
and output swings can be selected independently of each other 
over a 3-to-15 V range. Vss may be connected to Vee when 
no level-shift function is required. 

For the CD4054A and CD4056A data is transferred from input 
to output by placing a "high" voltage level at the strobe input. 
A "low" voltage level at the strobe input latches the data input 
and the corresponding outputs. 

Whenever the level-shifting function is required, the CD4055A 
can be used by itself to drive a liquid-crystal display (Figs. 4 
and 7). However, the CD4056A must be used together with a 
CD4054A to provide the common DF output (see Fig. 8). The 
capability of extending the voltage swing on the negative end 
can be used to advantage in the setup of Fig.5. Fig.6 is 
common to all three 1C types. 

These devices are available in 16-lead dual-in-line ceramic 
packages ("D suffix), dual-in-line plastic packages ("E" suffix), 
16-lead flat packages (" K " suffix), or in chip form ("H" suffix). 



268 









CD4054A, CD4055A, CD4056A 


File No. 634 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V ss < V, < V DD ) 

(Recommended DC Supply Voltage (Vqqj - Vgs) • 3 to 15 V) 


CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 

LIMITS 


CHARAC- 

TERISTIC 

CURVES 

8. TEST 
CIRCUITS 

Fig. No. 

CD4054AD CD4054AK 

CD4055AD CD4055AK 

CD4056AD CD4056AK 


V D d- 

V SS 

V DD~ 

v ee 

— 55°C 

25°C 

125°C 




MW! 




Hi 


Quiescent Device 
Current 

D 


5 

10 

_ 

_ 

10 

_ 

mm 

mm 

_ 

_ 

mm 

PA 

18,19,20 


15 

15 

- 

- 


- 

i 


_ 

_ 


Quiescent Device 
Dissipation/Package 

Po 


5 

10 

_ 

_ 

wm 

_ 

5 


_ 

m 

B91 

pW 



15 

15 


- 

BcV'l 

- 

■a 


- 

m 

EB1 

Output Voltage: 

Low-Level 

V OL 

■ 

H 

10 


■ 

BR 


H 



m 

BB 

■ 




15 

- 

- 


- 

0 


- 




VOH 


• 

10 

EH 

- 

- 

9.99 

10 

_ 


_ 

_ 

V 



mm 

15 

Esa 

- 

- 

KMET1 

■n 

- 





v NL 

1 

n 

10 

i 

- 


i 


_ 

i 

_ 

_ 

D 


m 

15 

15 

2 

- 


2 


- 

2 

_ 

_ 

v N h 

* 

5 

10 

1 

_ 

_ 

1 


_ 

1 

_ 

_ 


KES 

15 

15 

WBM 

- 

- 

2 

Bn 


2 

_ 

_ 

Output Drive Current: 
(All Outputs) 

N -Channel 

IqN 


■ 



1 

■ 

0.9 

1.8 


0.6 


■ 

mA 

11,12 

m 

SB 

15 

HI 

- 

- 

1.4 

EH 

- 

1 

- 

- 

(All Outputs) 

P-Channel 

'dp 

n 

m 


H 




n 


■ 



mA 

13,14 


« 

15 

mm 

- 

- 

■S3 

mn 

~ 


~ 

- 


* For definition, see Appendix. 



^ ::rumrinnjuuuuuui 

SEG “ ENr '\°J I I L 

— juijirmjiajiJirLr 


_(v OD _v EE ) 




92CS- 20009 Rl 


Fig. 7 — Single-digit liquid-crystal display 


DF 1N “DISPLAY-FREQUENCY INPUT 92CS- 20094RI 

df out , level- shifted display- frequency output 
lb) 

Fig. 6 — Display-driver circuit for one segment line and waveforms 


269 































CD4054A, CD4055A, CD4056A 


File No. 634 


STATIC ELECTRICAL CHARACTERISTICS (All inputs Vss < V, < V DD ) 

(Recommended DC Supply Voltage (Vqq — Vgg) 3 to 15 V) 


CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 

LIMITS 

UNITS 

CHARAC- 
TERISTIC 
CURVES 
& TEST 
CIRCUITS 

Fig. No. 

CD4054AE 

CD4055AE 

CD4056AE 

Q 



— 40°C 

25°C 

85°C 


BH 


BOI 



BBJISi 

PHI 


Quiescent Device 

Current 

m 


5 

10 

- 

- 

,0 

- 

mm 

mm 

- 



mA 

18,19,20 


15 

15 

- 

- 

EQB 

- 

i 

Em 

- 

- 


Quiescent Device 
Dissipation/Package 

B 


5 

10 

- 

- 

ua 

- 

5 

m 

- 

- 

500 

pW 



15 

15 

- 

- 


- 

mm 


- 

- 


Output Voltage: 

Low-Level 



5 

10 


■ 



0 

n 



0.05 

V 



mm 

15 

- 

- 

jJB 

- 

0 


- 

- 


High-Level 



5 

10 


- 

- 

E 

na 

~ 

B9 

- 

- 

V 



mm 

15 


- 

- 

iy 


~ 


- 

- 

Noise Immunity 
(All Inputs)* 

B 

i 

5 

10 

i 

_ 

_ 

*M 



i 

- 

- 

V 


oa 

wm 

MM 

2 

- 

- 

2 

tia 

- 

2 

- 

- 

Vnh 

9 

mm 

10 

1 

_ 

_ 

1 



1 

- 

- 

V 


15 

15 

2 

- 

- 

2 

6.75 

- 

2 

- 

- 

Output Drive Current: 

(All Outputs) 

N-Channel 

i d n 

0.5 

5 

10 


1 

■ 

0.6 

1.8 


0.5 



mA 

11,12 

oa 

15 

15 

1.2 

- 

- 

1 

2.8 

- 


- 

- 

(All Outputs) 

P-Channel 

'dp 

9.5 

5 

10 

-0.4 



-0.3 


_ 




mA 

13,14 

|Q9 

15 

15 

-0.6 

- 

- 

-0.5 

HQ 


EH 

- 

- 


* For definition, see Appendix. 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, C L = 15 pF, and input rise and fall times = 20 ns 
Typical Temperature Coefficient at all values of V^ = 0.3%/°C 


CHARACTERISTICS 

SYMBOLS 


LIMITS 

UNITS 

CHARAC- 

TERISTIC 

CURVES 

Fig. No. 

CD4054AD.AK 

CD4055AD.AK 

CD4056AD.AK 

CD4054AE 

CD4055AE 

CD4056AE 

V DD-VSS 

V DD" V EE 

a 

is 



KM 


Propagation 

Delay Time 
(Any Input to Any 
Output) 

■ 

5 

10 

_ 

450 

900 

_ 

B 

1200 

B 

- 

15 

15 

- 

300 

600 

- 

3 

800 

Transition Time 

(Any Output) 

ma 

5 

10 

_ 

mm 

80 

_ 

mm 

mm 

n 

- 

15 

15 

- 

E21 

60 

- 

30 

80 

osssbh 

h 

5 

10 

_ 

mm 

EffE 

- 

70 

EBB 

n 

9 

15 

15 

- 

mm 

60 

- 

mm 

mm 

Strobe Pulse* 

Duration 

t W 

5 

10 

- 

mm 

mm 

_ 

■a 

EEEE 

a 

9 

15 

15 


40 

80 

- 

mm 

IBS 


C, 

Any Input 

- 

5 

- 


5 


PF 

- 


* CD4054A and CD4056A only. 


270 

























































CD4054A, CD4055A, CD4056A 


File No. 634 


DRAIN- TO -SOURCE VOLTAGE I V DS ) — V DRAIN-TO-SOURCE VOLTAGE (V D g) — V 




Fig. 13 — Typical p-channel drain choiacierisacs Fig. 14 — Minimum p-channel drain characteristics 





-IOV 


Fig. 18 — Quiescent-device-current test circuit for CD4054A. 



-IOV 


Fig. 19 — Quiescent-device-current test Fig.20 — Quiescent-device-current 
circuit for CD4054A. test circuit for CD4056A. 


272 










File No. 635 



Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4057AD 
CD4057AK 
CD4057AH 



COS/MOS LSI 4-Bit Arithmetic 


Logic Unit 

Applications: 

■ Parallel Arithmetic Units 

■ Process Controllers 

Features: 

* LSI Complexity on a Single Chip 

■ 16-Instruction Capability 
-Add, Subtract, Count 
-AND, OR, Exclusive-OR 
-Right, Left, or Cyclic Shifts 


a Remote Data Sets 
■ Graphic Display Terminals 


■ Bidirectional Data Busses 

■ Instruction Decoding on Chip 
n Fully Static Operation 

■ Single-Phase Clocking 


RCA-CD4057A is a low-power arithmetic logic unit (ALU) 
designed for use in LSI computers. An arithmetic system of 
virtually any size can be constructed by wiring together a 
number of CD4057A ALU's. The CD4057A provides 4-bit 
arithmetic operations, time sharing of data terminals, and 
full functional decoding for all control lines. The distributed 
control system of this device provides great flexibility in 
system designs by allowing hard-wired connection of N units 
in 4N unique combinations. Four control lines provide 16 
instructions which include Addition, Subtraction, Bidirec- 
tional and Cycle Shifts, Up-Down Counting, AND, OR, and 
Exclusive-OR logic operations. 


■ Easily Expandable to 8, 12, 16, . . . Bit Operation 

■ Conditional-Operation Controls on Chip 

o Low Quiescent Device Dissipation ... 10 juW (typ) at 
V DD =10V 

■ Add Time (Data In-ToSum Out) = 375ns(typ)at10V 

■ All Terminals Protected Against Static Discharge 

■ High Noise Immunity . . . 45% of Vqq (typ) Over Full 
Temperature Range 

■ Operation from Single Positive or Negative 
Power Supply ... 3 V to 15 V 

■ Full Military Temperature Range . . . — 55°C to +125°C 



PARALLEL DATA I 
PARALLEL DATA 4 
PARALLEL DATA 2 
NEGATIVE INDICATOR 
ZI INPUT 
INPUT c 
INPUT d 

CONDITIONAL INPUT A 

CONDITIONAL INPUT C 

RIGHT SERIAL DATA 
LINE 

BYPASS 

NC 

MODE-CONTROL INPUT 
LINE Cl 

Ro I 


* NOTE: NON-STANDARD TERMINAL LOCATIONS FOR 
V SS AND V DD . MOST OTHER COS/MOS TYPES 
USE CORNER TERMINALS FOR POWER- 
SUPPLY CONNECTIONS 

92CS-20253 



Fig. 1 — Block diagram — CD4057A. 


Fig. 2 — Terminal assignments. 


11-73 


273 








CD4057AD, CD4057AK, CD4057AH 


File No. 635 


Two mode control lines allow the CD4057A to function as 
any 4-bit section of a larger arithmetic unit by controlling 
the bidirectional serial transfer of data to adjacent arithmetic 
arrays. By means of three “Conditional Control" lines 
Overflow, All Zeros, and Negative State conditions may be 
detected and used to establish a conditional operation. 
Predetermined operation of the CD4057A on a conditional 
basis allows greater ALU flexibility. Although especially 
applicable as a parallel arithmetic unit, the CD4057A also 
finds use in virtually any application requiring one or more 
of its 16 basic instructions. The CD4057A is supplied in a 
hermetically sealed 28-lead dual-in-line ceramic package 
(CD4057AD), in a flat-pack (CD4057AK), and in chip 
form (CD4057AH). 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V $s < V, < V DD ) 

(Recommended DC Supply Voltage (Vqq — Vjjg) 3 to 15 V) 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V $s < V, < V DD ) 

(Recommended DC Supply Voltage (Vqq — Vjjg) 3 to 15 V) 


CHARACTERISTIC 

SYMBOL 

TEST 

LIMITS 

UNITS 

CONDITIONS 

CD4057AD, CD4057AK 


v 0 

Volts 

V DD 

Volts 

— 55°C 

25°C 

125°C 

moii 

EES 

1^23 

1223 

ET8 

1223 

1223 

C73 

32231 

Quiescent Device 

Current 

mm 



5 

_ 

91 

EH 

K9H 

CEB 

WEM 

_ 

— 

m 

(jlA 


BEE 

- 

Hi 1 

EH 

- 


d 

- 

- 

hh 

Quiescent Device 
Dissipation/Package 

n 



5 

_ 

_ 

18.5 

Hi 

m 

1PW 

_ 

_ 

Hi 

EE 


EEE 

- 

- 

75.0 

Hi 

wm 

IH 

- 

- 


Output Voltage: 

Low-Level 




5 

_ 

- 

81BT1 

- 

- 

bbh 

- 

- 

0.05 

WM 


BEE 

- 

- 


- 

- 

Hi 

- 

- 

0.05 

High Level 




5 

4.99 

_ 

_ 

ERjl 

wm 

_ 

4.95 

_ 

_ 

WM 


O 


- 

- 

CI%1 

■El 

- 

EE3 

- 

- 

Noise Immunity 
(All Inputs) 

For Definition 

See Appendix 

V NIL 


MB 

5 

wm 

_ 

_ 

wm 

BBS 

_ 

EH 

_ 

_ 

V 

i 

mm 

3 

- 

- 

mm 

EH 

- 

ra 

- 

- 

V NIH 


m 

5 

BE1 

_ 

_ 

wm 

BBS 

_ 

wm 

_ 

_ 

9 

10 

mm 

_ 

_ 

3 

ESH 

_ 

3 

_ 

_ 

Output Drive Current: 

Zero Indicator 

n-channel 

IqN 

1 

0.5 

5 

0.11 

B 

B 



B 

0.06 

B 

■ 

mA 

HTJ 

BEE 

litfli 

- 

- 

122 m 

BBS 

- 

Q3 

- 

- 

p-channel 

'dp 


wm 

n 

EBB 

_ 

_ 

EBB 

0.06 

_ 

0.02 

_ 

_ 


BEE 

EH 

- 

- 

EH 


- 

ItWdfc 

- 

- 

Negative Indicator 

n-channel 



EK3 

5 

EHI 

- 

- 

0.09 

0.30 

_ 

0.06 

- 

_ 

BB 

bee 

MW 

- 

- 

EWtl 

0.40 

- 

0.07 

_ 

- 

p-channel 



e m 

wm 

EBB 

_ 

_ 

0.06 

0.19 

_ 

0.04 



BIB 

BEE 

MW 

- 

- 

CTffl 

BBS! 

Hi 

BBTB 

- 

- 

Overflow Indicator 
n-channel 

i d n 


EH 

wm 

BBS 

_ 

_ 

BBS 

BBS 


0.14 

_ 

_ 

EH 

BEE 


Hi 

- 



Hi 

PHI 

- 

- 

p-channel 

•dp 


ESI 

5 


M 

- 

ng 

beh 

HI 

0.05 

_ 

_ 

EUSi 

bee 


Hi 

- 

0.10 

0.38 

- 

BBfS 

- 

- 

All Other Outputs 

n-channel 

i d n 


m 

B9 

EHI 


- 

HF1 

EH 

- 

0.06 

- 

_ 

is 

BEE 

Hi 

Hi 

- 

001 

HRS 

Hi 


- 

- 

p-channel 

»D p 


E83 

wm 

0.02 

_ 

_ 


0.05 

_ 

0.01 

_ 

_ 

EJ3I 

!BEB 

EB!i 

- 

- 

0.05 

0.08 

~ 

0.03 

- 

- 


MAXIMUM RATINGS, Absolute Maximum Values: 


STORAGE-TEMPERATURE RANGE -65 to +150 °C 

OPERATING-TEMPERATURE RANGE -55 to +125 °C 

DISSIPATION PER PACKAGE 200 mW 

DC SUPPLY- VOLTAGE RANGE (V DD -V SS ) -0.5 to +15 V 

ALL INPUTS V SS <V, < V DD 

Lead Temperature (During soldering) 

At distance 1/16 ± 1 /32 inch (1 .59 ± 0.79 mm) 

from case for 1 0 seconds max 265 °C 

MINIMUM RECOMMENDED 

DC SUPPLY VOLTAGE (V DD ~V SS ) 3 V 


274 









































File No. 635 


CD4057AD, CD4057AK, CD4057AH 


DYNAMIC ELECTRICAL CHARACTERISTICS, at T A = 25°C and C L = 15 pF 

Typical Temperature Coefficient at all values of Vqq = 0.3%/° C 


CHARACTERISTICS 

SYMBOLS 

TEST 

CONDITIONS 



Vdd 

Volts 

Min. 

Propagation Delay Time: 
DATA IN-to- 

SUM OUT 

l PLH, 

t PHL 


5 


10 

- 

CARRY IN-to- 

SUM OUT 

5 

_ 

10 

- 

DATA IN-to- 

CARRY OUT 

5 

_ 

10 

- 

CARRY IN-to- 
CARRY OUT 

5 

_ 

10 

- 

Zl Input 

-to- 

Zl Output 

l PLH 

5 


10 

_ 

tPHL 

5 

- 

10 

_ 

Transition Time: 

Zl Output 

*TLH 


5 


10 

- 

l THL 

5 

_ 

10 

_ 

Negative Indicator and 
Overflow Indicator 

*TLH > 
l THL 

5 

- 


- 

All Other 

Outputs 

5 

_ 

10 

- 


Minimum Clock Pulse 

Width 

%L» X \NH 


Clock Rise and Fall Time 

t r CL, t f CL 


Set Up Time : 



DATA 

l SLH' t SHL 


OP CODE 




Data Hold Time 


x Dh 



Maximum Clock Frequency: 

Count Mode 

f CL 

Shift Mode 

f CL 



Input Capacitance Cj ANY INPUT 
























































CD4057AD, CD4057AK, CD4057AH 


File No. 635 


PARALLEL DATA 


OVERFLOW OVERFLOW LEFT NEG. 

I/O IND. SERIAL IND. 

DATA 

LINE 



Fig. 3 — Simplified logic diagram. 


LOGIC DESCRIPTION 



l PD (°I ~ Cq> + 3 *PD ( C I - c q) = 790 ns 


*PD < D I “ c O> + 2 l PD < C I _ C 0 ) + tpo 

8,3,6 

tpD (D r - Cq) + 2 t PD (Ci - C 0 ) = 615 ns 


tpo < D I “ C 0 ) + tpo (Ci - Cq)+ tpQ 

S9-12 

(Cj - Sq) = 750 ns 

tpQ (Dl - Cq) + tpo (Ci - Cq) = 440 ns 


D5-8 

S5-8 


tpD (°I - Cq) + tpQ (Ci - Sq) = 575 ns 


tpo (Dj - Cq) = 265 ns 
D1-4 


SI-4 


tpo (Dl - Sq) = 375 ns 


OPERATIONAL MODES 

The CD4057A arithmetic logic unit operates in one of four 
possible modes. These modes control the transfer of infor- 
mation, either serial data or arithmetic operation carries, to 
and from the serial-data lines. Fig. 5 shows the manner in 
which the four modes control the data on the serial-data 
lines. 



6 BYPASS 
j VSS°N>- fMODE 2 1 -C^~vss; 



LEFT !vsS°NH MODE 3l~a*' > "^S l | RIGHT -*-T — $MODE 3^— f*- 

data o-4- t-o . V - e odata [ ] 


vss 


92CS-20252RI 


Fig. 4 — Typical speed characteristics of a 16-bit ALU at V qq = 10 V. 


Fig. 5 — Schematic of "Mode" concept. 


276 

















File No. 635 


CD4057AD, CD4057AK, CD4057AH 


In MODE 0, data can enter or leave from either the left or 
the right serial-data line. 

In MODE 1, data can enter or leave only on the left serial- 
data line; 

In MODE 2, data can enter or leave only on the right serial- 
data line. 

In MODE 3, serial data can neither enter nor leave the regis- 
ter, regardless of the nature of the operation. 
Furthermore, the register is by-passed electri- 
cally, i.e., there is an electrical bidirectional 
path between the right and left serial data 
terminals. 


The two input lines labeled Cl and C2 in the terminal assign- 
ment diagram define one of four possible modes shown in 
Table I. 

Through the use of mode control, individual arithmetic arrays 
can be cascaded to form one large processor or many proces- 
sors of various lengths. 


TABLE I - MODE DEFINITION 


C2 

Cl 

MODE 

0 

0 

0 

0 

1 

1 

1 

0 

2 

1 

1 

3 


Examples of how one "hard-wired" combination of three 
ALU's can form (a) a 12-bit parallel processor, (b) one 8-bit 
and one 4-bit parallel processor, or (c) three 4-bit parallel 
processors, merely by changes in the modes of each ALU 
are shown in Fig. 6. 



L | MODE i 1— |mOQ E3 ^ J 


92CS-20254 


Fig. 6— "Mode" connections for parallel 
processor: 

(a) 12-bit unit, 

(b) one 8-bit and one 4-bit unit 

(c) three 4-bit units. 


Data-flow interruptions are shown by shaded areas. With 
these three ALU's and the four available modes, 61 more 
system combinations can be formed. If 4 ALU's are used, 
4^ combinations (256) are possible. Fig. 7 shows a diagram 
of 4 CD4057A's interconnected to form a 16-bit parallel 
processor. 

NOTE: The BYPASS terminal of the "most significant” 
CD4057A is connected to the bypass terminal of the "least 
significant" CD4057A. The bypass terminals on all other 
CD4057A's are left floating. This interconnection is per- 
formed whenever more than one CD4057A are used to form 
a processor. 

INSTRUCTION REPERTOIRE 

Four encoded lines are used to represent 16 instructions. 

Encoded instructions are as follows: 


abed 


0 0 0 0 

NO-OP (Operational Inhibit) 

0 0 0 1 

AND 

0 0 10 

Count down 

0 0 11 

Count up 

0 10 0 

Subtract Stored number from zero (SMZ) 

0 10 1 

Subtract from parallel data lines (SM) 


(stored number from parallel data lines) 

0 110 

Add (AD) 

0 111 

Subtract (SUB) (Parallel data lines from stored 


number) 

10 0 0 

Set to all ones (SET) 

10 0 1 

Clear to all zeroes (CLEAR) 

10 10 

Exclusive-OR 

10 11 

OR 

110 0 

Input Data (From parallel data lines) 

110 1 

Left shift 

1110 

Right shift 

1111 

Rotate (cycle) right 


All instructions ar executed on the positive edge of the clock. 

PARALLEL COMMANDS 

a. CLEAR — sets register to zero. 

b. SET — sets register to all ones. 

c. OR — processes contents of register with value on 
parallel-data lines in a logical OR function. 

d. AND — processes contents of register with value on 
parallel-data lines in a logical AND function. 

e. Exclusive-OR — processes contents of register with data 
on parallel-data lines in a logical Exclusive-OR function. 

f. IN — loads data on parallel-data lines into register. 

g. DATA OUT CONTROL — unloads contents of register 
and overflow flip-flop onto parallel data lines and over- 
flow I/O independent of all other controls. 

h. SUB: 

In Mode 0, adds to the contents of the register the one's 
complement of the data on the parallel-data 
lines. Carries can enter on the right serial 
data line and can leave on the left serial data 
line. The overflow indicator does not change 
state. 


277 




CD4057AD, CD4057AK, CD4057AH 


File No. 635 


In Mode 1 , adds to the contents of the register the two's 
complement of the data on the parallel-data 
lines. Generated carries can leave on the left 
serial line. The CARRY IN is set to zero. 
The overflow indicator does not change 
state. 

In Mode 2, same as Mode 0, except carries cannot leave 
on the right serial-data line. The absence or 
presence of an overflow is registered. 

In Mode 3, same as Mode 1, except carries cannot leave 
on the left serial-date line. The absence or 
presence of an overflow is registered. 

i. COUNT UP: 

In Mode 0, adds to the contents of the register the data 
on the right serial-data line and permits any 
resulting carry to leave on the left serial-data 
line. No data enters the parallel-data lines. 

In Mode 1, internally adds a one to the contents of the 
register and permits any resulting carry to 
leave on the left serial-data line. No data 
enters or leaves the right serial -data line. 

In Mode 2, adds to the contents of the register the data 
on the right serial-data line. No data enters 
or leaves the left serial-data line. 

In Mode 3, internally adds a one to the contents of the 
register. No data enters or leaves the register 
on any serial-data or parallel-data line. 

In all modes, with the DATA OUT control 
"high" the count is presented on the parallel 
data lines (D1-D4). 


j. COUNTDOWN: 

In Mode 0, subtracts a one (2's complement form) 
from the contents of the register and adds 
to this result the data on the right serial- 
data line and permits any resulting carry to 
leave on the left serial-data line. No data 
enters on the parallel-data lines. 

In Mode 1, internally subtracts a one from the contents 
of the register and permits any resulting 
carry to leave on the left serial-data line. No 
data enters or leaves the right serial-data 
line. 

In Mode 2, subtracts a one from the contents of the 
register and adds to this result the data on 
the right serial-data line. No data enters or 
leaves on the left serial-data line. 

In Mode 3, internally subtracts a one from the contents 
of the register. No data enters or leaves on 
the serial-data lines. 

In all modes, with the DATA OUT control "high" the 
count is presented on the parallel data lines (D1-D4). 

k. ADD (AD): 

In Mode 0, adds the contents of the register to the data 
on the parallel-data lines and the right 
serial-data line. Any resulting carry can leave 
on the left serial-data line. The overflow 
indicator does not change state. 

In Mode 1, adds the contents of the register to the data 
on the parallel-data lines and allows any 
resulting carry to leave on the left serial-data 
line. The right serial-data line is open- 
circuited. The overflow indicator does not 
change state. The CARRY-IN is set to zero. 


p m EL 



V DD ft TERMINAL INTENTIONALLY LEFT FLOATING V DD V SS 

92CS- 20259 


Fig. 7 — Connection for 16-bit Arithmetic Logic Unit. 


278 





File No. 635 


CD4057AD, CD4057AK, CD4057AH 


In Mode 2, adds the contents of the register to the data 
on the parallel data lines and the right serial 
data line. Any overflow sets the overflow 
indicator. The left serial data line is open- 
circuited. The absence or presence of an 
overflow is registered. 

In Mode 3, adds contents of the register to the data on 
the parallel-data lines. Any resulting carry 
sets the overflow indicator. The two serial- 
data lines are open circuited. The absence 
or presence of an overflow is registered. 

The CARRY— IN is set to zero. 

l. SM— same operation as AD except the contents" of the 
register are two's complemented during addition in 
Mode 1 and Mode 3. In Mode 0 or Mode 2, the contents 
of the register are one's complemented and added to the 
data on the right serial-data line and the parallel-data 
lines. Overflows occurring in Mode 1 or Mode 0 do not 
alter the overflow indicator. The presence or absence of 
overflows is registered on the overflow indicator in Mode 
2 or Mode 3. 

m. SMZ: 

In Mode 0, one's complements the contents of the 
register and adds the data on the right 
serial-data line to the contents of the regis- 
ter. Any resulting carry can leave on the left 
serial-data line. The overflow indicator does 
not change state. 

In Mode 1, two's complements* the contents of the 
register and permits any carry to leave on 
the left serial-data line. No data can enter 
the right serial-data line. The overflow in- 
dicator does not change state. The CARRY- 
IN is set to zero. 

In Mode 2, one's complements the contents of the 
register and adds the data on the right 
serial-data line to the contents of the regis- 
ter. Carries cannot leave the left serial data 
line. The absence or presence of an overflow 
alters the overflow indicator. 

In Mode 3, two's complements the contents of the 
register. Serial data can neither enter the 
right serial-data line nor leave the left 
serial-data line. The overflow indicator is at 
zero. The CARRY-IN is set to zero. 

n. NO-OP — no operation takes place. The clock input is 

inhibited and the state of all registers and 
indicators remains unchanged. 

SERIAL-SHIFT OPERATIONS 

a. ROTATE (cycle) RIGHT — This operation is internal. 
The contents of the register shift to the right, cyclic 
fashion with the leftmost stage accepting data from the 
rightmost stage regardless of the mode. Data can leave 
the register serially on the right data line only while the 


register is in Mode 2 or Mode 0. Data can enter the left 
data line serially while the register is in Mode 1 or Mode 
0. The Rol terminal of the "Most Significant" 
CD4057A must be connected to the Ro2 terminal of the 
"Least Significant" CD4057A. All other Rol and Ro2 
terminals must be left floating. When only one CD4057A 
is used, Rol must be connected to Ro2. 

b. RIGHT SHIFT - The contents of the register shift to the 
right and serial operations are as follows: 

In Mode 0, data can enter serially on the left data line, 
shift through the register, and leave on the 
right data line. 

In Mode 1, data can enter serially on the left data line. 

The right data line effectively is open- 
circuited. 

In Mode 2, data can leave serially on the right data line. 

The left data line effectively is open- 
circuited. Vacant spaces are filled with 
zeros. 

In Mode 3, serial data can neither enter nor leave the 
register; however, the contents shift to the 
right and vacated places are filled with zeros. 

In all modes, with the DATA OUT control "high" the 
data is presented on the parallel data lines (D1-D4). 

c. LEFT SHIFT - The contents of the register shift to the 
left and serial operations are as follows: 

In Mode 0, data can enter the right data line, shift 
through the register, and leave on the left 
data line. 

In Mode 1, data can leave serially on the left data line. 

The right data line effectively is open- 
circuited. All vacant positions are filled with 
zeros. 

In Mode 2, data can enter serially on the right data line. 

The left data line effectively is open- 
circuited. 

In Mode 3, data can neither enter nor leave the register; 

however, the contents shift to the left, and 
vacated places are filled with zeros. 

In all modes, with the DATA OUT control "high" the 
data is presented on the parallel data lines (D1-D4). 

Because the "DATA OUT" control instruction is inde- 
pendent of the other 16 instructions, care must be taken not 
to activate this control when data are to be loaded into the 
processor. This instruction should only be activated when the 
processor is executing a NO-OP, any SHIFT, SMZ, COUNT 
UP or DOWN, CLEAR, or SET. 

If a data line, serial or parallel, is used as an input and the 
logic state of that line is not defined (i.e., the line is an open 
circuit), then the result of any operation using that line is 
undefined. 


279 



CD4057AD, CD4057AK, CD4057AH 


File No. 635 



NOTES: Rol CONNECTED TO Ro2; by pass is open; zi connected to v od . register IN MODE 3. 

• SOLID LINE REPRESENTS INPUT FROM EXTERIOR SOURCE WHEN "DATA OUT* IS LOW; DASHED LINE 
REPRESENTS OUTPUT WHEN "DATA OUT" IS HIGH. 


Fig. 8 - Timing Diagram , 


281 




File No. 635 


CD4057AD, CD4057AK, CD4057AH 


OPERATIONAL SEQUENCE FOR ARITHMETIC 
ADD CYCLE 

1. Apply IN Instruction and Word A on Parallel Data Lines 
(D1-D4). 

2. Apply CLOCK to load Word A into the register. 

3. Apply OP CODE Instruction and Word B on Data Lines. 

4. Apply CLOCK to load resulting function of A and B 
into the register. 

5. Apply “DATA OUT" control to present result to Parallel 
Data Lines. 

NOTE: Transitions of Step 2 and Step 3 may occur almost 
simultaneously; i.e. separated by only one data-hold time. 



t t t t t 

12 3 4 5 


* SOLID LINE REPRESENTS INPUT 
FROM EXTERIOR SOURCE WHEN 
'iDATA OUT" IS LOW. DASHED LINES 
REPRESENT OUTPUT WHEN "DATA 
OUT" IS HIGH 


92CS-2I877 


Fig. 9 — Add cycle waveforms. 


ZERO DETECTION 

The condition of “all zeros" is indicated by a "1" on the 
Zero Indicator terminal of the "Most Significant" CD4057A. 
As shown in Fig. 7, terminal Zl of the CD4057A containing 
the least significant set of bits is connected to Vqq. Zero 
indication is independent of modes. 


NEGATIVE-NUMBER DETECTION 

The NEG IND terminal of the CD4057A is connected to the 
output of the flip-flop that is in the most significant bit 
position. A "1" on the NEG IND terminal indicates a 
negative number is in the register. This detection is also 
independent of modes. 

COMPLEMENTING NUMBERS 

1 . One's complement of number in ALU register. 

a) ALU must be in MODE 0 or MODE 2. 

b) Zero on Rt. Data Line. 

c) Execute an SMZ instruction. 

2. One's complement of number to be loaded into ALU 
register. 

a) If zero indicator output is low, execute a CLEAR 

instruction, and make Rt. Data Line = 0. 

b) ALU must be in MODE 0 or MODE 2. 

c) Execute an SUB instruction. 

3. Two's complement of number in ALU register. 

a) ALU must be in MODE 1 or MODE 3. 

b) Execute an SMZ instruction. 

4. Two's complement of number to be loaded into ALU 

register. 

a) If zero indicator output is low, execute a CLEAR 
instruction, and make Rt. Data Line = 0. 

b) ALU must be in MODE 1 or MODE 3. 

c) Execute an SUB instruction. 

The following algorithms are given as a general guideline to 
demonstrate some of the capabilities of the CD4057A. 

MULTI PLICATON OF TWO N-BIT NUMBERS 


Register 1 
(2N Bits) 

. .0/A $ a v . , .00/B s *b-j. , .b N _y 

Multiplier Multiplicand 

‘Aj and B s are sign bits 


CD4057A 

ALU 

(2 N Bits) 


00 . . . 0 / 00 . . .0 


Register 2 
(2N Bits) 


Multiplication Algorithm 

1. Clear ALU to Zero 

2. Store A s © B $ in External Flip-Flop. 

3. If A s = 1, Complement Register 1. 

4. If B s = 1, Complement Register 2. 

5. Load Register 2 into ALU. 

6. Do Shift Left on ALU N Times 
(N = number of bits). 

7. Do N Times: 

( 1 ) 

a) If MSB of ALU = 1 

(Negative Indicator = High), 

Then shift ALU left 1 bit; 
add Register 1 to ALU. 


281 






CD4057AD, CD4057AK, CD4057AH 


File No. 635 


b) If MSB of ALU = 0 

(Negative Indicator = Low), 

Then shift ALU left 1 bit. 

8. If A s © B s = 1, then Complement ALU. 

9. Answer in ALU. 

Division Algorithm 




Dividend 



Two examples of how the conditional operation can be 
used are as follows: 

1) For the Multiplication Algorithm 


1. Store A s © B s in External Flip-Flop. 

2. If A s = 1 , complement ALU 1 and 
ALU 2. 

3. If B s = 1, complement Register A. 

4. Check for Divisor = 0 

a) If Divisor = 0; stop, indicates 
division by 0. 

b) If Divisor =£ 0; continue. 

5. Apply SUB instruction to ALU 1 
and Register A to ALU 1 data lines. 

a) If C Q = 0 (Dividend < Divisor), 
Stop, indicates overflow. 

b) If C Q = 1 (Dividend Divisor), 
Continue. 

6. Put a zero on RT. data line of ALU 
2 and shift ALU 1 & ALU 2 left 1 
bit. 

7. Do "N" times. 

Apply SUB instruction to ALU 1 
and Register A to ALU 1 data lines. 

a) If C 0 - 1, then clock ALU 1, and 
put a 1 on right data line of ALU 2. 

b) If C 0 = 0, then no clock, and put 
a 0 on right data line of ALU 2. 

8. If sign Flip Flop = 1, complement 
ALU 2. 

9. Answer in ALU 2. 


CONDITIONAL OPERATION 

Inhibition of the clock pulse can be accomplished with a 
programmed NO-OP instruction or through conditional input 
terminals A, B, and C. In a system of many CD4057A's, each 
CD4057A can be made to automatically control its own 
operation or the operation of any other CD4057A in the 
system in conjunction with the Overflow, Zero, or Negative 
(Number) indicators. Table II, the conditional-inputs truth 
table, defines the interactions among A, B, and C. 


A = 1, for step 7 (1) 

A = 0, for step 7 (2) 

B = 1 

C = negative Indicator 
2) For the Division Algorithm 
A = 1, for step 7 (1) 

A - 0, for step 7 (2) 

B = 1 

C = C D (left data line) 

OVERFLOW DETECTION 

The CD4057A is capable of detecting and indicating the 
presence or absence of an arithmetic two's-complement 
overflow. A two's-complement overflow is defined as having 
occurred if the signs of the two initial words are the same 
and the sign of the result is different while performing a 
carry-generating instruction. 

0.011 

For example: (+) 0.110 

1.001 

Overflows can be detected and indicated only during 
operation in Mode 2 or Mode 3 and can occur for only four 
instructions (AD, SMZ, SM, and SUB). If an overflow is 
detected and stored in the overflow flip-flop, any one of the 
five instructions AD, SMZ, SM, SUB, or IN can change the 
overflow indicator. 

When any of the three subtraction instructions is used, the 
sign bit of the data being subtracted is complemented and 
this value is used as one of the two initial signs to detect 
overflows. If an overflow has occurred, the final sign of the 
sum or difference is one's complemented and stored in the 
most-significant-bit position of the register. 

The overflow flip-flop is updated at the same time the new 
result is stored in the CD4057A. Whenever data on the 
parallel-data lines are loaded into the CD4057A, whatever is 
on the Overflow 1/0 line is loaded into the overflow flip-flop. 
Also, whenever data are dumped on the parallel data lines 
from the CD4057A, the contents of the overflow flip-flop are 
dumped on the Overflow 1/0 line. Thus overflows may be 
stored elsewhere and then fed into the CD4057A at another 
time. 


282 







File No. 635 


CD4057AD, CD4057AK, CD4057AH 


OPERATIONAL SEQUENCE AND WAVEFORMS FOR 

PROPAGATION-DELAY MEASUREMENTS 

1. DATA IN-to-CARRY OUT and DATA IN-to-SUM OUT 

A. Apply Word A and IN instruction 

B. Apply Clock to load word A into register 

C. Apply AD instruction 

D. Apply Word B (data in) 

E. Apply Clock to load result (sum out) 

F. Apply DATA OUT CONTROL to look at result 


A B C 0 E F 


I I I I I J 


0 DATA IN 
0 CARRY OUT 
0 SUM OUT 

0— *»0 DATA IN TO CARRY OUT 
0 -*■ 0 DATA IN TO SUM OUT 



2. CARRY IN-to-CARRY OUT and CARRY IN-to-SUM OUT 

A. Apply Word A and IN instruction 

B. Apply Clock to load word A into register 

C. Apply AD instruction 

D. Apply Word B 

E. Apply CARRY IN (carry in) 

F. Apply Clock to load result (sum out) 

G. Apply DATA OUT CONTROL to look at result 


A B C D E F G 

II I i I H 



0 CARRY IN 

« SOLID LINE REPRESENTS INPUT „ 

FROM EXTERIOR SOURCE WHEN (2 ) CARRY OUT 

t)ATA OUT* IS LOW. DASHED LINES ^ 

REPRESENT OUTPUT WHEN "DATA SUM OUT 

OUT“ IS HIGH 92CS-2I878 0— *-0CARRY IN TO CARRY OUT 


0 — ► 0 CARRY If 


• SOLID LINE REPRESENTS INPUT 
FROM EXTERIOR SOURCE WHEN 
‘OATA OUT" IS LOW. DASHED LINES 
REPRESENT OUTPUT WHEN "DATA 
OUT" IS HIGH 


Fig. 10(a) - DATA IN-to-CARRY OUT and DATA IN-to-SUM OUT. 


Fig. 10(b) - CARRY IN-to-CARRY OUT and CARRY IN-to-SUM OUT. 


AMBIENT TEMPERATURE (T A )=25°CP 
COUNT-UP MODE L 




iiiiiiiiiiiliiiiiKiiiii i 51888 

iSilljlllil! IlSilli 

iliilliiiliiiiiiiiliii iiiiiiii 


AMBIENT TEMPERATURE (T A )=25°C 
TYPICAL TEMP COEFFICIENT 
AT ALL VALUES OF VdD'0.3 7, 



MAX. COUNTING FREQUENCY (f M )— MHz 


LOAD CAPACITANCE (C L ) — pF 


Fig. 11 — Max. counting frequency vs. supply voltage 
for a typical CD4057A. 


Fig. 12 — Transition time vs. load capacitance for Data Outputs ( D1-D4 ). 



CD4057AD, CD4057AK, CD4057AH 


File No. 635 



Fig. 15— Data hold time. 


TEST CIRCUITS 



Fig. 16 — Noise immunity 

for "SET" instruction (see Timing Diagram) 

TYPICAL APPLICATION 



Fig. 17 — Quiescent device current. 


The CD4057A has been designed for use as a parallel pro- nal connections and data busing are primary design goals, 
cessor in flexible, programmable, easily expandable, special The block diagram of Fig. 18 is an example of a computer 
or general purpose computers, where minimization of exter- that processes 8 bits in parallel. 



Fig. 18 — Example of Computer Organization Using CD4057A. 


284 









nUQBZA] 

Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

Preliminary CD4059AD 


COS/MOS Programmable 
Divide-by-"N” Counter 


j2 — 4 21 — je Features: 

j3 — 5 20— J 7 o Synchronous programmable H N counter: 

J4 — e i9— Je N = 3 to 9999 or 15,999 

Jl6 — 7 la —j9 ■ 4 BCD decades of counting on one chip 

Jl5 — 8 17 J'o ■ Low power consumption: 30 /iW (typ.) at Vnn = 10 V 

JI4 — 9 16—JII _ . 

■ Presettable down counters 

JI3 — 10 15 — J 12 

Kc _„ ,4 — Ka ■ Fully static operation 

Vgs _ | 2 i 3 _ Kb ■ Mode select control of initial decade 

TOP view 92CS - 22212 R 1 counting function (Hi 0, 8, 5, 4, 2) 

TERMINAL DIAGRAM m T 2 L drive capability 

■ Master preset initialization 

■ Latchable H N output 

RCA Preliminary CD4059AD* is a divide-by-N down counter 

that can be programmed to divide an input frequency by any Applications. 

number "N" from 3 to 15,999. The output signal is a pulse B Communication set frequency 

one-clock-pulse wide occurring at a rate equal to the input VHF, UHF, FM, AM, etc. 

frequency divided by N. This single output has TTL drive ■ Fixed or programmable frequc 

capability. The down counter is preset by means of 16 jam a "Time out" timer for consume 


Applications: 

■ Communication set frequency synthesizers 

VHF, UHF, FM, AM, etc. 

■ Fixed or programmable frequency division 
n "Time out" timer for consumer application 

industrial controls 


PROGRAM JAM INPUTS (BCD) 


v ss <§>— 

V DD <§) — 


PRESETTABLE LOGIC 


FIRST 
COUNTING 
SECTION 
-HO. 8. 5. 4,2 


INTERMEDIATE COUNTING SECTION - 

H 10 M -HO PI 


LAST 
COUNTING 
SECTION 
HI .2 .2.4.8 


MODE I ^ 
SELECT \ Q3>- 
INPUTS 'T 


Fig. 1— Functional block diagram. 


9-74 


285 







Preliminary CD4059AD 


The three mode select inputs Ka, Kb, and Kc determine the 
modulus ("divide-by" number) of the first and last counting 
sections in accordance with the truth table shown in Table I. 
Every time the first (fastest) counting section goes through one 
cycle it reduces by 1 the number that has been preset (jammed) 
into the three decades of the intermediate counting section 
and into the last counting section, which consists of flip-flops 
that are not needed for operating the first counting section. 
For example, in the 2 mode only one flip-flop is needed in 
the first counting section. Therefore the last counting section 
has three flip-flops that can be preset to a maximum count of 
seven with a place value of thousands. If -MO is desired for the 
first section, set Ka = 1, Kb = 1, and Kc = 0; jam inputs J 1 , J2, 
J3, and J4 are used to preset the first counting section and there 
is no last counting section. The intermediate counting section 
consists of three cascaded BCD decade (-H0) counters pre- 
settable by means of jam inputs J5 through J16. 

The mode select inputs permit frequency synthesizer channel 
separations of 10, 12.5, 20, 25, or 50 parts. In addition, these 
inputs set the maximum value of N at 9999 (when the first 
counting section divides by 5 or 10) or 15,999 (when the first 
counting section divides by 8, 4, or 2). 

The three decades of the intermediate counting section can be 
preset to a binary 15 instead of a binary 9, while their place 
values are still 1, 10, 100, multiplied by the number of the -HM 
mode. For example, in the ^-8 mode, the number from which 
counting down begins can be preset to: 

3rd decade: 1500 

2nd decade: 150 

1st decade: 15 

Last counting section 1000 

2665x8 = 21,320 
plus the first counting section can be preset to 7 

Therefore 21,327 is the 
maximum possible count in the ^8 mode. 

The highest count of the various modes is shown in the 
column entitled: “extended" counter range, max., of Table I. 


Control inputs Kb and Kc can be used to initiate and lock the 
counter in the "master preset" state. In this condition the 
flip-flops in the counter are preset in accordance with the jam 
inputs and the counter remains in that state as long as Kb and 
Kc both remain low. The counter begins to count down from 
the preset state when a counting mode other than the master 
preset mode is selected. Whenever the master preset mode is 
used, control signals Kb = 0 and Kc = 0 must be applied for at 
least 3 full clock pulses. A "1" on the latch input will cause the 
counter output to remain "high" until the latch input returns 
to "0". If the latch input is "0" the output pulse will remain 
high for only 1 cycle of the clock-input signal. 

After the master preset mode inputs have been changed to one 
of the-J- modes, the next positive-going clock transition changes 
an internal flip-flop so that the countdown begins at the second 
positive-going clock transition. Thus, after an MP mode, there 
is always one extra count before the output goes high. See 
illustration below for total count of 3. (-f8 mode) 


CLOCK JUU 

uir 

-4. 

inmuuuu 

ruim 

muL 

INTERNAL STATE -HT| 
OF COUNTER 

OUTPUT -J ! 

a 

x; 

2 1^1 3 1 2 

mI 3 1 

_n 

2 

L 

l*-3 

J 

1 3l 

n 

1 2 

L 

1.3! 3 1 - 

_n_ 


92CS-2489I 


As illustrated in the sample applications, this device is partic- 
ularly advantageous in communication digital frequency syn- 
thesis (VHF, UHF, FM, AM, etc.) where programmable divide- 
by-"N" counters are an integral part of the synthesizer phase- 
locked-loop subsystem. Note that the Preliminary CD4059A 
can also be used to perform the synthesizer "Fixed Divide by 
R" counting function. For additional information, see RCA- 
ICAN-6716 "Low Power Digital Frequency Synthesizers 
Utilizing COS/MOS IC's." The Preliminary CD4059A can 
also be used in general-purpose counters for instrumentation 
functions such as totalizers, production counters, and "time 
out" timers. 

The Preliminary CD4059A is available in 24-lead ceramic dual- 
in-line packages. 


TABLE I 


MODE 



FIRST COUNTING 
SECTION 

LAST COUNTING 

SECTION 

DESIGN 

COUNTER 

RANGE 

m 

First 
counting 
section 
divides by: 



Kc 

Di- 

vides 

by: 

Can be 
preset 

to a 

maximum 

of: 

Jam 

inputs 

used: 

Di- 

vides 

by: 

Can be 
preset 

to a 

maximum 

of: 

Jam 

inputs 

used: 

Min. 

Max. 

Max. 

2 

1 

1 

1 

2 

1 

J1 

8 

7 

J2,J3,J4 

3 

15,999 

17,331 

4 

0 

1 

1 

4 

3 

J1,J2 

4 

3 

J3,J4 

3 

15,999 

18,663 

5 

1 

0 

1 

5 

4 

J1,J2,J3 

2 

1 

J4 

3 

9,999 

13,329 

8 

0 

0 

1 

8 

7 

J1,J2,J3 

2 

1 

J4 

3 

15,999 

21,327 

10 

1 

1 

0 


9 

J1,J2,J3,J4 

1 1 

0 

- 

3 

9,939 

16,659 

Master Preset 













(MP) 

X 

0 

0 


MP 



MP 


- 

- 



X = Don't Care 


286 



















Preliminary CD4059AD 


MAXIMUM RATINGS, Absolute-Maximum Values: 


Storage Temperature Range —65 to +150 °C 

Operating Temperature Range .... —55 to +125 °C 
DC Supply Voltage Range 

(Vdd-Vss) 15 V 

Device Dissipation (Per Pkg.) 200 mW 

All Inputs Vss^V|<Vdd 

Recommended DC Supply Voltage 

(Vqd-vss) 3 to 15 v 

Lead Temperature (During soldering) 

At distance 1/16 ± 1/32 inch 
(1.59 ± 0.79 mm) from case 

for 10 seconds max 265 °C 


STATIC ELECTRICAL CHARACTERISTICS AT Ta = 25°C 
Typical Temperature Coefficient at all values of VpD = — 0.3%/°C 


CHARACTERISTICS 

SYMBOL 

TEST 

CONDITIONS 

TYPICAL 

VALUES 

UNITS 

vo 

Volts 

VDD 

Volts 

Min. 

Typ. 

Max. 

Quiescent Device Current 

»L 


5 

- 

1 

_ 

M A 


10 

- 

3 

- 

Quiescent Device Dissipation/Package 

PD 


5 

_ 

5 

_ 

juW 


10 

- 

30 

- 

Output Drive Current : 
n-Channel (Sink) 

IdN 

0.4 

4.5 

1.3 

2.6 

_ 

mA 


10 

- 

12 

- 

p-Channel (Source) 

»dP 

4.1 

4.5 

_ 

-0.4 

_ 

mA 

9.5 

10 

- 

-1.5 

- 


DYNAMIC ELECTRICAL CHARACTERISTICS AT T A = 25°C and C L = 50 pF 
Typical Temperature Coefficient for all values of VpD = 0.3%/°C 


CHARACTERISTICS 

SYMBOL 

TEST 

CONDITIONS 

LIMITS 

UNITS 


VDD 

Volts 

Min. 

Typ. 

Max. 

Propagation Delay Time 


■ 

5 

_ 

280 

_ 

ns 

10 

- 


- 

Transition Time 



5 

_ 

35 

_ 

ns 

10 

- 

25 

- 

tTLH 


5 

- 

90 

- 

10 

_ 

50 

_ 

Clock Rise or Fall Time 

— 

■ 

5 

_ 

_ 

15 

MS 

10 

- 

- 

5 

Maximum Clock Frequency: 

All +Modes 

WEM 

■ 

5 

_ 

2.5 

- 

MHz 

10 

- 

5 

- 

Input Capacitance 

C| 

Any input 

- 

5 

- 

PF 


287 




























































Preliminary CD4059AD 


“HOW TO PRESET PRELIMINARY CD4059AD TO DESIRED +N" 


The value N is determined as follows: 

N = [MODE*] [1000 x Decade 5 Preset + 100X Decade 4 
Preset + 10X Decade 3 Preset + IX Decade 2 Preset ] + Decade 1 
Preset 

* MODE= First counting section divider (10, 8, 5, 4 or 2) 

To calculate preset values for any N count, divide the N count by the Mode. 

The resultant is the corresponding preset values of the 5th through 2nd 
decade with the remainder being equal to the 1st decade value. 


Preset Value = 


N_ 

Mode 


Examples: 

A) N = 8479, Mode = 5 

1695*^4^ Preset Values 

5 18479 
Mode *N 


( 1 ) 


( 2 ) 


MODE SELECT = 5 PROGRAM JAM INPUTS (BCD) 

4 1 5 9 6 

Ka Kb Kc J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 

101 0011 1010 1001 0110 

To verify the results use equation 1 : 

N = 5 (1000X 1 + 100 X6+ 10X 9+ 1 X 5) + 4 
N = 8479 

B) N = 12382, Mode = 8 
1547 + 6 
8 f 12382 

MODE SELECT = 8 PROGRAM JAM INPUTS 

6 1 7 4 5 

Ka Kb Kc J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 

001 0111 1110 0010 1010 

To verify: 

N = 8 (1000 X 1 + 100 X 5 + 10 X 4 + 1 X 7) + 6 
N = 12382 


C) N = 8479, Mode =10 
0847 + 9 
10 1 8479 

MODE SELECT = 10 PROGRAM JAM INPUTS 

9 7 4 8 

Ka Kb Kc J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 

110 1001 1110 0010 0001 
To Verify: 

N= 10(1000X 0+ 100X 8 + 10X4+ 1 X 7) + 9 
N = 8479 


288 



Preliminary CD4059AD 


APPLICATIONS 

1) DIGITAL PLL FOR FM BAND SYNTHESIZER 



2.56 MHz 


Calculating Min & Max "N" Values: 

Output Freq. Range (f 0 ) = 98.8 to 118.6 MHz 
Channel Spacing Freq. (f c ) = 200 kHz 
Division Factor (k) = 40 


Reference Freq. (fr) 


40 


* kHz= 5 kHz 



f|<Max. = 


118.6 MHz 
40 



98.8 MHz 

2.965 MHz; f k Min = — = 2.47 MHz 


118.6 MHz 

NMax ~ ~ 593 

Max 200 kHz 


98.8 MHz ^ 
N Min- 200 kHz 


2.56 MHz 

R=_ 5kH7 _=512 


2) -rN Counter Configuration for UHF — 220 to 400 MHz 

Channel Spacing: 50kHzor25kHz 



50/25 kHz 100 kHz 1MHz 10 MHz 100 MHz 


400 MHz 

NMax = rrm = 1 6 ,ooo 


NMin = ‘ 


25 kHz 

220 MHz 
25 kHz = 


400 MHz 

N Max = cn i,u, = 8,000 


= 8,800 


NMin =' 


50 kHz 

220 MHz 
50 kHz 


= 4,400 


3) -H\l Counter Configuration for VHF - 1 16 to 160 MHz 

Channel Spacing = 12.5 kHz 



12.5 kHz 


160 MHz .. 116 MHz 

NMax ' , OC |lj ~ 1 2,800 N|\/ijn - — ... _ 9,300 


12.5 kHz 


12.5 kHz 


289 




















Preliminary CD4059AD 


4)-H\l Counter Configuration for VHF — 30 to 80 MHz 

Channel Spacing: 25 kHz 



25 kHz 100 kHz 1MHz 10 MHz 


NMax _ 


80 MHz 
25 kHz 


= 3,200 


30 MHz 
NMin ~25kHz 


= 1200 


5)-rN Counter Configuration for AM — 995 to 2055 kHz 

Channel Spacing = 10 kHz 



10 kHz 100 kHz 1MHz 


NMax = 


2055 kHz 
10 kHz 


205 


NMin - 


995 kHz 
10 kHz 


290 







File No. 813 



Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4060A Type 



COS/MOS 14-Stage Ripple-Carry 
Binary Counter/Divider and Oscillator 


Features: 

■ 4-MHz operating frequency (typ.) at Vpp— V55 = 10 V 

■ Common reset 

■ Fully static operation 

■ 10 buffered outputs available 


The RCA-CD4060A consists of an oscillator section and 14 
ripple-carry binary counter stages. The oscillator configuration 
allows design of either RC or crystal oscillator circuits. A 
RESET input is provided which resets the counter to the all-O's 
state and disables the oscillator. A high level on the RESET 
line accomplishes the reset function. All counter stages are 
master-slave flip-flops. The state of the counter is advanced one 
step in binary order on the negative transition of 0j(0q). 
All inputs and outputs are fully buffered. 

The CD4060A is supplied in 16-lead dual-in-line welded-seal 
ceramic packages (D), plastic packages (E), ceramic packages 
(F), flat packs (K), and in chip form (H). 


MAXIMUM RATINGS, Absolute-Maximum Values: 


STORAGE-TEMPERATURE RANGE -65to+150°C 

OPERATING-TEMPERATURE RANGE: 

CERAMIC-PACKAGE TYPES -55to+125°C 

PLASTIC-PACKAGE TYPES -40 to +85 °C 

DC SUPPLY-VOLTAGE RANGE: 

<V DD“ V SS ) -0.5 to +15 V 

DEVICE DISSIPATION (PER PACKAGE) 200 mW 

ALL INPUTS V SS^ V I^ V DD 

LEAD TEMPERATURE (DURING SOLDERING): 

At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) 

from case for 10 seconds max 265 °C 

RECOMMENDED OPERATING CONDITIONS: 

DC Supply-Voltage Range 

(V dd -Vss> 3 to 15 V 

Input Voltage Swing v SS toV DD 


Oscillator Features: 

■ All active components on chip 

a RC or crystal oscillator configuration 

Applications: 

■ Timers 

■ Frequency dividers 


OSCILLATOR 



Fig. 1— Logic diagram of CD4060A oscillator, pulse shaper, 
and 1 of 14 counter stages. 


8-74 


291 







File No. 813 


CD4060A 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V SS <V,<V DD ) 

(Recommended DC Supply Voltage (VqD” ^SS> 3 to 15 V) 


STATIC ELECTRICAL CHARACTERISTICS (All inputs V SS <V,<V DD ) 

(Recommended DC Supply Voltage (Vpp— V5g) 3 to 15 V) 









CD4060AD 

CD4060AF 







TEST 



CD4060AK 

CD4060AH 




FIG 

CHARACTERISTIC 

SYMBOL 

CONDITIONS 



CERAMIC PACKAGE LIMITS 



UNITS 

NO. 




HR 

19 








■ 

i 





Rfl 

1221 


BBI 




Quiescent Device 

BB 

■ 

■ 

5 

- 

Q 

m 

- 

m 

■3 

- 

- 

900 

/iA 


Current 

m 

■ 

■ 

mum 

- 

- 

m 

- 

- 

m 

- 

- 

1500 


Quiescent Device 


■ 

■ 

5 

- 

- 

EM 

- 

KB 

E3 

- 

- 

mu 

pW 


Dissipation/Package 

P D 

■ 


m 

- 

- 


- 

10 


- 

- 

jjjjt 


Output Voltage: 

nu 


■ 

m 

- 

- 


- 

0 

0.01 

- 

- 



■ 

Low-Level 

hi 

1 

El 

- 

- 

ES 

- 

0 


- 

- 



Hi 

High-Level 

1 

PH 

■ 

5 


- 

- 

4.99 

5 

- 

4.95 

- 

- 

V 

H 

Eni 

l 

m 


- 

- 

9.99 

10 

- 

yu 

- 

- 


■ 

Noise Immunity 

(Any Input) 

Vnl 


m 

wm 

■a 

- 


1.5 


- 

mm 

- 

- 




D 

m 

3 

- 


3 

mm 

- 

wm 

- 

_ 


17,18 

Vnh 


ES 

D 

m 

- 

- 

1.5 

2.25 

- 

MEM 


- 

V 



9 

■£■ 

mi 

_ 

_ 

3 

4.5 

- 

3 


_ 



Output Drive Current : A 

IqN 


23 

D 


m 

- 

0.18 

0.36 

- 

0.125 

- 

- 


B 



IS 

O 

Q 

IB 

- 

323 

KEwX 

- 

EPS 

- 

- 



*D p 


EH 

m 

321 

B 

- 

3y^~ 

323 

- 


- 

- 


Qj 




m 

Q 

IB 

- 



- 

322 

- 

- 



Input Current 

'I 

Any Input 


e: 

- 

LZ_ 

BOB 

±1 

b: 

- 

- 




*Data does not apply to terminals 9 or 10. 



92CS-2I5IO 



Fig. 3— Typical n -channel drain characteristics. 


Fig. 4— Minimum n<hanne! drain characteristics. 


293 
















































CD4060A 


File No. 813 


STATIC ELECTRICAL CHARACTERISTICS (Allinputs V SS <V,<V DD ) 

(Recommended DC Supply Voltage (V DD -V SS ) 3 to 15 V) 


CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 

CD4060AE 

PLASTIC PACKAGE LIMITS 

UNITS 

FIG. 

NO. 




v 0 

V DD 

— 40°C 

25 °C 

85°C 






V 

V 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 



Quiescent Device 




5 

- 

- 

50 

- 

1 

50 

- 

_ 

700 

HA 

16 

Current 

'l 



0 

- 

- 

mu 

- 

2 

EQ3 

- 

- 

IEImI 

Quiescent Device 

Pm 



5 

- 

- 



5 


- 

- 

g 

pW 

■ 

Dissipation/Package 

r D 



KH 

- 

- 

im 

- 

Bl 

gSSSTSB 

- 



■ 

Output Voltage: 


Fan 

9 

El 

- 

- 


- 

0 

0.01 

- 

- 



■ 

Low-Level 


Out 

= 50 

1 

19 

- 

- 


- 

0 


- 

- 



1 



Fan 

g 

B 

4.99 

- 

- 


5 

- 



- 

V 

■ 

v OH 

Out 

= 50 

1 

H 

9.99 

- 

- 

! 

10 

- 



- 


■ 

1 



m 

m 

1.5 

- 


1.5 

2.25 

- 

s 

- 

- 


■ 

■ 

m 

El 

3 

- 

- 

3 

mm 

- 

m 

' - : 

- 


17,18 


■ 

m 

B 

Bl 

- 

- 

1.5 


- 

m 


- 



■ 

B 

na 

El 

- 

- 

3 

mm 

- 

EH 

- 

- 


■ 

Output Drive Current:* 



0.5 

» 

0.21 

- 

- 

0.18 

0.36 

- 

QQ 

- 




N-Channel (Sink) 

■d n 



B 


- 

- 


0.75 

- 

£1 

- 

- 

mA 

P-Channel (Source) 

i„p 


ES 

B 

Em 

- 

- 

ms 

-0.25 

- 

g§j 

- 

- 

mA 

□ 

«D r 


9.5 

10 

-0.29 

- 

~ 


-0.5 

- 

gg 

- 

- 

Input Current 

'l 

Any Input 

- 

- 

- 

- 

±10“ 5 

+i 

- 

- 

- 

M A 

- 


Data does not apply to terminals 9 or 10. 


DRAIN- T0-S0URCE VOLTAGE (V os )—V DRAIN- TO -SOURCE VOLTAGE (V DS )—V 




Fig. 5— Typical p-channel drain characteristics. Fig. 6— Minimum p-channel drain characteristics. 


294 

























File No. 813 CD4060A 


DYNAMIC ELECTRICAL CHARACTERISTICS AT T A = 25°C, C L = 15 pF (unless otherwise specified), Input t r ,t f = 20 ns 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

CERAMIC TYPES 

PLASTIC TYPES 

UNITS 

FIG. 


V DD 

MIN. 

TYP. 

MAX. 

MIN. 

TYP. 

MAX. 

NO. 

Input-Pulse Operation j 

Propagation Delay 

l PHL» 


5 

- 

900 


- 




m 

Time to Q4 Out 

*PLH 



- 

450 

sm 

- 


g 


B 

Propagation Delay 

X PHU 


5 

- 

450 


- 


103 

ns 


Time, Q n to Q n +i 

X PLH 



- 

225 

450 

- 

ggyi 

475 

Transition Time 

msm 


5 

- 



- 

KE9 




— 



- 

75 


- 

mm 





f = 100 kHz 

5 

- 

200 

jy 

- 

gg 



9 


10 

- 

75 

yjyjl 

- 

mm 


■ 

Input-Pulse 

1 


5 

- 

- 

15 

- 

- 

■a 

D 

B 

Rise & Fall Time 




- 

- 

mm 

- 

- 

El 

fl 

Max. Input-Pulse 



5 

1 


- 

um 

jgrjj 

- 

MHz 

10 

Frequency 


10 

3 

4 

- 


4 

- 

Input Capacitance 

h 


- 

5 

- 

- 

5 

- 

mm 



Propagation Delay 

*PHL 



- 

500 

1000 

- 


1250 

M 

■ 

Time 


10 

- 



- 

HI 


1 

B 




5 

- 


1000 

- 

gjj 

991 

B 

B 



10 

- 


500 

- 



B 




Fig. 7— Typical propagation delay time vs. load Fig. 8— Typical propagation delay time vs. 

capacitance faj to Q4 output). load capacitance (Q p to Q p + j). 


295 















































File No. 813 


CD4060A 


TEST PERFORMED 
WITH UNIT IN ALL 
"O's" STATE AND 
ALL "I's" STATE 
AND INPUTS AT 10 V 
AND GROUND 


10 V 



Fig. 16— Quiescent device current test circuit. 



Fig. 17— Input-pulse noise immunity test circuit. 




92CS-23767 


Fig. 18— Reset-pulse noise immunity test circuit. Fig. 20— Input pulse-shaping circuit (Schmitt-Trigger) for CD4060A. 



TYPICAL COMPONENT VALUES AND CIRCUIT PERFORMANCE® 


OSCILLATOR 

Rs 

Rt 

c T 

lQQmA@ 

FREQUENCY 

KJi 

Kft 

V DD = 10V 

10 Hz 

450 

45 

IpF 

0.3 

100 Hz 

450 

45 

0.1 pF 

0.3 

1000 Hz 

450 

45 

0.01 pF 

0.4 

10 KHz 

450 

45 

0.001 pF 

0.5 

100 KHz 

450 

45 

100 pF 

0.7 

1 MHz 

45 

4.5 

100 pF 

1 


® See Application Note ICAN-6267 Astable and Monostable Oscillator 
Using RCA COS/MOS Digital Integrated Circuits. 


Fig. 19-Typica! RC oscillator circuit. 


* 0 PIN 9 



92CS-23768RI 

Fig. 21 —Input circuit characteristics for circuit in Fig. 20. 


^""cDAOGOA 











File No. 768 


QUQgZi] Digital Integrated Circuits 

Solid State Monolithic Silicon 

Division CD4061AD 

CD4061AH 



COS/MOS 256-Word by 1-Bit 
Static Random-Access Memory 

Features: 

■ Low standby power: 10 Nanowatts/bit (typ.) @ Vqq = 10 V 

■ Access time: 380 ns (max.) @ V DD = 10 V ■ Noise immunity: 45% of V DD (typ.) 

■ Single 3-to-15 V power supply ■ Fully decoded addressing 

■ COS/MOS input/output logic compatibility ■ Single write/read control line 

■ TTL output drive capability 

■ Three-state data outputs for bus-oriented systems 

■ 11 01 -type pin designations* 

■ Separate data output and data input lines 


RCA-CD4061A is a single monolithic integrated circuit con- 
taining a 256-word by 1-bit fully static, random-access, NDRO 
memory. The memory is fully decoded and requires 8 address 
input lines (Ao — A7) to select one of 256 storage locations. 
Additional connections are provided for a WRITE/READ 
comma nd CHIP ENABLE, DATA IN, and DATA OUT and 
DATA OUT lines. 

To perform READ and WRITE operations the CHIP-ENABLE 
signal must be low. When the CHIP-ENABLE signal is high, 
read and write operations are inhibited and the output is a high 
impedance. To change addresses, the CHIP-ENABLE signal 
must be returned to a high level, regardless of the logic level of 
the WR ITE/R EAD input. In a multiple package application, the 
CHIP-ENABLE signal may be used to permit the selection of 
individual packages. 

Output-voltage levels appear on the outputs only when the 
CHIP-ENABLE and WRITE/READ signals are both low. 
Separate data inputs and outputs are provided; they may be 
tied together, or, to eliminate interaction between READ and 
WRITE functions, may be used separately. The circuit ar- 
rangement permits the outputs from many arrays to be tied to 
a common bus. 


All input and output lines are buffered. The CD4061 A output 
buffers are capable of direct interfacing with TTL devices. 

The CD4061A is available in a hermetically sealed 16-lead 
dual-in-line ceramic package (CD4061AD) or in chip form 
(CD4061AH). 


MAXIMUM RATINGS, Absolute-Maximum Values: 


STORAGE-TEMPERATURE RANGE -65 to +150 °C 

OPERATING-TEMPERATURE RANGE -55 to +125 °C 

DC SUPPLY-VOLTAGE RANGE 

(V DD -V ss ) -0.5 to +15 V 

DEVICE DISSIPATION (PER PKG.) 200 mW 

ALLINPUTS Vss<V|<V D d 

RECOMMENDED DC SUPPLY VOLTAGE 

< V DD- V SS> 3 to 15 V 

LEAD TEMPERATURE (DURING SOLDERING) 

At distance 1/16 ±1/32 inch (1 .59 ±0.79 mm) 

from case for 1 0 seconds max 265 °C 


*The pin designations are compatible with other static 256-Bit memories and are, therefore, not compatible with standard COS/MOS 
CD4000A-series devices; i.e. Vqq is pin 5 and Vgs is pin 4. 


298 


7-74 






File No. 768, 


CD4061AD, CD4061AH 




FOR SINGLE 


AND p DEVICES 


[all p-SUBSTRATES TIED TO Vdd. 
/ALL n-SUBSTRATES TIED TO V ss . 


Fig. 1 - CD4061A logic diagram. 


CD4061A OPERATIONAL MODES 


OPERATION 

ADDRESS LINES 

CHIP-ENABLE 

WRITE/READ 

DATA IN 

DATA OUTPUTS 

Write ."0" 

Stable 

0 

1 

0 

High-Impedance 

Write "1" 

Stable 

0 

1 

1 

High-Impedance 

Read 

Stable 

0 

0 

X 

Valid 1 or 0 

♦Read/Write 

Stable 

0 

0/1 

X 

Valid 1 or 0/High- 
lmpedance 

Address Change 

Changing 

1 

X 

X 

High-Impedance 


X = Don't Care 

* For a READ/WRITE operation on the same address, chip-enable may be held to a logic 0 for both successive 
operations. 


299 

















CD4061AD, CD4061AH File No. 768 


STATIC ELECTRICAL CHARACTERISTICS (All inputs Vss < V, < V DD ) 

(Recommended DC Supply Voltage (Vp^ — V«js) 3 to 15 V) 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

LIMITS 

UNITS 

CHARAC- 

TERISTIC 

CURVES 

8. TEST 

CIRCUITS 

Fig. No. 


v o 

Volts 

V DD 

Volts 

-55 °C 

25°C 

125°C 


EQJj 


mu 

EQ 





Quiescent Device 

Current 

m 



5 

_ 

_ 

5 

_ 


m 

_ 

_ 


PA 

14 

10 

- 

- 

■Q 

- 

E3 

m 

- 

- 

EH 

Quiescent Device 

Dissipation/Package 

D 



5 

- 

- 

- 


B 

m 

~ 


ESI 

jtiW 

- 

10 

- 

- 

- 

- 

E9 

eq 

- 

- 


Output Voltage 

Low-Level 

o 

> 



5 

- 

_ 


_ 

0 


- 

_ 

QS3 

■ 

- 

ma 

- 

- 


- 

0 

Uj 

- 

- 

Cjgi 

High-Level 

X 

o 

> 



5 

WH1 

- 

- 

BE 

5 

- 

ft 

- 

- 

■ 

- 

10 

E 

- 

- 


sm 

- 


- 

- 

Noise Immunity 
(All Inputs) 

V NL 

1 

0.8 

5 

C3 

_ 

_ 

B3 

Ba 

- 

ra 

_ 

_ 

■ 

17 

1 

10 

3 

- 

- 

3 

e m 

- 

EB 

- 

- 

v N h 

1 

nm 

5 

m 

- 

- 

Da 

WHS 1 

- 

m 

_ 

_ ■ 

■ 

17 

9 

mm 

& 

- 

- 

Bi 

■a 

- 

3 

- 

- 

Output Drive Current: 
(Data Out, Data Out) 

N-Channel (Sink) 

i d n 

1 

■ 

H 

■ 

■ 

■ 

■ 

■ 

B 

n 

B 

■ 

mA 

3, 4,12 



mm 


- 

- 

EJ 

5 

- 

D 

- 

- 

P-Channel (Source) 

'd p 


nm 

5 

BB 

- 

- 


na 

- 

iBHSi 

_ 

_ 

mA 

5. 6. 13 


4.6 

5 

EH 

- 

- 

EZX 

eh 

- 


- 

- 


mm 

10 

SB 

- 

- 

m 

BB 

- 

B3SI 

- 

- 

Output Off Resistance 
(High -Impedance State) 

R o (0ff) 

' 


5 

BB 

n 

- 

m 

- 

- 

m 

- 

- 

Mfi 

- 

10 

sm 

m 

- 

m 

- 

- 

mm 

“ 

- 


300 
































File No. 768 


CD4061AD, CD4061AH 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, V ss = 0 V, C L = 50 pF, and t r , t f = 20 ns 










CHARAC- 









TERISTIC 


CHARACTERISTICS 

SYMBOLS 

TEST CONDITIONS 


LIMITS 


UNITS 

CURVES 

& TEST 





V DD 





CIRCUITS 





(Volts) 

Min.* 

Typ. 

Max.* 


Fig. No. 


Read Cycle Time 



5 

1200 

1000 

- 

ns 



l RC 


10 

550 

450 

- 



Chip-Enable Hold Time 



5 

40 

0 

- 

ns 


UJ 

T CEH 


10 

0 

- 

- 


o 

>- 

Chip-Enable Pulse Width 



5 

700 

500 

- 

ns 


o 

t CE 


10 

350 

250 

- 


< 

UJ 

cc 

Chip-Enable Setup Time 



5 

460 

- 

- 

ns 



^ES 


10 

200 

- 

- 



Read Access Time 

*RA 


5 

- 

450 

750 


2. 9, 10 





10 

- 

250 

380 



Write Cycle Time 



5 

1200 

1000 

- 




*WC 


10 

550 

450 

- 




Chip-Enable Hold Time 

*CEH 


5 

40 

0 

_ 





10 

0 

- 

- 




Chip-Enable Pulse Width 



5 

700 

500 

_ 




*CE 


10 

350 

250 

- 



UJ 

Chip-Enable Setup Time 

^ES 


5 

460 

- 

- 



o 

> 


10 

200 

- 

- 



o 

UJ 

Write Hold Time 

*WH 


5 

150 

100 

- 

ns 

2 

E 


10 

100 

70 

~ 



£ 

Write Pulse Width 

t W 


5 

150 

100 

- 





10 

100 

70 

- 




Data Setup Time 

*DS 


5 

140 

80 

- 





10T 

80 

35 

- 




Data Hold Time 



5 

25 

10 

- 




*DH 


10 

20 

10 

- 





l TLH 


5 

- 

60 

100 




Output Transition Time 


10 

- 

50 

75 

ns 






5 

- 

35 

60 


8 



*THL 


10 

- 

25 

40 



Chip-Enable 

^CE. 


5 

- 

- 

15 




Input Rise and 



10 

- 

- 

5 

/us 



Fall Time 

*fCE 


15 

- ■ 

- 

1 




* See "Symbol Definitions" 


301 



CD4061AD, CD4061AH 


File No. 768 


a) READ-CYCLE WAVEFORMS 

M J 


w/r*logic"o h data in* don't care 


•X 




l— ' ceh-^L 




* If * 20 ns 




y 


b) WRITE-CYCLE waveforms 



SYMBOL DEFINITIONS 
READ CYCLE 

tRc — READ CYCLE TIME — Time required between address 
changes during a read cycle. Minimum read cycle time is equal 
to tQEH (min.) + *CE (min.) + tcES (min.). (See Definitions 
below). 

tCEH ” CHIP-ENABLE HOLD TIME - Time required before 
chip-enable level can be lowered after an address transition. 

t CE - CHIP-ENABLE PULSE WIDTH - Time required for the 
chip to be active for valid reading of output data. 
t CES “ CHIP-ENABLE SETUP TIME - Time required before 
ar address transition can tak^place after chip-enable level has 
been increased. tcES( min *) + t CEH( m ‘ n *) ' s the minimum time 
required to discharge internal nodes and allow settling of ad- 
dress decoders during an address transition. Chip-enable level 
must be raised during each address change, even if read cycles 
only or write cycles only are successively performed. However, 
if address is not changed, chip enable may remain in its active 
(low) state during successive read and write cycles. 

tRA - READ ACCESS TIME - Measured from chip-enable 
transition; time before output data is valid. 

WRITE CYCLE 

twc “ WRITE CYCLE TIME — Time required between ad- 
dress changes during a write cycle. This time sets the maximum 


operating frequency for the memory, with minimum write 
cycle time equal to tp E n (min.) + tp E (min.) + tQES (min.). 

t C £H “ CHIP-ENABLE HOLD TIME - See Definition under 
read cycle. 

t CE - CHIP-ENABLE PULSE WIDTH - See Definition under 
read cycle. 

t CES - CHIP-ENABLE SETUP TIME - See Definition under 
read read cycle. 

twH “ WRITE HOLD TIME — Measured from chip-enable 
transition; time required before negative transition of write 
pulse can occur for successful write operation. 
t w - WRITE PULSE WIDTH - Time required for W/R pulse to 
be high. Note that no specification for positive transition of 
this pulse is made — it may occur before or after the chip- 
enable transition. In many applications, the W/R control is 
normally low and is strobed high during a write cycle. 

t DS — DATA SETUP TIME — Measured from write-pulse 
negative transition; time required for data input to be valid. 

tpn — DATA HOLD TIME — Measured from write-pulse 
negative transition; time required for data input to be valid 
after W/R is returned to a low level. The minimum data pulse 
width is equal to tQS (min.) + tp^ (min.). 


302 




LOAD CAPACITANCE (C L ) — pF 


LOAD CAPACITANCE (C L )~ pF 


Fig. 7 — Typical low-to-high transition time (t-rt u) vs C t . 


Fig. 8 — Typical high-to-low transition time (t 







CD4061AD, CD4061AH 


File No. 768 



Fig. 9 — Typical read access time (t^ A i vs C[_- 



LOAD CAPACITANCE <Ci )*50 dF 

T4 




TT 


TT 








44 

44 

44 

44 

44 

44 

44 

44 

44 

3 

H 





H 








■ 

iai 

iai 



5 

iai 

IBI 

■Si 

a 

IBI 



IBI 


vi 





c 





in 

IBI 




IBI 

IBI 

■■1 

a 


IBI 

■ Bl 
















Tl 

TT 

a 

IBI 

IT 

















IBI 

■ai 

a 

in'- 


j** 

TT 

TT 















IBI 

■si 

IV 



IBI 

IBI 

IBI 















JJ 

9^ 



TT 

TT 

IBI 






K 

400 

(O 

2 300 











50 

■ 

Bl 

IT 

II 

IBI 

IBI 














4 


a 

i 

Bl 

a 

B 

IBI 

IBI 














-i 

£ 


B 

j 

Sj 

B 

a 

4* 

u 














IBI 

B 

IBI 

B 

i 

Bl 

a 

B 

B 

Bl 

•s: 







w. 

ui 

■ 





B 

»! 

B 

i 

n 

n 




■Bl 








■! 

■ 





41 

t4 

s 

i 

■Bl 

IB! 

IBI 






o 

o 

«I 





■i 

Sj 

■ 

s 





iai 

is; 

SB* 

ill 

jjj 

j|| 

■B 

;s 

mi 

S! 

Ij 



i 

B 

SI 

iai 




o 200 
< 

UJ 

on 

100 





mi 

i 

5 

■ 



i 




a 

a 

a 

Ml 

IBI 

IBI 

IB 

IB 

Bl 

Bl 

Si 

s 


5 









■ 

■ 







B 

IBI 

IB 

s: 



u 









■ 

■ 

a 







B 

IBI 

IB 

Bl 



IBI 

IBI 







a 

■ 

■ 

a 

a 







a 

a 

a 

a 

a 

a 

a 

a 





-75 -50 -25 0 25 50 75 100 125 


AMBIENT TEMPERATURE (T A ) °C 

92CS-2386I 

Fig. 10 — Typical read access time vs temperature. 


TEST CIRCUITS 



Fig. 11 — Typical power dissipation vs cycle time. with the exception of tQ^ = 400 ns. 


10 V 

Q 



Quiescent Device Current Test Conditions 


92CS-23865 


Test 

A 

B 

Memory Cells 

1 

0 

0 

All 0 

2 

1 

1 

All 0 

3 

0 

1 

All 0 

4 

0 

0 

All 1 

5 

1 

1 

All 1 

6 

0 

1 

All 1 




6 II — | 

7 10 — 1 

8 9 | — 1 


10 V 

Q 


Fig. 14 — Quiescent device current. 


Fig. 15 — Operating life. 



92CS-23867 

Fig. 16 - Bias life. 


Description of Test: 

Functional test run with random 
data input. All inputs toggle be* 
tweem 30% and 70% of Vqq. 

I— A6 

| A5 92CS-23868 

Fig. 17 — Noise immunity. 

Note: Connection to all terminals in Figs. 15 & 16 (except 4 and 5) are made through 47 kSl resistors. 


304 









File No. 816 



Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4062AK 

CD4062AT 

CD4062AH 


j 

200 DYNAMIC 

r 

RC — 
REC — ►- 

STAGES 

— 0 


1 \ H 


CM 1 

CL — 

CLOCK 

I ► CLid 

CM “H 

GENERATOR 

► CL2D 





92CS— 24664 

CD4062A Functional Diagram 


COS/MOS 200-Stage Dynamic 
Shift Register 


Special Features: 

■ Operation from a single 3-V to 15-V positive or 
negative power supply 

■ Minimum shift rates over full temperature range — 

Single phase clock: 3 V< Vqq < 10 V; f m j n = 10 kHz; 
— 55°C < T a < +125°C (f mjn = 1 kHz up to T A < 75°C) 

Two-phase clock: 3V< V DD < 15 V; f min = 10 kHz; 

— 55°C < T A <+125°C (f min = 1 kHz up to T A < 75°C) 


The RCA-CD4062A is a 200-stage dynamic shift register with 
provision for either single- or two-phase clock input signals. 
Single-phase-clocked operation is intended for low-power, low 
clock-line capacitance requirements. Single-phase clocking is 
specified for medium-speed operation (< 1 MHz) at supply 
voltages up to 10 volts. Clock input capacitance is extremely 
low (< 5 pF), and clock rise and fall times are non-critical. The 
clock-mode signal (CM) must be low for single-phase operation. 

Two-phase clock-input signals may be used for high-speed 
operation (up to 5 MHz) or to further reduce clock rise and 
fall time requirements at low speeds. Two-phase operation 
is specified for supply voltages up to 15 volts. Clock input 
capacitance is only 50 pF/phase. The clock-mode signal (CM) 
must be high for two-phase operation. The single-phase-clock 
input has an internal pull-down device which is activated 
when CM is high and may be left unconnected in two-phase 
operation. 

The logic level present at the data input is transferred into the 
first stage and shifted one stage at each positive-going clock 
transition for single-phase operation, and at the positive-going 
transition of CL-| for two-phase operation. 

The CD4062A is supplied in a 16-lead flat pack (K), a 12-lead 
TO-5 style package (T), and in chip form (H). 


a Low power dissipation 

0.3 mW/bit at 1 MHz and 10 V 
0.04 mW/bit at 0.5 MHz and 5 V 
(alternating 1-0 data pattern) 

□ Data output TTL-DTL compatible 
a Recirculating capability 
a Delayed two-phase clock outputs available 
for cascading registers 

a Asynchronous ripple-type presettable to all I's or 0's 
a Ultra-low-power-dissipation standby operation 

Applications: 
a Serial shift registers 
a Time-delay circuits 
a CRT refresh memory 
a Long serial memory 


MAXIMUM RATINGS, Absolute-Maximum Values: 


STORAGE-TEMPERATURE RANGE -65 to +150°C 

OPERATING-TEMPERATURE RANGE -55 to +125°C 

DC SUPPLY-VOLTAGE RANGE (V DD -V SS ) -0.5 to +15 V 

DEVICE DISSIPATION (PER PACKAGE) 200 mW 

ALL INPUTS Vss^V^Vqq 

LEAD TEMPERATURE (DURING SOLDERING): 

AT DISTANCE 1/16 ± 1/32 IN. (1.59 ± 0.79 MM) 

FROM CASE FOR 10 S MAX 265°C 


RECOMMENDED OPERATING CONDITIONS 

DC SUPPLY VOLTAGE (Vq^V^): SI NGLE-PH ASE CLOCK 

3 to 10 V 

TWO-PHASE CLOCK 

3 to 15 V 

INPUT VOLT AGE SWING V DD to V ss 


8-74 


305 






CD4062A 


File No. 816 



•terminal numbers in 

PARENTHESES REFER TO 
12-LEAD TO -5 STYLE 
PACKAGE 




* 

Vss 


(a) A BIDIRECTIONAL LOW IMPEDANCE WHEN CONTROL INPUT 
IS "LOW" AND CONTROL INPUT 2 IS "HIGH" 

(b) AN OPEN CIRCUIT WHEN CONTROL INPUT I IS "HIGH" AND 
CONTROL INPUT 2 IS "LOW" 

CL (a) = INTERNAL CLOCK IN PHASE WITH CL| 

CL (b)» INTERNAL CLOCK IN PHASE WITH CL 2 

92 CM - 2 2695RI 


Fig. 1-CD4062A logic block diagram. 



r\_ 


r 






S\ 


"V 

_r\ 

92CM - 22700RI 


fv 
r 


v 


Fig. 2— Clock circuit logic diagram. 


306 












File No. ai6 


CD4062A 


STATIC ELECTRICAL CHARACTERISTICS, All Inputs V ss < V, <V DD 

Recommended DC Supply Voltage (Vq£)— V§ s) 3 to 15 V 


CHARACTERISTIC 



TEST CONDITIONS 


< o' 

V DD 

V 

CM=High 


5 

CL^High 

CL2=Low 


10 


Output Voltage: 
Low-Level 


Noise Immunity 
(Any Input) 


Output Drive Current: 
N-Channel 
(Sink) 


P-Channel 

(Source) 


Input Current 


CM=High 

CL-|=High 

CL2=Low 



Any Input 



Maximum power dissipation rating ^ 200 mW. 


•h r tr i r 


DELAYED 200 CLOCK PULSES / 

X = DATA SET-UP TIME -\ U-tpLH tPHL-J L 

HIGH TO LOW 
Y=DATA HOLD TIME 
Z=DATA SET-UP TIME 
LOW TO HIGH 

92CS-22702 

Fig. 3— Timing diagram— single-phase dock. 


/I |\io% 

H|— 



Q DELAYED 200 CLOCK PULSES , 
MIN t w (CL|), t w (CL 2 ) = 20ns 


Fig. 4— Timing diagram— two-phase dock. 







































CD4062A 


File No. 816 


DYNAMIC CHARACTERISTICS AT T A = 25°C, V ss = 0 V, C L = 50 pF, Input t r ,tf = 20 ns, except ^CL and t f CL 
Single-Phase-Clock Operation; Clock Mode (CM) = Low; 3 V < Vqq < 10 V (See Figure 3) 


CHARACTERISTIC 


Maximum Clock Frequency 
(50% Duty Cycle) 


Minimum Clock Frequency 
(50% Duty Cycle) 


Clock Rise and Fall Times** 


Average Input Capacitance 

All Inputs Except CL-j and CL 2 
Propagation Delays : 

CL to Q 

CL to CL 1 0 (Positive Going) 


CL to CL 2 D (Positive Going) 


CL to CL 10 (Negative Going) 


TEST CONDITIONS 


V DD 

V MIN. TYP. MAX. 


f CL I t r ? tf=20 ns I 5 I 0.5 | 1 



If more than one unit is cascaded in single-phase parallel clocked application, t r CL should be made less than or equal to the sum of the 
propagation delay at 15 pF, and the transition time of the output driving stage. (See Figs. 5 and 7 for cascading options.) 

Use of delayed clock permits high-speed logic to precede CD4062A register (see cascade register operation). 


308 


































File No. 816 CD4062A 


Two-Phase Clock Operation (CL-j, CL2); Clock Mode (CM) = High; 3 V< Vpp < 15 V. See Figure 4. 


CHARACTERISTIC 

SYMBOL 

TEST CONDI' 

NONS 

V DD 

V 

LIMITS 

UNITS 

FIG. 

NO. 

MIN. 

TYP. 

MAX. 

Maximum Clock Frequency 

f CL 


5 

1.25 


- 

MHz 

- 


mm 

5 

- 

Minimum Clock Frequency 

f CL 


5 

150 

10 

- 

Hz 

- 

10 

mjn 

10 

- 

Clock Overlap Tirr 
S0%y 

CL 2 / 

10% 

CL-j 

td 1 

le 

/ 10% \ 

= ^-so% 

td 2 




40 

- 

- 

ns 


Average Input Capacitance 

CL 1# CL 2 

C| 



- 

50 

- 

pF 

B 

Propagation Delays 

CL-j to Q 

tPHL' 

*PLH 


5 

- 

jg3?m 

Ei9 

ns 

1 

mm 

- 

100 

JESM 

CL-j to CL-jq 

CL 2 to CL 2 p 

5 

- 

250 

u 

10 

- 

100 



— 


*SU 


5 

300 

150 



ns 

1 


10 

100 

50 




a 


^OLD 


5 

■ 

■ 

■ 

ns 

1 



10 

0 

- 


Clock Rise and Fall Times 

t r CL ^ , CL 2 

tfOL. 1 v d_2 


No Restrictions If 

Clock Overlap Require- 
ment Is Met 


CASCADED REGISTER OPERATION 



FEATURES: 

■ Low clock capacitance — 5 pF/package 

■ Medium-speed operation ~ 1 MHz @ 10 V 

■ Stringent clock rise and fall times required 


Fig. 5-Singie-phase docking (CM » GND). 





92CS-22696 

Fig. 6— Two-phase docking. 


FEATURES: 

■ High-speed operation ~ 5 MHz @ V DD « 10 V 

■ No clock rise and fall time requirements if clock 
overlap specification is met 

■ Clock input capacitance only 50 pF/phase/package 


309 
























































CD4062A 


File No. 816 


CASCADED REGISTER OPERATION (CONT'D) 


a) SINGLE PHASE CLOCK INPUT (LOW SPEED) 



FEATURES: 

■ 5 pF clock capacitance 

■ Low speed— delayed clock introduces ~ 200 ns 
delay per cascaded package @ 10 V 

■ Non-stringent clock rise and fall times (delayed 

clock prevents race conditions when cascading registers) 


b) SINGLE- PHASE - CLOCK INPUT (MEDIUM SPEED) 


*3 

CL 2 D 

M r 

CM! cl 24 

v DDi 

cm] 

j*CL 2D 

F CL 2, r 

V DD4 

cm| 

^ CL go " 

1 CL 2v 

*3 

j“ CL 2D 


CD4062A 


CD4062A 

H 

CD4062A 

H 

CD4062A 

H 

CD4062A 

L 

6 


5 

J L 

4 

J L 

2 

j i 

I 




CLOCK RE- PHASING 


FEATURES: 

■ 5 pF clock capacitance 

■ Medium speed— two-phase delayed clocks add only 
70 ns delay per cascaded package. Data must be re- 
phased (as shown) every five packages at 10 V. (10 
packages at 5 V) 

■ Non-stringent clock rise and fall times 


C) TWO - PHASE - CLOCK INPUT (HIGHER SPEED) 



FEATURES: 

■ Low clock capacitance ~ 50 pF/phase 

■ Higher speed than single-phase delayed clocking 
Clock overlap required equals (40 + 20 x N) ns 
N = number of cascaded registers 


92CS- 22699 

Fig. 7— Use of delayed-clock outputs. 


OPEN CIRCUIT FOR SINGLE-PHASE OPERATION 
CL2 WAVEFORM FOR TWO-PHASE OPERATION 



OPEN CIRCUIT FOR SINGLE -PHASE OPERATION 
CL| WAVEFORM FOR TWO-PHASE OPERATION 

92CS-22692RI 


FEATURES: 

■ Ripple- type set/reset to all I's/O's 

■ Ultra-low standby power dissipation 


Fig. 8— Asynchronous set/reset and standby. 



92CS-Z269Q 


FEATURES: 

■ 64 stage static register delayed clock compatible 
with single-phase clock input on CD4062A 

■ CL-j p delayed clock output on CD4062A compatible 
with other COS/MOS registers 


Fig. 9— Compatibility with other COS/MOS registers /logic. 



92CS-22698 


FEATURES: 

■ Single TTL supply level 

■ "Race''-Free: High speed TTL driving 
medium speed COS/MOS 


Fig. 10— Compatibility with TTL/DTL systems. 


310 


















File No. 816 


CD4062A 


SIMPLE TWO-PHASE CLOCK GENERATOR CIRCUITS FOR DRIVING CD4062A 




REQUIRED: 

1 QUAD 2 NAND OR TRIPLE 3 NAND 
(SN5400/7400 OR (SN5410/7410) 

1 HEX INVERTER (SN5404/7404) 


92CM- 2 2697 

td.j AND td 2 « 40 ns WITH THIS CIRCUIT 

tdT AND td 2 MAY BE ADJUSTED BY 
ADDING MORE INVERTER DELAYS OR 
CAPACITIVELY LOADING POINTS a AND b. 


Fig. 11— TTL— 5-volt levels (only 2-gate packages required). 



REQUIRED: td AND td 2 MAY BE ADJUSTED BY ADDING 

1 CD4001A— QUAD 2 INPUT NOR GATE MORE INVERTER DELAYS OR CAPACITIVELY 

1 CD4050A— HEX BUFFER (NON-INVERTING) LOADING a AND b. 


Fig. 12-COS/MOS—3-15 volt levels (only 2-gate packages required). 


< 

£ 

l 

o 

H 

H 

AMBIENT TEMPERATURE (Ta)*25°C 

TYPICAL TEMPERATURE COEFFICIENT IS -0.3%/°C 
AT ALL VALUES OF Vqs 




- 





_ 





__ 





_ 




_ 








_ 


- 










i 




H 

i 




i 





::: 














II 





i 





::: 






























- 

Ui 










: 





: 





:r~ 





a: 100 

3 

O 

z 

< 75 
oc 

Q 

£ 50 

z 

< 

! 25 








-- 



- 




- 

— 




— 







E 

_ 


200 mW) 

_ 

_ 










^ PKG. DISSIPATION 

- 


— 




— 






:3 



_lj 





“h 


JJ 



1 


_ 


















:r 


;£ 



£ 



44- 

gat 

( 

E -1 

vgs 







E 


4 J 

GF 









i: 


II 



£ 



)*'5V t 


~_z 






II 


I 


10 

V- 



i~t~ 

zt: 



__ 

T 








:: 




i 


4 








:: : 

i: 



:: 

E 







rr 




- 




- 


_L 





+ ; 




E 











±5VI 





1 

- 



" 

+ - 




1 







- 

£ 



3= 

=i= 

44 

__ 





__ 







. 

I 







1 

*- 

- 


±t±±d 

-- 


-- 



■ 





-- 


-- 

j- 

-- 






0 5 10 15 

DR AIN -TO- SOURCE VOLTAGE (Vds> — V 

92CS-23854 


Fig. 13— Typical n-channel drain characteristics for Q output. 


DRAIN-TO-SOURCE VOLTS IV DS ) 



Fig. 14— Typical p-channel drain characteristics for Q output. 


311 



CD4062A 


File No. 816 



NOTE: t THL FOR Q OUTPUT IS SIGNIFICANTLY LESS THAN t TLH 


300 

f 

AMBIENT TEMPERATURE IT A ) = 25"C 
TYPICAL TEMPERATURE COEFFICENT FOI 
ALL VALUES OF V DD *0.3%/°C 






































T 

5 

T 

T 

IT 

TT 

II 

T 




















ft 


T 

ft 

ft 

ft 

T 


















SL 

p 

>LY 

V 

OL 

TS 

(V 

DD 

)* E 


























jE 200 

s 

1- 

z 

o 

t 100 













:e 













































































































- 1C 





















; - 





■15 









z 

2 

i- 






































I _ 






























































































0 20 30 40 50 60 70 80 90 100 


LOAD CAPACITANCE lC L l-pF 


Fig. 15— Typical transition time vs. C[_ for data outputs. 


Fig. 16— Typical transition time vs. Cj_ for delayed dock output. 



92CS- 24666 


Fig. 17— Typical power dissipation vs. frequency. 



92CS-24667 


Fig. 18— Minimum shift frequency vs. ambient temperature. 


TEST CIRCUITS 


10 v 



Fig. 19— Quiescent device current. Fig. 20— Noise immunity. 


In single-phase clock mode inputs CLj and Cl_2 should be 
left unconnected. 

In two-phase clock mode 1 -phase clock input may be 
left unconnected because an internal pulldown device 
is provided. 


312 







File No. 805 



Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4063B Types 


WORD 
fA>B — 


— A>B 

cascading! a=b _ 


— A=B 

inputs 


— A<B 

WORD ad> 




92CS- 

24516 

CD4063B Functional Diagram 


COS/MOS 4-Bit Magnitude Comparator 


Features: 

■ Standard B-series output drive 

■ Expansion to 8, 16 ... 4N bits by cascading units 

■ Medium-speed operation: compares two 4-bit words in 250 ns (typ.) at 10 V 

Applications: 

® Servo motor controls 
o Process controllers 


The RCA-CD4063B is a low-power 4-bit magnitude comparator 
designed for use in computer and logic applications that 
require the comparison of two 4-bit words. This logic circuit 
determines whether one 4-bit word (Binary or BCD) is "less 
than", "equal to", or greater than" a second 4-bit word. 

The CD4063B has eight comparing inputs (A3, B3, through 
AO, BO), three outputs (A < B, A = B, A > B) and three cas- 
cading inputs (A < B, A = B, A > B) that permit systems 
designers to expand the comparator function to 8, 12, 16 . . .4N 
bits. When a single CD4063B is used, the cascading inputs are 
connected as follows: (A < B) = low, (A = B) = high, (A > B) = 
low. 


For words longer than 4 bits, CD4063B devices may be cas- 
caded by connecting the outputs of the less-significant com- 
parator to the corresponding cascading inputs of the more- 
significant comparator. Cascading inputs (A < B, A = B, and 
A > B) on the least significant comparator are connected to a 
low, a high, and a low level, respectively. 

All outputs have equal source- and sink-current capabilities and 
conform to standard B-series output drive (see Static Elec- 
trical Characteristics). 

The CD4063B is supplied in 16-lead dual-in-line welded-seal 
ceramic packages (D), plastic packages (E), ceramic packages 
(F), flat packs (K), and in chip form (H). 


TRUTH TABLE 


1 INPUTS | 

OUTPUTS 

| COMPARING 

CASCADING 

A3, B3 

A2, B2 

A1, B1 

> 

o 

00 

o 

A < B 

00 

ii 

< 

A > B 

A < B 

A = B 

A > B 

A3 > B3 

X 

X 

X 

X 

X 

X 

0 

0 

1 

A3 = B3 

A2> B2 

X 

X 

X 

X 

X 

0 

0 

1 

A3 = B3 

A2 = B2 

A1 >B1 

X 

X 

X 

X 

0 

0 

1 

> 

CO 

n 

CD 

CO 

A2 = B2 

> 

n 

03 

AO > BO 

X 

X 

X 

0 

0 

1 

I A3 = B3 

CM 

CO 

II 

CM 

< 

A1 = B1 

> 

o 

ii 

00 

o 

0 

0 

1 

0 

0 

1 

CO 

CO 

II 

CO 

< 

A2 = B2 

> 

ii 

00 

> 

o 

II 

00 

o 

0 

1 

0 

0 

1 

0 

CO 

00 

II 

CO 

< 

A2 = B2 

A1 = B1 

> 

o 

00 

o 

1 

0 

0 

1 

0 

0 

A3 = B3 

A2 = B2 

> 

ii 

00 

A0< B0 

X 

X 

X 

1 

0 

0 

A3 = B3 

A2 = B2 

A1 <B1 

X 

X 

X 

X 

1 

0 

0 

> 

CO 

II 

00 

CO 

A2< B2 

X 

X 

X 

X 

X 

1 

0 

0 

A3 < B3 

X 

X 

X 

X 

X 

X 

1 

0 

0 


X = Don't Care 1= High State 0 = Low State 


8-74 


313 






CD4063B 


File No. 805 


STATIC ELECTRICAL CHARACTERISTICS 


CHARAC- 

TERISTIC 

SYMBOL 

TEST 

CONDI- 

TIONS 

CD4063BD, BK, BF, BH 

CERAMIC PACKAGE LIMITS 

UNITS 

FIG. 

NO. 

v 0 

Volts 

VDD 

Volts 

-^5°C 

25°C 

125°C 


PH 


na 

Typ. 



i ns 

233 

Quiescent Device 

Current 

D 

■ 

5 

_ 

- 

5 

_ 

WMM 

5 

- 

_ 

EB 

/uA 

12 

mm 

- 

- 

mm 

- 

wssm 

mm 

- 

- 


wm 

- 

- 


- 

BOB 


- 

- 


Output Voltage 
Low-Level 

VOL 

■ 

5 

- 

- 

roi 


0 

BTtTi 

- 

- 


V 

1 

mm 

- 

- 

ebb 


El 


- 

- 

EES 

mm 

- 

- 

- 

- 

0 

- 

- 

- 

- 

High-Level 

VOH 

■ 

mm 

BUB 

- 

- 

ii%i 

5 

- 

EE9 

- 

- 

10 

EEEI 

- 

- 


10 

- 

EESI 

- 

- 

mm 

- 

- 

- 

- 

15 

- 

- 

- 

- 

Noise Immunity 

vnl 


5 

mm 

- 

- 

mm 

B3B 

- 

mm 


- 

V 

13 


mm 

3 

- 

- 

3 

4.5 

- 

mm 

- 

- 

MEM 

mm 

- 

- 

- 

- 

mu 

- 

- 

- 

- 

vnh 

ga 

5 

sn 

- 

- 

m 

WEM 

- 

is 

- 

- 


tm 

KO 

- 

- 

3 

mm 

- 

3 

- 

- 

HQ 

mm 

iz: 

- 

- 

- 

msuM 

- 

- 

- 

- 

Output Drive 
Current: 

N-Channel 

(Sink) 

IdN 

0.4 

H 


■ 

■ 

0.4 

m 

■ 

0.3 

■ 

■ 

mA 

■ 

iiH 

mm 

mm 

- 

- 

0.9 

mm 

- 

Mtizm 

■■ 

- 

mim 

mm 

-j 

- 

- 

mm 

6 

- 

- 

- 

- 

P-Channel 

(Source) 


mm 

mm 

BQ 

- 

- 

m 

WSWM 

- 

IBS 

~ 

- 


5.6 

KOI 



- 

- 

E3EI 


- 


B 

- 

ese 

■a 

b n 

- 

- 


-1.8 

- 


B 

- 

BLUE 

mm 

- 

- 

- 

mm 

-6 

- 


- 

- 

Input Current 

'I 


■a 

- 

- 

- 

- 


a 

| 

- 

- 

//A 

- 


MAXIMUM RATINGS, Absolute-Maximum Values: 


STORAGE-TEMPERATURE RANGE -65 to +150°C 

OPERATING-TEMPERATURE RANGE: 

CERAMIC-PACKAGE TYPES -55 to +125°C 

PLASTIC-PACKAGE TYPES -40 to +85 °C 

DC SUPPLY- VOLT AGE RANGE 

V DD * -0.5 to +18 V 

DEVICE DISSIPATION (PER PACKAGE) 200 mW 

LEAD TEMPERATURE (DURING SOLDERING): 

At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) 

from case for 10 seconds max 265 °C 


* All voltage values are referenced to Vgg terminal. 


OPERATING CONDITIONS AT T A 25°C 


For maximum reliability, nominal operating conditions should be 
selected so that operation is always within the following ranges. 


Characteristic 

V DD 

Min. 

Max. 

Units 

Fig. 

Supply Voltage Range 

- 

3 

18 

V 

- 

Input Voltage Swing 
(Recommended V 55 to Vp D ) 


0 2 V DD 
to 

0.8 V DD 
(Any one 
input) 

-0.5 V 

to 

V DD + 
0.5 V 

V 

! 



314 







































File No. 805 


CD4063B 


STATIC ELECTRICAL CHARACTERISTICS 


CHARAC- 

TERISTIC 


Noise Immunity 


Output Drive 
Current: 

N-Channel 

(Sink) 


P-Channel 

(Source) 


Input Current 




■ mm\ 



IBB5SISESES3BESSB2SKSS^HjSCH9i 


1 15151 1 


iriTiTij 


■■■■ 




DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Input t r , tf = 20 ns, and C L = 50 pF 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

ALL TYPES 
LIMITS 

UNITS 

CHARACTERISTIC 

CURVES & 





TEST CIRCUITS 








FIG. NO. 

Propagation Delay Time: 

tPHL' 

*PLH 


5 

■ 




Comparing Inputs to 







Outputs 




M 

ns 

7,8 

Cascading Inputs to 

tPHL' 

X PLH 


5 

10 

500 

200 

1000 

400 

Outputs 


15 

140 

- 




*THL 


5 

100 

200 



Transition Time 



10 

50 

100 

ns 



l TLH 


15 

40 

80 



Average Input Capacitance 

C, 

Any Input 

5 

- 

PF 



315 




























































PROPAGATION DELAY TIME (tp H L,tp L H > 









TRANSITION TIME (t 


liETti 










File No. 769 




Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4066AD CD4066AE 
CD4066AK CD4066AH 



COS/MOS Quad Bilateral Switch 

For Transmission or Multiplexing of Analog or Digital Signals 
Applications: 

■ Analog signal switching/multiplexing 
Signal gating 
Squelch control 
Chopper 

■ Digital signal switching/Multiplexing 

■ Transmission-gate logic implementation 

■ Analog-to-digital & digital-to-analog conversion 

■ Digital control of frequency, impedance, phase, and 
analog-signal gain 


Modulator 
Demodulator 
Commutating switch 


RCA-CD4066A is a quad bilateral switch intended for the 
transmission or multiplexing of analog or digital signals. It 
is pin-for-pin compatible with RCA-CD4016A, but exhibits 
a much lower ON resistance. In addition, the ON resistance 
is relatively constant over the full input-signal range. 

The CD4066A consists of four independent bilateral switches. 
A single control signal is required per switch. Both the p and 
the n device in a given switch are biased ON or OFF simul- 
taneously by the control signal. As shown in Fig. 1 , the well of 
the n-channel device on each switch is either tied to the input 
when the switch is ON or to V$s when the switch is OFF. 
This configuration minimizes the variation of the switch- 
transistor threshold voltage with input signal, and thus keeps 
the ON resistance low over the fujl operating-signal range. 

The advantages over single-channel switches include peak 
input-signal voltage swings equal to the full supply voltage, 
and more constant ON impedance over the input-signal range. 
For sample-and-hold applications, however, the CD4016A 
is recommended. 


SWITCH 



Fig. 1 - Schematic diagram of 1 of 4 identical switches and its 
associated control circuitry. 


The CD4066A is supplied in a 14-lead dual-in-line ceramic 
package (CD4066AD), in a 14-lead dual-in-line plastic package 
(CD4066AE), or in a 14-lead ceramic flat pack (CD4066AK). 
It is also available in chip form (CD4066AH). 


Special Features: 

■ 15-V digital or ± 7.5-V peak-to-peak switching 

■ 80-£2 typical ON resistance for 15-V operation 

■ Switch ON resistance matched to within 5 £2 over 15-V 
signal-input range 

■ ON resistance flat over full peak-to-peak signal range 

■ High ON/OFF output-voltage ratio: 65 dB typ. 

@fj s = 10 kHz, R|_= 10 k£2 

■ High degree of linearity: < 0.5% distortion typ.@fj s =1 kHz, 
Vis = 5 Vp.p, V D D“VSS> 10 V, R L = 10 k£2 

■ Extremely low OFF switch leakage resulting in very low 
offset current and high effective OFF resistance: 

10 pA typ. @ Vqd-Vss = 10 V, T A = 25°C 

■ Extremely high control input impedance (control circuit 
isolated from signal circuit): 1012 £2 typ. 

n Low crosstalk between switches: 

-50 dB typ. @ fj s = 0.9 MHz, Rl = 1 k£2 

■ Matched control-input to signal-output capacitance: 
Reduces output signal transients 

■ Frequency response, switch ON = 40 MHz (typ.) 


7-74 


319 





CD4066AD, CD4066AE, CD4066AK, CD4066AH File No. 769 

ELECTRICAL CHARACTERISTICS (All inputs Vss<V|<Vdd) 

(Recommended DC Supply Voltage (Vdd — • • • • • • 3 to 15 V) 


ELECTRICAL CHARACTERISTICS (All inputs Vss<V|<Vdd) 

(Recommended DC Supply Voltage (Vdd — • • • • • • 3 to 15 V) 








LIMITS 

H 

CHARACTERISTIC 

SYMBOL 




CD4066AD, CD4066AK 






jMxan 


■ESEfl 

UNITS 







Bsai 

EH 

Esai 

^231 

BQ 


■1 

Quiescent Dissipation 
per Package 

All Switches OFF 

1 

VOLTS 

TERMINALS APPLIED 

Vdo 14 +10 

Vgs 7 GND 

V c 5.6,12,13 GND 

V is 1,4,8,11 <+10 

V os 2,3,9,10 <+10 

- 

i 

0.1 

i 

i 

300 

pW 

All Switches ON 


TERMINALS 

Vdd 14 

V S S 7 

V C 5,6.12,13 

v is = v os 1.4,8.11 

VOLTS 

APPLIED 

+ 10 

GND 

+ 10 

<10 (Thru 

^ 10 100U) 


i 

0.1 

i 

i 

300 

pW 

| SIGNAL INPUTS (V js ) AND OUTPUTS (V os ) 




V C =V DD 

WEM 

HEBH 











+7.5 V 

-7.5 V 



220 


I 


320 





+15 V 

0 V 


80 


ON Resistance 

r on 

R l = 10kO 

+5 V 


-5 V 

to 

+5 V 


400 


500 

190 

550 

n 




+ 10 V 

0 V 

0 to 
+10 V 







+2.5 V 

-2.5 V 

-2.5 V 
to 

+2.5 V 



270 

5000 







+5 V 

0 V 

0 to 
+5 V 











+7.5 to -7.5 

■ 


H 


m 

H 


AON Resistance 

Between Any 2 
of 4 Switches 

ARqn 

R|_ = 10 kO 




m 

■ 

■ 

■ 

m 

■ 

o 



+5V to— 5V 



10 


m 

■ 







+10 VtoO V 




■ 

Hi 


Sine Wave Response 
(Distortion) 



1 


5 V(p-p) A 

■ 

■ 

D 


- 

- 

B 

Input or Output 

Leakage— Switch OFF 
(Effective OFF 

Resistance) 

II 

V DD 

+7.5 V 

Vc = Vss 

-7.5 V 

v is 
±7.5 V 

■ 



BSP1 

■ 




+5 V 

-5 V 


±5 V 



IE23B 



±200* 


Frequency Response- 
Switch ON 
(Sine Wave Input) 

■ 

R|_ = 1 kH 

V C =V DD = +5V V ss = —5 V 

V 

20 Log ■) 0 = " 3dB 

1 

B 

40 

■ 

1 

■ 

MHz 

Feedthrough 

Switch OFF 

■ 

Vj s =5 V (p-p) 

v D d = +5 v. v c = v S s = -5 v 

20Log 10 ^= -50 dB 

1 

1 

1.25 

■ 

1 

■ 

H 

Crosstalk Between any 2 
of the 4 switches 

(Frequency at —50 dB 

■ 

r l = i ko 
v is (A) = 

5 V (p-p) 

v c (A) = v D d = + 5 v 

V C (B) = V SS = -5 V 

V os (B) Rn , R 

20 Logio V^AT = 

1 

1 

0.9 

1 

1 

1 

MHz 

Capacitance Input 

CIS 

V DD = +5 V. V C = V SS = 

-5 V 



■ 

H 

■ 

fl 



Output 

Cos 






R 

R 

1 

H 

R 

PF 

Feedthrough 

C|OS 





■ 

■ 


■ 

■ 

E 

■ 

Propagation Delay 

Signal Input to 

Signal Output 

*Pd 

Vc = vqd = +io v. v S s = gnd, c l = i 5 pF 

v is = 10 V (square wave) 
t r = tf = 20 ns (input signal) 

i 


fl 

■ 

i 

■ 

fl 


320 



































































File No. 769 


CD4066AD, CD4066AE, CD4066AK, CD4066AH 


ELECTRICAL CHARACTERISTICS (All inputs V SS < v l < V DD[ 

(Recommended DC Supply Voltage (Vdd~Vss) 3 to 15 V) 



CHARACTERISTIC SYMBOL 


Control (Vc) 

I I I v DD -v ss = iu v 

Noise Immunity | V NL | | l i5 = 10|iA 


Input Current 


Average Input Capacitance 


Crosstalk 
Control Input to 
Signal Output 


Propagation Delays 


Maximum Allowable 
Control Input 
Repetition Rate 


* Limit determined by minimum feasible leakage measurement for automatic testing. 
A Symmetrical about 0 volts. 



CHARACTERISTIC SYMBOL 


Quiescent Dissipation 
per Package 
All Switches OFF 


TEST CONDITIONS 



VOLTS 


TERMINALS 

APPLIED 

VDD 

14 

+ 10 

VSS 

7 

GND 

Vc 

5,6,12,13 

GND 

v is 

1,4,8,11 

<+ 10 

Vos 

2,3,9,10 

<+ 10 



VOLTS 


TERMINALS 

APPLIED 

VDD 

14 

+ 10 

VSS 

7 

GND 

Vc 

5,6,12,13 

+ 10 

Vjs = V 0 < 

; 1.4,8.11 

+ 10 <TKru 
^ 10 100 SI) 


B Minimum value for all temperatures shown is 2 V. 


LIMITS 


CD4066AE 



AON Resistance 
Between Any 2 
of 4 Switches 











































































CD4066AD, CD4066AE, CD4066AK, CD4066AH 


File No. 769 







LIMITS 

I 

CHARACTERISTIC 



TC r 


CD4066AE 





— 40°C 

25 ° c 

85°C 






ESS 

Max. 

Typ. 


Typ. 


HI 

Input or Output 

Leakage— Switch OFF 
(Effective OFF 

Resistance) 


V DD 

+ 7.5 V 


v c = v ss v ls 

-7.5 V ±7.5 V 

■ 

* 

±100 

+0.1 



±200 

n 


+5 V 


-5 V ±5 V 

- 

BEliP 

gf | 


- 



Frequency Response- 
Switch ON 
(Sine Wave Input) 


R l = 1 kS2 

v C 

= Vqd = +5V V SS =-5V 

V 

20 Log 1 = “ 3dB 

1 

- 

40 

■ 

1 



Feedthrough 

Switch OFF 

■ 

V is -5 V (p-p) 

v D d = +5 v. v c = v ss = -5 v 

20 Logio"^^ = - 5 °dB 

1 

- 

1.25 

■ 

1 

■ 

■ 

Crosstalk Between any 2 
of the 4 switches 

(Frequency at —50 dB 


R L = 1 KS7 

V is IA) = 

5 V (p-p) 

V C (A) = V DD = +5 V 

V C (B> = V SS = -5 V 

20 Logio v'js(A)' = ~ 5 ° dB 


i 

B 

l 

1 

1 

MHz 

Capacitance Input 

CIS 

V DD = +5V. V C = 

Vss = -5 v 

H 

■ 


H 

B 

B 


Output 

c OS 









■ 

PF 

Feedthrough 

U3SM 




B 



■ 


fl 


Propagation Delay 

Signal Input to 

Signal Output 

l pd 

V C = Vqd = +10 V. V SS = GND, Cl = 15 pF 

Vj s = 10 V (square wave) 
t r = tf = 20 ns (input signal) 

- 

- 

10 

- 

- 

- 

ns 

| Control (Vc> 

Noise Immunity * 

VNL 

v is < v DD 

vdd-vss= i° v 

l, s = 10 pA 

- 

- 

B 

- 

- 

- 

V 

Input Current 

n 

Vdd-vss = io v 

Vc^ Vqd-vss 

■ 

■ 


- 

- 

- 

pA 

Average Input Capacitance 

c c 


- 

- 

6 

- 

- 

- 

pF 

Crosstalk 

Control Input to 

Signal Output 


Vdd-Vss =10V 

V C = 10 V 
(square wave) 

r l = io k n 

■ 

■ 


- 


H 

mV 

Propagation Delays 

tpdC 

Vc = *fc = 20 ns 

r l = 30on 
V is < 10 V, C L = 15 pF 

- 

- 


- 

■ 

■ 

ns 

Maximum Allowable 

Control Input 

Repetition Rate 

■ 


1 

_ 

10 


1 

B 

B 


! Limit determined by minimum feasible leakage measurement for automatic testing. ■ Mjnjmum va , ue for a| , temperatur es shown is 2 V. 
Symmetrical about 0 volts. 


MAXIMUM RATINGS, Absolute-Maximum Values: 


STORAGE TEMPERATURE RANGE .... -65°C to +1 50°C 
OPERATING TEMPERATURE RANGE: 

Ceramic Packages — 55°C to +125°C 

Plastic Packages — 40°C to +85°C 

DISSIPATION PER PACKAGE 200 mW 

DC SUPPLY VOLTAGES: 

V DD“ V SS; V DD~ V EE -0.5 to +1 5 V 

ALLSIGNAL AND DIGITAL CONTROL INPUTS . V SS <V, <V DD 
MINIMUM RECOMMENDED POWER SUPPLY VOLTAGES 

V DD~ V SS; V DD _V EE 3V 

LEAD TEMPERATURE (DURING SOLDERING): 

At distance 1/16 ± 1 /32 inch (1 .59 ± 0.79 mm) 
from case for 10 seconds max 265°C 


SPECIAL CONSIDERATIONS - CD4066A 

1. In applications where separate power sources are used to 
drive Vdd and the signal inputs, the Vdd current cap- 
ability should exceed Vdd/ r L ( r L = effective external 
load of the 4 CD4066A bilateral switches). This provision 
avoids any permanent current flow or clamp action on the 
N/qd supply when power is applied or removed from 
CD4066A. 

2. In certain applications, the external load-resistor current 
may include both Vdd and signal-line components. To 
avoid drawing Vdd current when switch current flows 
into terminals 1, 4, 8, or 11, the voltage drop across the 
bidirectional switch must not exceed 0.8 volt (calculated 
from Ron values shown). 

No Vdd current will flow through Rl if the switch current 
flows into terminals 2, 3, 9, or 10. Failure to observe this 
condition may result in distortion of the signal. 


322 

























CD4066AD, CD4066AE, CD4066AK, CD4066AH 


File No. 769 



Fig. 2 (a) — Typical channel ON resistance vs. signal voltage for 
three values of supply voltage (Vqq—Vss)- 


350 

2 

SUPPLY VOLTAG 

V DD- V SS>*5V 

—r 





7 



riTTXTLl 11 
emperaturb: 

: P 





- 


AMBIENT T 








-.A 









o 300 




g 










:± 







£: 


1 























o 250 














;4 









tr 























z 200 























W 























g '50 























z 

O 














-5! 

5°C 








-j 























2 

z 























< 50 

X 














































0 
























-8 -6 -4 -2 O 2 4 6 8 

SIGNAL VOLTAGE (Vj. s ) - VOLTS 

92CS-239I4 


Fig.2 (b) — Typical channel ON resistance vs. signal voltage 
with supply voltage (Vqq—V^sI - 5 V. 



Fig.2 (c) — Typical channel ON resistance vs. signal voltage 
with supply voltage (Vqq—Vss) = 10 V. 



92CS-239I6 

Fig.2 (d) - Typical channel ON resistance vs. signal voltage 
with supply voltage (Vqq—VssI = 15 v - 



H.P. 

MOSELEY 

7030A 


92CS-227I6 



-2 0 2 
INPUT SIGNAL VOLTAGE (V ls )— VOLTS 


Fig. 3 - Channel ON resistance measurement circuit. 


Fig.4 — Typical ON characteristics for 1 of 4 channels. 







Mb 


CD4066AD, CD4066AE, CD4066AK, CD4066AH 


File No. 769 


TEST CIRCUITS 



92CS-239I8 


Fig. 5 — Capacitance. 



V C* V SS V DD 



Vss — 
ALL UNUSED TERMINALS 
ARE CONNECTED TO V S s. 


92CS-239 19 

Fig. 6 — OFF switch input or output leakage 



ALL UNUSED TERMINALS 
ARE CONNECTED TO V S S- 


92CS-2392I 

Fig. 8 — Crosstalk-control input to signal output. 



Fig.9 — Propagation delay tpi_n, tpHL. control-signal output. 



K> 2 4 6 8 I0 2 2 4 ®»7o 3 

SWITCHING FREQUENCY (f)— kHx 

92CS-23924 


ALL UNUSED INPUTS ARE CONNECTED TO Vss- 
92CS- 23923 

Fig. 10 — Maximum allowable control input repetition rate. 



92CS-2I6I4 


Fig. 11 - Power dissipation per package vs switching frequency. 


Fig. 12 — Bidirectional signal transmission via digital control logic. 


324 












File No. 769 


CD4066AD, CD4066AE, CD4066AK, CD4066AH 



triggering the counter at receiver end only. Hence signal amplitudes 
must be less than 30% of Vqq — Vgs to avoid erroneous counting or 
inhibit at CD4018A and CD4049A, respectively. 

Fig. 13 — 4-channel PAM multiplex system diagram. 


325 






Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

Preliminary CD4067BD 
Preliminary CD4097BD 


Preliminary Data* 


x>U 


I OF 16 DECODER 


• o-So. 


i O- 




V 


, OUT/ IN 

f-o 


15 0 




COS/MOS 

Analog Multiplexers/Demultiplexers 

CD4067B-Single 16-Channel Multiplexer/Demultiplexer 
CD4097B— Differential 8-Channel Multiplexer/Demultiplexer 


92CS- 24924 

CD 4067 B Functional Diagram 


The RCA-CD4067B and -CD4097B COS/MOS analog multi- 
plexers/demultiplexers* are digitally controlled analog switches 
having low "on" impedance, low "off" leakage current, and 
internal address decoding. In addition, the "on" resistance is 
relatively constant over the full input-signal range. The 
CD4067B is a 16-channel multiplexer with four binary control 
inputs. A, B, C, D, and an inhibit input, arranged so that any 
combination of the inputs selects one switch. A logic "1" 
present at the inhibit input turns all channels off. 

The CD4097B is a differential 8-channel multiplexer having 
three binary control inputs A, B, C, and an inhibit input. 
The inputs permit selection of one of eight pairs of switches. 

The CD4067B, CD4097B are supplied in a 24-lead dual-in-line 
welded-seal ceramic package. (CD4067BD, CD4097BD). 

•When the devices are used as demultiplexers, the in/out terminals 
are the outputs and the common out/in terminal (s) is(are) the 
input(s). 



MAXIMUM RATINGS, Absolute-Maximum Values: 

STORAGE-TEMPERATURE RANGE -66 to +150°C 

OPERATING-TEMPERATURE RANGE -55 to +125 °C 

DC SUPPLY-VOLTAGE RANGE 

V DD * -0.5 to +18 V 

DEVICE DISSIPATION (PER PACKAGE) 200 mW 

ALL INPUTS V ss < V, < V DD 

LEAD TEMPERATURE (DURING SOLDERING): 

At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) 

from case for 10 seconds max 266 °C 

* All voltage values are referenced to V SS terminal. 

OPERATING CONDITIONS AT T A = 25°C 

For maximum reliability, nominal operating conditions should be 
selected so that operation is always within the following ranges. 


Characteristic 

O 

O 

> 

Min. 

Max. 

Units 

Fig. 

Supply Voltage Range 

- 

3 

18 

V 

- 

Input Voltage Swing 
(Recommended Vgg to Vqq) 


0.2 V DD 
to 

0.8 V DD 
(Any one 
input) 

-0.5 V 

to 

V DD + 
0.5 V 

V 

~ 

Signal Input Current 


- 

25 

mA 


Output Load Resistance 

- 

100 

- 

a 

- 


— ^ I Y CHAN. 


CD4067B 


TERMINAL ASSIGNMENTS 



92CS-24979 


326 


9-74 









Preliminary CD4067B, CD4097B 


ELECTRICAL CHARACTERISTICS at T A = 25°C 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

TYPICAL 

VALUES 

UNITS 


V DD (V) 

v ss (v) 

Quiescent Device Current 

'L 


5 

0 

0.1 

pA 

10 

0 

0.2 

15 

0 

0.5 

SIGNAL INPUTS (V js ) AND OUTPUTS (V os ) j 

"ON" Resistance 

(Peak for V ss <V is <V DD ) 

r ON 

R l = lOkft 

(Any 

Channel 

Selected) 

+7.5 

-7.5 

140 

n 

+15 

0 

+5 

-5 

200 

+ 10 

0 

+2.5 

-2.5 

400 

+5 

0 

A "ON" Resistance 

Between Any 2 Channels 

ar on 

+7.5 

-7.5 

5 

+15 T 0 

+5 ■ -5 

10 

+10 

0 

Sine Wave Distortion 


R L = 10 k£l 
f is = 1 kHz 

5 V (p-p) A 

+7.5 

-7.5 

0.1 

% 

+5 

-5 

0.2 

+2.5 

-2.5 

2 

"OFF" Ar, y Channel OFF 



+5 

-5 

±0.2 

nA 

Leakage All Channels CD4067B 


Inhibit = +5 V 

+5 

-5 

±3.2 

Current OFF (Output) CD4097B 

+5 

-5 

±1.6 

Frequency Response- 
Channel "ON" 

(Sine Wave Input) 


R L = 1 k£2 

V js = 5 V (p-p) 

C L = lOpF 

V C = V DD = +5 V, 

V SS = -5V 

V os 

20 Log-jQ = —3 dB 

V is 

40 

MHz 

Feedthrough 

Channel "OFF" 


V DD = +5 V, 

V C = V S S = -5V 

Vos 

20 Login —40 dB 

v is 

1 

MHz 

Crosstalk Between Any 2 
of the 1 6 Switches 
(Frequency at —40 dB) 


R L = 1 kft 

Vj s (A) = 

5 V (p-p) 

C L = lOpF 

V C (A) = V DD = +5 V 

V C (B)=V SS = -5 V 

V os (B) 

20 Log-in = — 40 dB 

V is (A) 

1 

MHz 

Input 

C IS 


+5 | -5 

5 

pF 

Output 

CaPa ° i,anCe (Common OUT/IN) 

c os 



CD4067B 

60 

CD4097B 

30 

Feedthrough 

c IOS 



0.2 

Propagation Delay: 

Signal Input to Signal Output 

tPLH' 

*PHL 


v c = v DD = +iov, 

V S S = Vjnh=0V, 

C L = 50 pF 

Vj s = 10 V (square wave) 
t r* t f = 20 ns (input signal) 

30 

ns 


A Symmetrical about 0 volts. 


327 






Preliminary CD4067B, CD4097B 


ELECTRICAL CHARACTERISTICS (Cont'd) 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

TYPICAL 

VALUES 

UNITS 


Vpo-Vss (V) 

CONTROL (V c ) INPUTS A, B, C, D AND Inhibit | 

Noise Immunity 

Vnl, 

Vnh 

l is = 10/iA 

R L = 1 kft 

V is = V DD 

through 

1 k ft 

15 

6.75 

V 

10 

4.5 

5 

2.25 

Average Input Capacitance 

c c 


10 

5 

PF 

Turn-On Propagation Delay: 

Control Input to 
Signal Output 

tPHL' 

t PLH 

C L = 50 pF 

r l = io kn 

v c = Vpp (square) 

V is <V DD 

t r ,t f = 20 ns 

15 

140 


10 

200 

5 

400 

Inhibit Input to 
Signal Output 

15 

140 

10 

200 

5 

400 

Inhibit Recovery Time* 



10 

200 

— 


* Time after Inhibit is removed during which channel information is valid. 


CD4067B TRUTH TABLE 


A 

B 

c 

D 

Inh 

Selected 

Channel 

X 

X 

X 

X 

1 

None 

0 

0 

0 

0 

0 

0 

1 

0 

0 

0 

0 

1 

0 

1 

0 

0 

0 

2 

1 

1 

0 

0 

0 

3 

0 

0 

1 

0 

0 

4 

1 

0 

1 

0 

0 

5 

0 

1 

1 

0 

0 

6 

1 

1 

1 

0 

0 

7 

0 

0 

0 

1 

0 

8 

1 

0 

0 

1 

0 

9 

0 

1 

0 

1 

0 

10 

1 

1 

0 

1 

0 

11 

0 

0 

1 

1 

0 

12 

1 

0 

1 

1 

0 

13 

0 

1 

1 

1 

0 

14 

1 1 

1 

1 

1 

0 

15 



92CS-24980 

CD4097B Functional Diagram 


SPECIAL CONSIDERATIONS 

1. In applications where separate power sources are used to 
drive Vpp and the signal inputs, the Vpp current capability 
should exceed Vpp/Ri_ (R|_ = e ff ect > ve external load). 
This provision avoids any permanent current flow or clamp 
action on the Vpp supply when power is applied or 
removed from the CD4067B, CD4097B. 

2. In certain applications, the external load-resistor current 
may include both Vpp and signal-line components. To 
avoid drawing Vpp current when switch current flows into 
the transmission gate inputs, the voltage drop across the 
bidirectional switch must not exceed 0.8 volt (calculated 
from Rqisj values shown). 

No Vpp current will flow through Rl if the switch 
current flows into terminal 1 on the CD4067B; terminals 1 
and 17 on the CD4097B. 


CD4097B TRUTH TABLE 


A 

B 

c 

Inh 

Selected 

Channel 

X 

X 

X 

1 

None 

0 

0 

0 

0 

OX, 0Y 

1 

0 

0 

0 

IX, 1 Y 

0 

1 

0 

0 

2X, 2Y 

1 

1 

0 

0 

3X, 3Y 

0 

0 

1 

0 

4X, 4Y 

1 

0 

1 

0 

5X, 5Y 

0 

1 

1 

0 

6X, 6Y 

1 

1 

1 

0 

7X,7Y 


328 





























File No. 809 


OUCBZ/D 

Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4068B Types 



CD4068B Functional Diagram 


COS/MOS 8-Input NAND Gate 


Features: 

n Medium-Speed Operation - tpj_| |_ = 130 ns, tp L ^ = 100 ns (typ.) at 10 V 
■ Standard B-Series Output Drive 


The RCA-CD4068B NAND gate provides the system designer 
with direct implementation of the positive-logic 8-input NAND 
function and supplements the existing family of COS/MOS 
gates. 

This device has equal source- and sink-current capabilities and 


conforms to standard B-series output drive (see Static Elec- 
trical Characteristics). 

The CD4068B is supplied in a 14-lead dual-in-line welded-seal 
ceramic package (D), plastic package (E), ceramic package (F), 
flat package (K), and in chip form (H). 


V DD 



Fig. 1-CD4068B schematic diagram. 


9-74 


329 






CD4068B 


File No. 809 


STATIC ELECTRICAL CHARACTERISTICS 


CHARAC- 

TERISTIC 

SYMBOL 

TEST 

CONDI- 

TIONS 

CD4068BD CD4068BF 

CD4068BK CD4068BH 

CERAMIC PACKAGE LIMITS 

UNITS 

FIG. 

NO. 

v 0 

Volts 

VDD 

Volts 

— 55°C 

25°C 

125°C 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Quiescent Device 

Current 

'L 


5 

_ 

- 

0.5 

- 

0.01 

0.5 

- 

- 

30 

PA 

13 

10 

- 

- 

1 

- 

0.01 

1 

- 

- 

60 

15 

- 

- 

- 

- 

0.01 

- 

- 

- 

- 

Output Voltage 
Low-Level 

VOL 


5 

- 

- 

Hlffl 

- 

0 

EEO 

- 

- 

■mid 


1 

mm 

- 

- 

■mil 

- 

0 

grin 

- 

_ 

Egg 

15 

- 

- 

- 

- 

0 

- 

- 

- 

- 

High-Level 

VOH 

■ 

5 

Esm 

- 

- 


5 

- 


- 

- 

10 

ItMM 

- 

- 


10 

- 

HE1 

- 

- 

■a 

- 

- 

- 

- 

15 

- 

- 

- 

- 

Noise Immunity 

vnl 

mm 


mm 

- 

- 

IB 

WEM 

- 

■B 

- 

- 

V 

14 


S3 

3 

- 

- 

mm 

4.5 

- 

BO 

- 

- 

BkIM 

mm 

- 

- 

- 

- 

6.75 

- 

- 

- 

- 

vnh 

mm 

5 

MEM 

- 

- 

IB 

2.25 

- 

mm 

- 

- 

i 

mm 

mm 

- 

- 

3 

4.5 

- 

3 

- 

- 

mm 

mm 

- 

- 

- 

- 


- 

- 

- 

- 

Output Drive 
Current: 

N-Channel 

(Sink) 

idn 

0.4 

H 


■ 

■ 

0.4 


■ 


■ 


mA 

1 

0.5 

mm 

1.1 

- 

- 

0.9 

1.8 



■si 

- 

1.5 

mm 

- 

- 

- 

mm 

6 

- 

- 

- 

- 



E3 

5 

-2 

- 

- 

BO 


■1 

heei 

— 

- 

mA 

■ 

k m 

5 

-0.5 

- 

- 

EOEI 

-0.8 

- 

bb 


- 

9.5 

10 

-1.1 

- 

- 

-0.9 

-1.8 

- 

-0.65 

- 

- 

13.5 

15 

- 

- 

- 

-3 

-6 

- 

- 

- 

- 

Input Current 

'l 


15 

- 

- 

- 

- 

±10-5 

±i 

- 

- 

- 

PA 

- 


MAXIMUM RATINGS, Absolute-Maximum Values: 


STORAGE-TEMPERATURE RANGE -65 to+150°C 

OPERATING-TEMPERATURE RANGE: 

CERAMIC-PACKAGE TYPES -55 to +125°C 

PLASTIC-PACKAGE TYPES . -40 to +85 °C 

DC SUPPLY-VOLTAGE RANGE 

V DD * -0.5 to +18 V 

DEVICE DISSIPATION (PER PACKAGE) 200 mW 

LEAD TEMPERATURE (DURING SOLDERING): 

At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) 

from case for 10 seconds max 265 °C 


* All voltage values are referenced to V ss terminal. 


OPERATING CONDITIONS AT T A = 25°C 


For maximum reliability, nominal operating conditions should be 
selected so that operation is always within the following ranges. 


Characteristic 

V DD 

Min. 

Max. 

Units 

Fig. 

Supply Voltage Range 

- 

3 

18 

V 

- 

Input Voltage Swing 
(Recommended Vgg to Vqq) 


0-2 V DD 

to 

0.8 V DD 
(Any one 
input) 

-0.5 V 

to 

V DD + 
0.5 V 

V 



330 










File No. 809 


CD4068B 


STATIC ELECTRICAL CHARACTERISTICS 


CHARAC- 

TERISTIC 

SYMBOL 

TEST 

CONDI- 

TIONS 

CD4068BE 

PLASTIC PACKAGE LIMITS 

UNITS 

FIG. 

NO. 

v 0 

Volts 

V D D 

Volts 

— 40°C 

25°C 

85°C 

Min. 

Typ. 

Max. 


KJJ3 

Max. 

Min. 

Typ. 

Max. 


B 

■ 

5 

- 

- 

5 

■91 


5 

- 


ma 

MA 

B 

mm 

- 

- 

mm 



mm 

- 

■I 

■£[«■ 

mm 

- 

- 

- 

■ 

■a»m 


- 

- 

- 

Output Voltage: 
Low-Level 

VOL 


B 

- 

- 


- 

0 


- 

_ 

ms 

V 

1 

mm 

- 

- 

ebb 

- 

0 

itoti 

- 

- 

eghi 

mm 

- 

- 

- 

- 

0 

- 

- 

- 

- 

High-Level 

VOH 

■ 

5 

BEm 

- 

- 

IflEEl 

5 

- 


- 

- 

mm 

MsEUW 

- 

- 

IHEE1 

10 

- 


- 

- 

mm 

- 

- 

- 

- 

15 

- 

- 

- 

- 

Noise Immunity 

VNL 

■a 

mm 

warn 

- 

- 

KO 

ftiJI 

- 

■El 

- 

- 


1 

9 

mm 

3 

- 

- 

3 

4.5 

- 

EH 

- 

- 

||gj| 

■a 

- 

- 

- 

- 


- 

- 

- 

- 


wm 

5 

ma 

- 

- 

KE3 

i Vktem 

- 

mm 

- 

- 

i 

mm 

BZJI 

- 

- 

mm 

msm 

- 

3 

- 

- . 

KLI 

■a 

- 

- 

- 

- 


- 

- 

- 

- 

Output Drive 
Current: 

N-Channel 

(Sink) 


0.4 

5 

0.45 

■ 

■ 

0.4 

0.8 

■ 


■ 

■ 

mA 

■ 

ESI 

mm 

1 

- 

- 

irei i 

1.8 

- 

esbi 

- 

- 

tsm 

■a 

■ 

- 

- 

mm 

6 

- 

_ 

- 

- 

P-Channel 

(Source) 

IdP 

2.5 

5 

-1.8 

- 

- 

-1.6 

-3.2 

- 

-1.3 

- 

- 

mA 

6,7 

4.6 

5 

-0.45 

- 

- 

-0.4 

-0.8 

- 

-0.36 

- 

- 

9.5 

10 

-1 

- 

- 

-0.9 

-1.8 

- 

-0.75 

- 

- 

13.5 

15 

- 

- 

- 

-3 

-6 

- 

- 

- 

- 

Input Current 

>1 


15 

- 

- 

- 

- 

±10-5 

±i 

- 

- 

- 

JUA 

- 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Input t r , tf » 20 ns, and C L = 50 pF 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

ALL TYPES 
LIMITS 

UNITS 

CHARACTERISTIC 
CURVES & 

TEST CIRCUITS 
FIG. NO. 


V D D 

Volts 

Typ. 

Max. 

Propagation Delay Time: 



5 


■os 




tpHL 


10 



ns 

8, 10 

High-to-Low Level 



15 

100 

II 






5 


500 



Low-to-High Level 

l PLH 


10 


200 

ns 

9,10 




15 


- 




*THL 


5 

100 




Transition Time 



10 

50 


ns 

11 


*TLH 


15 

40 

80 



Average Input Capacitance 

c > 

Any Input 

5 

- 

PF 

- 


331 



































OUTPUT VOLTAGE (V 0 ) 



AMBIENT TEMPERATURE (T A ) = 25«C | 1 [1 1 | | I 

gate- to-source voltage (v^-sv 


AMBIENT TEMPERATURE {T A ) = 25»CLL 

m-i H|| | [I ur 


1444- 1 1 

r-f-H Mil t-H-l-H-t'-H-t-H-H 1 1 1 

- GATE-TO-SOURCE VOLTAGE (VgsJr-SV 

10 V 







92CS- 24 320 

Fig. 6— Typical output-P-channel drain characteristics. 


92CS-2432 I 

Fig. 7— Minimum output-P-channel drain characteristics. 


332 









PROPAGATION DELAY TIME (tpLH.tPHL)' 






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File No. 804 



Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4069B Type 



COS/MOS Hex Inverter 


Features: 

■ Medium Speed Operation - t pHL , t pLH = 40 ns (typ.) at 10 V 

■ Standard B-Series Output Drive 


The RCA-CD4069B consists of six COS/MOS inverter circuits. 
All outputs have equal source and sink current capabilities and 
conform to the standard B-series output drive (see Static Elec- 
trical Characteristics). 

This device is intended for all general-purpose inverter appli- 
cations where the medium-power TTL-drive and logic-level- 
conversion capabilities of circuits such as the CD4009A and 
CD4049A Hex Inverter/Buffers are not required. 

The CD4069B is supplied in 14-lead dual-in-line welded-seal 
ceramic packages (D), plastic packages (E), ceramic packages 
(F), ceramic flat packs (K), and in chip form (H). 



Fig. 1 —Schematic diagram of one of six identical inverters. 


Applications: 

■ Logic inversion 

■ Pulse shaping 

■ Oscillators 

■ High-input-impedance amplifiers 


MAXIMUM RATINGS, Absolute-Maximum Values: 


STORAGE-TEMPERATURE RANGE 

OPERATING-TEMPERATURE RANGE: 

CERAMIC-PACKAGE TYPES 

PLASTIC-PACKAGE TYPES 

DC SUPPLY- VOLT AGE RANGE 

V DD * 

DEVICE DISSIPATION (PER PACKAGE) 

ALL INPUTS V ss 

LEAD TEMPERATURE (DURING SOLDERING): 

At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) 
from case for 10 seconds max 


-65 to +150°C 

-55 to +125°C 
-40 to +85 °C 

-0.5 to +18 V 

200 mW 

< V, < v DD 


266 °C 


* All voltage values are referenced to V SS terminal. 


OPERATING CONDITIONS AT T A = 25°C 


For maximum reliability, nominal operating conditions should be 
selected so that operation is always within the following ranges. 


Characteristic 

V DD 

Min. 

Max. 

Units 

Fig. 

Supply Voltage Range 

- 

3 

18 

V 

- 

Input Voltage Swing 
(Recommended V 55 to V DD ) 


0-2 V DD 
to 

0.8 V DD 
(Any one 
input) 

-0.5 V 

to 

V DD + 
0.5 V 

V 



334 


8-74 







File No. 804. 


CD4069B 


STATIC ELECTRICAL CHARACTERISTICS 


CHARAC- 

TERISTIC 

SYMBOL 

TEST 

CONDI- 

TIONS 

CD4069BD, BF, BK, BH 

CERAMIC PACKAGE LIMITS 

UNITS 

FIG. 

NO. 

v 0 

Volts 

Vdd 

Volts 

— 55°C 

25°C 

125°C 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Quiescent Device 

Current 

'L 


5 

- 

- 

0.5 

- 

0.01 

0.5 

- 

_ 

30 

HA 

17 

10 

- 

- 

1 

- 

0.01 

1 

- 

- 

60 

15 

- 

- 

- 

- 

0.01 

- 

- 

- 

- 

Output Voltage: 
Low-Level 

VOL 


5 

- 

' - 

0.01 

- 

0 

0.01 

- 

- 

0.05 

V 

- 

10 

- 

- 

0.01 

- 

0 

0.01 

- 

- 

0.05 

15 

- 

- 

- 

- 

0 

- 

- 

- 

- 

High-Level 

VOH 


5 

4.99 

- 

- 

4.99 

5 

- 

4.95 

- 

- 

10 

9.99 

- 

- 

9.99 

10 

- 

9.95 

- 

- 

15 

- 

- 

- 

- 

15 

- 

- 

- 

- 

Noise Immunity 

vnl 

3.6 

5 

1.5 

- 

- 

1.5 

2.25 

- 

1.4 

- 

- 

V 

18 

7.2 

10 

3 

- 

- 

3 

4.5 

- 

2.9 

- 


10.8 

15 

- 

- 

- 

- 

6.75 

- 

- 

- 


Vnh 

1.4 

5 

1.4 

- 

- 

1.5 

2.25 

- 

1.5 

- 

- 

2.8 

10 

2.9 

- 

- 

3 

4.5 

- 

3 

- 

- 

4.2 

15 

- 

- 

- 

- 

6.75 

- 

- 

- 

- 

Output Drive 
Current: 

N-Channel 

(Sink) 

IdN 

0.4 

5 

0.5 



0.4 

0.8 


0.3 



mA 

5,6 

0.5 

10 

1.1 

- 

- 

0.9 

1.8 

- 

0.65 

- 

- 

1.5 

15 

- 

- 

- 

3 

6 

- 

- 

- 

- 

P-Channel 

(Source) 

IdP 

2.5 

5 

-2 

- 

- 

-1.6 

-3.2 

- 

-1.15 

- 

- 

mA 

7,8 

4.6 

5 

-0.5 

- 

- 

-0.4 

-0.8 

- 

-0.3 

- 

- 

9.5 

10 

-1.1 

- - 

- 

-0.9 

-1.8 

- 

-0.65 

- 

- 

13.5 

15 

- 

- 

- 

-3 

-6 

- 

- 

- 

- 

Input Current 

'l 


15 

- 

- 

- 

- 

±10- 5 

±1 

- 

- 

- 

fiA 

- 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Input t r , tf = 20 ns, and C L = 50 pF 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

ALL TYPES 

LIMITS 

UNITS 

CHARACTERISTIC 

CURVES & 

TEST CIRCUITS 
FIG. NO. 


V DD 

Volts 

Typ. 

Max. 

Propagation Delay Time: 

tPHI , 


5 

65 

125 






10 


80 

ns 

9, 10 




15 


— 






5 

100 

200 



Transition Time 

'THU 


10 

50 

100 

ns 

11 


*TLH 


15 

40 

80 



Average Input Capacitance 

C| 

Any Input 

5 

- 

pF 

- 


335 



CD4069B 


File No. 804 


STATIC ELECTRICAL CHARACTERISTICS 


TEST 

CONDI- 

CHARAC- SY M B0 L TIONS 


CD4069BE 

PLASTIC PACKAGE LIMITS 


I 25°C | 

85°C i 


Min. 



- 

91 

El 


- 


IBM 

9BKSOB1 

- 

- 

■ 

Riiin mu | 

- 

■ 


limiMIBIiTiB 

- 

- 

EE3 




















File No. 804 


CD4069B 







CD4069B 


File No. 804 



Fig. 10— Typical propagation delay time vs. supply voltage. 


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ill! I 

iiii iiii 

DU jjji 

£ 

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ill 

IBB : 

ill 

::: :! : 

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iiliil 

1 

3 

1 

i 

j 


0 20 40 60 80 100 

LOAD CAPACITANCE (C L )— pF 

92CS-24322 

Fig. 11— Typical transition time vs. load capacitance. 



APPLICATIONS 


rt>n 


Rf 



FOR TYPICAL COMPONENT 
VALUES AND CIRCUIT 
PERFORMANCE, SEE 
APPLICATION NOTES 
XCAN 6086 AND 


XCAN 6539 


92CS-24437 


Fig. 13— Typical crystal oscillator circuit. 


Fig. 12— Typical dynamic power dissipation. 


1/3 CD4069B 



FOR TYPICAL COMPONENT 
VALUES AND CIRCUIT PERFORMANCE, 
SEE APPLICATION NOTE ICAN-6267 


1/6 CD4069B 



Rf«IO MEG 


1/3 CD4069B 



Rf 

UPPER SWITCHING POINT: 
R s + Rf V DD 
V P * — R f ~ 

LOWER SWITCHING POINT: 
R f - R S V DD 

v N «-^ ~ 


R f > R s 


92CS-24438 


92CS-24439 


92CS-24440 


Fig. 14— Typical RC oscillator circuit. 


Fig. 15— High-input impedance amplifier. 


Fig. 16— Input pulse shaping circuit (Schmitt trigger ). 



File No. 804 


CD4069B 




339 







Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 


Preliminary CD4070BE, CD4077BE 



COS/MOS 

Quad Exclusive-OR Gate— CD4070B 
Quad Exclusive-NOR Gate— CD4077B 


V. 

I* 

y 

14 

— VDD 

A — 

L. 

I* 

J 

14 

2 

13 

— H 

B — 

2 

13 

3 

12 

— G 

J=A©B — 

3 

12 

4 

II 

— M*G©H 

K*C©D — 

4 

II 

5 

10 

— L*E©F 

C — 

5 

10 

6 

9 

— F 

D — 

6 

9 

7 

8 

— E 

V S S — 

7 

8 


— VDD 

— H 

— G 

— M*G©H 

— L = E©F 

— F 

— E 


9ZCS-24498 


TERMINAL ASSIGNMENT 
CD4070B 


TERMINAL ASSIGNMENT 
CD4077B 


The RCA-CD4070B contains four independent exclusive-0 R 
gates. RCA-CD4077B contains four independent exclusive-NOR 
gates. 

Type CD4070B is pin-for-pin compatible with RCA-CD4030A 
and in addition has greater current-sourcing capability and a 
higher input impedance. 

The GD4070B and CD4077B are supplied in 14-lead dual-in- 
line plastic packages. 


MAXIMUM RATINGS, Absolute-Maximum Values: 

STORAGE-TEMPERATURE RANGE -65 to +150°C 

OPERATING-TEMPERATURE RANGE -40 to +85 °C 

DC SUPPLY-VOLTAGE RANGE: 

(V DD *) -0.5 to +18 V 

DEVICE DISSIPATION (PER PACKAGE) 200 mW 

ALL INPUTS V ss < V, < V DD 

LEAD TEMPERATURE (DURING SOLDERING) 

At distance 1/16 ± 1/32 in. (1.59 ±0.79 mm) 

from case for 10 s max +265 °C 


* All voltage values are referenced to Vgg terminal. 

OPERATING CONDITIONS AT T A = 25°C 


For maximum reliability , nominal operating conditions should be 
selected so that operation is always within the following ranges. 


Characteristic 

BSH 


Max. 

Units 

Fig. 

Supply Voltage Range 

- 

3 

18 

D 

- 

Input Voltage Swing 
(Recommended Vgg to Vqq) 

1 

0.2 V DD 
to 

0.8 V DD 
(Any one 
input) 

-0.5 V 

to 

V DD + 
0.5 V 

V 



TRUTH TABLE CD4070B 
1 of 4 Gates 


A 

B 

J 

0 

0 

0 

1 

0 

1 

0 

1 

1 

1 

1 

0 


Where 1 = High Level 
" 0 = Low Level 
J = A © B 


TRUTH TABLE CD4077B 
1 of 4 Gates 


A 

B 

J 

0 

0 

1 

1 

0 

0 

0 

1 

0 

1 

1 

1 


Where 1 = High Level 
" 0 = Low Level 

J = A© B 


340 


8-74 











Preliminary CD4070BE, CD4077BE 


STATIC ELECTRICAL CHARACTERISTICS AT T A = 25°C 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

TYPICAL VALUES 
CD4070B 
CD4077B 

UNITS 

v 0 

Volts 

V DD 

Volts 

Quiescent Device Current 

«L 


5 

0.01 

HA 

10 

0.01 

Output Drive Current: 

N-Channel (Sink) 

i d n 

V| = V SS 

0.4 

5 

0.8 

mA 

0.5 

10 

1.8 

P-Channel (Source) 

»dP 

Q 

Q 

> 

II 

>" 

4.6 

5 

-0.8 

2.5 

5 

-1.8 

9.5 

10 

-1.8 


DYNAMIC ELECTRICAL CHARACTERISTICS AT T A = 25°C, C L = 50 pF, Input t r ,tf = 20 ns 


CHARACTERISTIC 


TEST CON 

DITIONS 

VDD 

Volts 

TYPICAL VALUES 

CD4070B 

CD4077B 

UNITS 

Propagation Delay: 

High-to-Low 

tPHL 


5 

175 

ns 

10 

70 

Low-to-High 

tPLH 


5 

175 

ns 

10 

70 

Transition Time: 

High-to-Low 

*THL 


5 

100 

ns 

10 

50 

Low-to-High 

*TLH 


5 

100 

ns 

10 

50 

Average Input Capacitance 

C| 

Any Input 

5 

pF 


341 


































File No. 807 


Digital Integrated Circuits 

Monolithic Silicon 

CD4071B Types 
CD4072B Types 
CD4075B Types 

COS/MOS OR Gates 


CD4071B Quad 2-Input OR Gate 
CD4072B Dual 4-Input OR Gate 
CD4075B Triple 3-Input OR Gate 

Features: 

■ Medium-Speed Operation tpj_H = 70 ns (typ.); tp^L = 100 ns (typ.) at 10 V 

■ Standard B-Series Output Drive 


The RCA-CD4071B, -CD4072B, and -CD4075B OR gates 
provide the system designer with direct implementation of the 
positive-logic OR function and supplement the existing family 
of COS/MOS gates. These devices have equal source- and sink- 
current capabilities and conform to standard B-Series output 
drive (see Static Electrical Characteristics). 

The CD4071B, CA4072B, and CD4075B are supplied in 14-lead 
dual-in-line plastic packages (E), welded-seal ceramic packages 
(D), ceramic packages (F), ceramic flat-packs (K), and in 
chip form (H). 


MAXIMUM RATINGS, Absolute-Maximum Values: 


STORAGE-TEMPERATURE RANGE -65 to +150°C 

OPERATING-TEMPERATURE RANGE: 

CERAMIC-PACKAGE TYPES -55 to +125°C 

PLASTIC-PACKAGE TYPES -40 to +85 °C 

DC SUPPLY-VOLTAGE RANGE 

V DD * -0.5 to +18 V 

DEVICE DISSIPATION {PER PACKAGE) 200 mW 

LEAD TEMPERATURE {DURING SOLDERING): 

At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) 

from case for 10 seconds max 265°C 


* All voltage values are referenced to V SS terminal. 



tUCMl 

Solid State 
Division 



OPERATING CONDITIONS AT T A = 25°C 


For maximum reliability, nominal operating conditions should be 
selected so that operation is always within the following ranges. 



Fig. 1—CD407 IB schematic diagram (1 of 4 identical OR gates). 


342 


9-74 







File No. 807 


CD4071B, CD4072B, CD4075B 


STATIC ELECTRICAL CHARACTERISTICS 


CHARAC- 

TERISTIC 

SYMBOL 

TEST 

CONDI- 

TIONS 

CD4071BD, BF, BK, BH CD4072BD, BF, BK, BH 

CD4075BD, BF, BK, BH 

CERAMIC PACKAGE LIMITS 

UNITS 

FIG. 

NO. 

v 0 

Volts 

VDD 

Volts 

— 55°C 

25°C 

125°C 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Quiescent Device 

Current 

<L 


5 

- 

- 

5 

_ 

0.01 

0.5 

- 

- 

30 


15 

10 

- 

- 

10 

- 

0.01 

1 

- 

- 

60 

15 

- 

- 

- 

- 

0.01 


- 

- 

- 

Output Voltage 
Low-Level 

VOL 


5 

- 

- 

0.01 

- 

0 

0.01 

- 

- 

0.05 

V 

- 

10 

- 

- 

0.01 

- 

0 

0.01 

- 

- 

0.05 

15 

- 

- 

- 

- 

0 

- 

- 

- 

- 

High-Level 

VOH 


5 

4.99 

- 

- 

4.99 

5 

_ 

4.95 

- 

- 

10 

9.99 

- 

- 

9.99 

10 

- 

9.95 

- 

- 

15 

- 

- 

- 

- 

15 

- 

- 

- 

- 

Noise Immunity 

VNL 

0.8 

5 

1.5 

- 

- 

1.5 

2.25 

- 

1.4 

- 

- 

V 

4,5, 16 

1 

10 

3 

- 

- 

3 

4.5 

- 

2.9 

- 

- 

1.5 

15 

- 

- 

- 

- 

6.75 

- 

- 

- 

- 

vnh 

4.2 

5 

1.4 

- 

_ - 

1.5 

2.25 

- 

1.5 

- 

- 

9 

10 

2.9 

- 

- 

3 

4.5 

- 

3 

- 

- 

13.5 

15 

- 

- 

- 

- 

6.75 

- 

- 

- 

- 

Output Drive 
Current: 

N-Channel 

(Sink) 


1 

H 


| 

1 


0.8 



■ 

■ 


1 


mm 




SilsS 

1.8 

- 

■Qi 



mm 

mm 




mm 

6 

- 


B 

■ 

P-Channel 

(Source) 


mm 

5 

-2 

- 

- 

ess 

WSWM 

- 


- 

- 


■ 

mxM 

5 


- 

- 

QQ 

-0.8 

- 


- 

- 

Mivm 

10 

BD 

- 

- 


jam 

- 


- 

- 


19 

- 

- 

- 

mm 

-6 

- 

- 

- 

- 

Input Current 

'l 




- 

- 

- 


SI 

. - 

- 

- 


- 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Input t r , tf = 20 ns, and C L = 50 pF 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

ALL TYPES 

LIMITS 

UNITS 

CHARACTERISTIC 
CURVES & 

TEST CIRCUITS 
FIG. NO. 


V DD 

Volts 

Typ. 

Max. 

Propagation Delay Time: 



5 

250 

500 




t PHL 


10 

100 

200 

ns 

10, 12 

High-to-Low Level 



15 

75 

- 






5 

175 

350 



Low-to-High Level 

t PLH 


10 

70 

140 

ns 

11, 12 




15 

55 

- 




X THL 


5 

100 

200 



Transition Time 



10 

50 

100 

ns 

13 


*TLH 


15 

40 

80 



Average Input Capacitance 

C| 

Any Input 

5 

- 

pF 

- 


343 







CD4071B, CD4072B, CD4075B 


File No. 807 
























CHANNEL DRAIN CURRENTS I Q N) 


Bmii 


raiil 


litTil 














CD4071B, CD4072B, CD4075B 


File No. 807 



FREQUENCY (f )- kHz 

92CS-24323 

Fig. 14— Typical dynamic power dissipation vs. frequency. 


V DD 



CD4075B - PUT METER IN SAME 
PLACE AS CD407IB 
TIE PINS 1,2,3,4,5,11,12,13 
TO SWITCH. 


CD4072B - PUT METER IN SAME 
PLACE AS CD407IB 
TIE PINS 2,3,4,5,9,10,11,12 
TO SWITCH. 


92CS-24492 


Fig. 15— Quiescent current test circuits. 



Fig. 16— Noise immunity test circuits. 


92CM— 24493RI 






File No. 806 



Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4081B Types 
CD4082B Types 
CD4Q73B Types 



COS/MOS AND Gates 


CD4081 B Quad 2-Input AND Gate 
CD4082B Dual 4-Input AND Gate 
CD4073B Triple 3-Input AND Gate 


Features: 

■ Medium-Speed Operation — tp|_n = 85 ns (typ.); tpm_ = 65 ns (typ.) at 10 V 

■ Standard B-Series Output Drive 


The RCA-CD4081B, -CD4082B, and -CD4073B AND gates Static Electrical Characteristics). 


provide the system designer with direct implementation of the 
AND function and supplement the existing family of COS/MOS 
gates. These devices have equal source- and sink-current capa- 
bilities and conform to standard B-series output drive (see 


The CD4081B, CD4082B, and CD4073B are supplied in 14- 
lead dual-in-line plastic packages (E), welded-seal ceramic 
package (D), ceramic packages (F), ceramic flat packs (K), and 
chip form (H). 



Fig. 1 -CD4081 B schematic diagram (1 of 4 identical AND gates). 


MAXIMUM RATINGS, Absolute-Maximum Values: 


STORAGE-TEMPERATURE RANGE -65 to +150°C 

OPERATING-TEMPERATURE RANGE: 

CERAMIC-PACKAGE TYPES -55 to +125°C 

PLASTIC-PACKAGE TYPES -40 to +85 °C 

DC SUPPLY-VOLTAGE RANGE 

V DD * -0.5 to +18 V 

DEVICE DISSIPATION (PER PACKAGE) 200 mW 

LEAD TEMPERATURE (DURING SOLDERING): 

At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) 

from case for 10 seconds max 265 °C 


* All voltage values are referenced to Vgg terminal. 


OPERATING CONDITIONS AT T A = 25°C 


For maximum reliability, nominal operating conditions should be 
selected so that operation is always within the following ranges. 


Characteristic 

V DD 

Min. 

Max. 

Units 

Fig- 

Supply Voltage Range 

- 

3 

18 

V 

- 

Input Voltage Swing 
(Recommended Vgg to Vpp) 


0 2 V DD 
to 

0 8 v DD 
(Any one 
input) 

-0.5 V 

to 

V DD + 
0.5 V 

V 



348 


8-74 






File No. 806 _ 


.CD4081B, CD4082B, CD4073B 


STATIC ELECTRICAL CHARACTERISTICS 


TEST CD4081BD, BK, BF, BH CD4082BD, BK, BF, BH 


CHARAC- 

TERISTIC 


Quiescent Device 
Current 


SYMBOL TI0 NS 

Vo 


CD4073BD, BK, BF, BH 
CERAMIC PACKAGE LIMITS 






WEI 

EBEEMsSI 

- 


E 

1 

0.01 1 

- 

~ 


— 

0.01 

- 

- 


wsm 

miKHEEDI 

- 

- 


gtTtTl 

M— IliKill 

- 

- 


- 

i - 1 Q 1 - 1 

- 

- 

- 

r - 

I' 1 1 'W 1 IH 

Bum 

- 

- 



ma 

- 

- 


Output Drive 
Current: 

N-Channel 

(Sink) 

IdN 

■PPMi 

idp 

(Source) 




Input Current 


9.5 10 -1.1 

13.5 15 

15 ~ 


-0.9 -1.8 

-3 -6 


I ±10-5 I ±i 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Input t r , tf = 20 ns, and C L = 50 pF 



349 







































CD4081B, CD4082B, CD4073B 


File No. 806 


STATIC ELECTRICAL CHARACTERISTICS 


CHARAC- 

TERISTIC 

SYMBOL 

TEST 

CONDI- 

TIONS 

CD4081BE, CD4082BE, CD4073BE 

PLASTIC PACKAGE LIMITS 

UNITS 

FIG. 

NO. 

v 0 

Volts 

VdD 

— 40°C J 

25°C ! 

85°C 

Volts 



^231 


BE 9 


H! 

Si 

ESI 

Quiescent Device 
Current 

D 

■ 

5 

3 


mm 



B! 


B 

E3 

HA 

15 

■El 

- 

- 

■Ell 

- 

KS3 

■Ell 

- 

3 

na 

mm 


- 


- 


CZ] 

- 


- 

Output Voltage: 
Low-Level 

VOL 

■ 

mm 

_ 

- 

ram 

- 

0 

EE9 

_ 


ran 

1 

1 

m 

- 

- 

ran 

- 

0 

fEESM 

- 

- 

E53 

wm 

- 

- 

- 

- 

0 

- 

- 

- 

- 

High-Level 

VOH 

■ 

L_5 

BE 1 

- 

- 

rag 

5 

- 

EE23 

- 

- 

mm 

13 

- 

- 


10 

- 

E3 

- 

- 

mm 

- 

- 

- 

cz: 

15 

- 

- 

- 

- 

Noise Immunity 

vnl 


5 

wm 

- 

- 

KO 

ESI 

- 

mm 

- 

- 

V 

4, 5, 16 


mm 

3 

- 

- 

3 

4.5 

- 

WEEM 

- 

- 


mm 

- 

- 

- 

- 

323 

- 

- 

- 

- 

VNH 


mm 

MEM 

- 

- 

wm 


- 

wm 

- 

- 


■EB 

mim 

- 

- 

3 

mm 

- 

3 

- 

- 


wm 

- 

- 

- 

- 


- 

- 

- 

- 

Output Drive 
Current: 

N-Channel 

(Sink) 

IdN 

0.4 

5 

0.45 

■ 

■ 

0.4 

0.8 

■ 

0.36 

■ 

■ 

mA 

1 

mu 

mm 

1 

- 

- 

EEI 

1.8 

- 


3 

- 

mm 

wm 

■ 

- 

- 

3 

6 

- 

L- 

L- 

- 

P-Channel 

(Source) 

Idp 

wm 

mm 

BE1 

- 


BO 

lEB 

IB 

Ell 

IB 

- 

mA 

8,9 

mm 


[SKU 

- 

- 

ISO 

Em 




- 

13 

eS 

!BH 

- 

- 

ISO 

mm 


bee 

3 

- 

EES 

wm 

3 

- 

- 

El 

IKO 

- 

- 

- 

- 


Input Current 

■l 

r: 

ID 

B 

- 


f: 

±10-5 

±1 

- 

- 

- 

AiA 

- 



Fig. 2—CD4082B schematic diagram (1 of 2 identical AND gates). 


350 












































OUTPUT VOLTAGE (V 0 )-V 
DRAIN CURRENT Ho)-mA 


File No. 806_ 


. CD4081 B, CD4082B, CD4073B 



*ALL INPUTS PROTECTED BY 

STANDARD COS/MOS PROTECTION 
NETWORK 



92CS-2 3828 

Fig. 3—CD4073B schematic diagram (1 of 3 identical AND gates). 



AMBIENT TEMPERATURE (T A )*25°C 

15 -SUPPLY j-H 

■VOLTAGE 44 : - f- - - : - - - 

> (V DD )=I5 vt - ; ; : 

JL 12.5 - tH - t - H ± i ± ------------- 





m mi 


0 2.5 5 7.5 10 12.5 15 

INPUT VOLTAGE ( V T )— V 


0 2.5 5 7.5 10 12.5 15 

INPUT VOLTAGE ( V T )— V 


Fig. 4— Typical voltage and current transfer characteristics. 


Fig. 5— Min. and max. voltage transfer characteristics. 


| AMBIENT TEMPERATURE (T A )*25°C 


[AMBIENT TEMPERATURE (T^n25»CjJ 


L MAXIMUM PACKAGE DISSIPATION = 200 it 



SOURCE VOLTAGE (V 6S )< 




DELAY TIME (t PHL ) 


CD4081B, CD4082B, CD4073B. 


.File No. 806 


DRAIN -TO -SOURCE VOLTAGE (V DS )-V 

M5 -10 -5 

AMBIENT TEMPERATURE (T A ) = 25°C 1 1 1 1 X 1 1 1 1 1 

Til 1 1 ii 1 1 1 1 ii 1 1 1 1 1 in 1 1 1 n i- l 'l mm 

I f GATE- TO- SOURCE VOLTAGE (V GS )=-5V: 


I MAX I MUM PACI 
-} DISSIPATION = 2 



DRAIN -TO -SOURCE VOLTAGE (V DS )-V 

H5 -10 -5 

ambient temperature (t a )*25°c ii::::::::::: 

M } I i I II 1 1 N f H H t t - H - H 1 1 1 1 1 1 1 = 

rj GATE- TO- SOURCE VOLTAGE (V 6S )=-5V 


Fig. 8— Typical output-P-channel drain characteristics. 


92CS-24 32I 

Fig. 9— Minimum output-P-channel drain characteristics. 


AMBIENT TEMPERATURE (T A ) = 25°C : ::: 


IMS II: 

i HT?!## :H: ip HI: 'lilt fit -I I t - m : 

r :::: ni.MMIT !!;! Iffillillil nff 1 


iSiHilSliiMliiSiilil JlliikziiiMlE 

0 20 40 60 80 100 

LOAD CAPACITANCE (C L ) — pF 

92CS-245 

Fig. 10— Typical high-to-low level propagation delay vs. 
load capaci tance. 


• in mm i i m 



if 

ill 

-iSSffis 

|f 

1 


lie 

r 


1 

•Hi 

■ 1 jj 


ijir 

E-ffijjjlj 

1!:: 


j: 

TTTf 

enl 


tmk 



j Wfljij].!; 4 



| jJJJjjljJjjji 



mil | 



■-SfSiiM 

M 

1 


MmiiilliJIlllife 

20 40 60 80 100 

LOAD CAPACITANCE (C L ) — pF 

92CS- 24532 

. 1 1— Typical low-to-high level propagation delay vs. 
load capaci tance. 


„ AMBIENT TEMPERATURE (T A )= 25°C I 

? LOAD CAPACITANCE (C L ) = 50 pF I 

4. 600 I I I I ITTTTTTT I ' ll I ' ll I I I I I I 1 C 


giaaajgajagjjMijml 



i- CHANNEL DRAIN CURRENT (XpP)-mA 





CD4081B, CD4082B, CD4073B 


File No. 806 



FREQUENCY (f )- KHz 

92CS-24323 

Fig. 14— Typical dynamic power dissipation vs. frequency. 


V D D 



CD4073B- PUT METER IN SAME 
PLACE AS CD408I 
TIE PINS 1,2,3,4,5,11,12,13 
TO SWITCH 


CD4082B - PUT METER IN SAME 
PLACE AS CD408I 
TIE PINS 2,3,4,5,9,10,11,12 
TO SWITCH. 


92CS-24534 


Fig. 1 5— Quiescent current test circuits. 



92CM -24535 


Fig. 16— Noise immunity test circuits. 





Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

Preliminary CD4076BE 


Preliminary Data 


DATA INPUT 
DISABLE 

Gl G2 

1 L 

CLOCK 


)UTPUT 

)ISABLE 

M N 

1 . 1 






“XT 


Df 





~ cr \ 

01 




A D-TYPE 







FLIP/FLOPS 

WITH 

ANO-OR 


1 

Lof^ 



-ot^ 


LOGIC 


-<fK- 










L j 

RESET 

92CS-24885 

CD4076B Functional Diagram 


COS/MOS 4-Bit D-Type Register 

With 3-State Outputs 


OUTPUT 
DISABLE ) N 



CD4076B 

TERMINAL ASSIGNMENT 


The RCA-CD4076BE four-bit register includes D-type flip- 

flops that feature three-state outputs. Data Disable inputs are disable 

provided to control the entry of data into the flip-flops. 

When both Data Disable inputs are low, data at the D inputs 
are loaded into their respective flip-flops on the next positive d/ 

transition of the clock input. Output Disable inputs are also 
provided. When the Output Disable inputs are both low, the data \ gi ' 
normal logic states of the four outputs are available to the load. disable^ 
The outputs are disabled (present a high impedance) independ- 
ently of the clock by a high logic level at either Output Disable 
input. d 

CD4076BE 
Truth Table 



When either Output Disable M or N is high, the outputs are 
disabled (high impedance state); however sequential operation 
of the flip-flops is not affected. 

1= High Level X = Don't Care 

0 = Low Level NC = No Change 



ALL inputs protected by standard 
COS/MOS PROTECTION NETWORK 


Fig. 1-CD4076B logic diagram. 


354 


9-74 









Preliminary CD4076BE 


STATIC ELECTRICAL CHARACTERISTICS AT T A = 25°C 


CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 

CD4076B 

TYPICAL 

VALUES 

UNITS 

> 

O 

> 

v DD ( V ) 

Quiescent Device Current 

A 


5 

0.02 

HA 


10 

0.02 

Output Device Current: 

N-Channel (Sink) 

i d n 

0.4 

5 

0.8 

mA 

0.5 

10 

1.8 

P-Channel (Source) 

' D P 

4.6 

5 

- 0.8 

2.5 

5 

- 3.2 

9.5 

10 

- 1.8 


DYNAMIC ELECTRICAL CHARACTERISTICS AT T A = 25°C, C L = 50 pF, Input t r ,tf = 20 ns 


CHARACTERISTIC 

SYMBOL 

> 

Q 

Q 

> 

TYPICAL VALUES 

UNITS 



5 

260 


Propagation Delay 

^HL^PLH 

10 

120 

ns 



5 

100 


Transition Time 

tTHL'tPLH 

10 

50 

ns 



5 

100 


Data Setup Time 

*SUHL' tSULH 

10 

60 

ns 



5 

125 


Minimum Clock Pulse Width 

%L' %H 

10 

50 

ns 



5 

75 


Minimum Reset Pulse Width 

x \nhW 

10 

40 

ns 



5 

230 


Reset Propagation Delay 

tpHL( R > 

10 

120 

ns 

Data Input Disable 

t SU (DIS) 

5 

100 


Setup Time 

10 

60 

ns 



5 

15 


Clock Rise and Fall Time 

t r CL, t f CL 

10 

15 

lis 



5 

4 


Clock Frequency 

f CL 

10 

10 

MHz 

3-State Propagation Delay 
Output 1 or 0 to 

tpd-H), 

5 

110 

ns 

High Impedance 

tp(O-H) 

10 

65 


3-State Propagation Delay, 

tp(H-l), 

5 

80 

ns 

High Impedance to 1 or 0 

tp(H-O) 

io s 

45 


355 





Preliminary CD4076BE 


MAXIMUM RATINGS, Absolute-Maximum Values: 

STORAGE-TEMPERATURE RANGE -65 to +150°C 

OPERATING-TEMPERATURE RANGE -40 to +85 °C 

DC SUPPLY-VOLTAGE RANGE 

V DD * -0.5 to +18 V 

DEVICE DISSIPATION (PER PACKAGE) 200 mW 

ALL INPUTS Vgg < V, < V DD 

LEAD TEMPERATURE (DURING SOLDERING). 

At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) 

from case for 10 seconds max 265 °C 

* All voltage values are referenced to Vgg terminal. 


OPERATING CONDITIONS AT T A = 25°C 


For maximum reliability, nominal operating conditions should be 
selected so that operation is always within the following ranges. 


Characteristic 

V DD 

Min. 

Max. 

Units 

Fig. 

Supply Voltage Range 

- 

3 

18 

V 

- 

Input Voltage Swing 
(Recommended Vgg to Vqq) 


0.2 V DD 
to 

0.8 V DD 
(Any one 
input) 

-0.5 V 

to 

V DD + 
0.5 V 

V 




356 




File No. 810 



Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

GD4078B Type 



COS/MOS 8-Input NOR Gate 


Features: 

■ Medium-speed operation - tpm. = 80 ns, tp|_H = 170 ns (typ.) at 1° v 

■ Standard B-series output drive 


*a>- 


*(D— 


c*0- 


* 0 - 


a 




til u 




3 

3 

3 


aiS 


3-R P 

n#- 


The RCA-CD4078B NOR Gate provides the system designer 
with direct implementation of the positive-logic 8-input NOR 
function and supplements the existing family of COS/MOS 
gates. 

This device has equal source- and sink-current capability and 
conforms to standard B-series output drive (see Static Elec- 
trical Characteristics). 

The CD4078B is supplied in a 14-lead dual-in-line welded-seal 
ceramic package (D), plastic package (E), frit-seal ceramic 
| Vdo package (F ), 14-lead flat package (K), and in chip form (H). 

t — i — n 


A 




y 


. '5" 

3\ 



1 

,3 

9 



, X 


Ua 

bit 


111 

llEr 


3~ ,3-' ,3 @j 


u 




f v ss 


* ALL INPUTS PROTECTED BY 

STANDARD COS/MOS PROTECTION 
NETWORK 


J«A+B+C + D+E+F>G+H 
LOGIC I * HIGH 
LOGIC 0 * LOW 



jf V SS 

Fig. 1—CD4078B schematic diagram. 


92CM- 23878RI 


8-74 


357 






CD4078B 


File No. 810 


STATIC ELECTRICAL CHARACTERISTICS 


CHARAC- 

TERISTIC 

SYMBOL 

TEST 

CONDI- 

TIONS 

CD4078BD CD4078BF 

CD4078BK CD4078BH 

CERAMIC PACKAGE LIMITS 

UNITS 

FIG. 

NO. 

vo 

Volts 

Vdd 

Volts 

— 55°C 

25°C 

125°C 



U23 


Typ. 


BJJ331 

PTS 

EQ 

Quiescent Device 
Current 

fl 

■ 

5 

- 

- 


-• 

BE 

WEI 


- 

Ml 

Q 


mm 

- 

- 

i 

- 


i 

- 

- 


mm 

- 

- 

- 

- 

BE 

- 

- 

- 


Output Voltage 
Low-Level 

VOL 

■ 

5 

_ 

- 

ESB 

- 

0 

wm 

- 

- 

BE3 

l 


El 

- 

- 

gnrm 

- 

0 

Eg 

- 

- 


mm 

- 

- 

m 

- 

0 

- 

- 

- 

- 

High-Level 

VOH 

■ 

5 

EEEl 

- 

- 

BfSEI 

5 

- 

EES 

- 

- 

mm 

EES 

- 

- 


10 

- 

EES 

- 

- 

mm 

- 

- 

- 

- 

15 

- 

- 

- 

- 

Noise Immunity 

vnl 

mm 

5 

mm 

- 

_ 

in 

WSBM 

- 

■a 

- 

- 

V 


9 

10 

3 

- 

-■ 

3 

4.5 

- 

mm 

- 

- 

M13I 

mm 

- 

- 

- 

- 

ess 

- 

- 

- 

- 

vnh 

mm 

5 

in 

- 

- 

KE1 

WEES 

- 

mm 

-■ 

- 


mm 

MEM 

- 

- 

mm 

mm 

- 

3 

- 

- 

worn 

mm 


- 

- 

- 

B3QE 

- 

- 

- 

- 

Output Drive 
Current: 

N-Channel 

(Sink) 

idN 

0.4 

5 

0.5 

1 

■ 

■ 

■ 

■ 

0.3 

■ 

■ 

mA 

1 


10 

1.1 

- 

- 

HE 

mm 

- 

MsEl 

- 

- 

mm 

mm 

- 

- 

- 

3 


- 

- 

- 

- 

P-Channel 

(Source) 

»dP 

MM 

n 

-2 

- 

- 


EE 

- 

BE 

- 

- 

mA 

■ 

Cl 

5 

EH 

- 


BME1 

-0.8 

- 


- 

- 

09 

mm 

b a 

- 

- 

Esj 

-1.8 

- 


- 

- 


mm 

- 

- 

- 

-3 

-6 

- 

- 

- 

- 

Input Current 

•l 


■a 

- 

- 

- 

- 

±10-5 

±i 

- 


- 

ma 

- 


MAXIMUM RATINGS, Absolute-Maximum Values: 


STORAGE-TEMPERATURE RANGE -65 to +150°C 

OPERATING-TEMPERATURE RANGE: 

CERAMIC-PACKAGE TYPES -55 to +125°C 

PLASTIC-PACKAGE TYPES -40 to +85 °C 

DC SUPPLY-VOLTAGE RANGE 

V DD * -0.5 to +18 V 

DEVICE DISSIPATION (PER PACKAGE) 200 mW 

LEAD TEMPERATURE (DURING SOLDERING): 

At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) 

from case for 1 0 seconds max 265 °C 


* All voltage values are referenced to Vgg terminal. 


OPERATING CONDITIONS AT T A = 25°C 


For maximum reliability, nominal operating conditions should be 
selected so that operation is always within the following ranges. 


Characteristic 

tm 

EQQB 

BjjjjjUBi 

EES 

EH 

Supply Voltage Range 

- 

3 

KB 

ms 

B 

Input Voltage Swing 
(Recommended Vgg to Vq D ) 

1 

0.2 V DD 
to 

0.8 V DD 
(Any one 
input) 

-0.5 V 

to 

V DD + 
0.5 V 

V 

i 


358 







































File No. 810. 


STATIC ELECTRICAL CHARACTERISTICS 


TEST 

CONDI- 

CHARAC- SYMBQL TIONS 



P-Channel 

(Source) 


Input Current 



MEM 

rrn 

- 

- 


1.8 

- 


- 

— mA 

em 

■a 

Big 

- 

- 


6 

- 


- 

- 

wm 

5 

-1.8 

- 

- 

pp 

-3.2 

- 

IBQ 

- 

- 


5 

—0.45 

— 

— s 

— U.^l 

—0.8 

— 

— U.Jb 

— 

— mA 

9.5 

10 

-1 

- 

- 

-0.9 

-1.8 

- 

-0.75 

- 

- 

13.5 

15 

- 

- 

- 

-3 

-6 

- 

- 

- 

- 


15 

- 

- 

- 

- 

±10-5 

±1 

- 

- 

- [lA 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Input t r , tf = 20 ns, and C L = 50 pF 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

ALL TYPES 

LIMITS 

UNITS 

CHARACTERISTIC 

CURVES & 


V DD 

Volts 

Typ. 

Max. 

TEST CIRCUITS 

FIG. NO. 

Propagation Delay Time: 



5 

200 

400 




t PHL 


10 

80 

160 

ns 

8,10 

High-to-Low Level 



15 

60 

- 






5 

425 

850 



Low-to-High Level 

X PLH 


10 

170 

340 

ns 

9,10 




15 

120 

- 




X THL 


5 

100 

200 



Transition Time 



10 

50 

100 

ns 

11 


l TLH 


15 

40 

80 




Average Input Capacitance 












92CS- 24320 

Fig. 6— Typical output p-channel drain characteristics. 


92CS-24 32 1 

Fig. 7— Minimum output p-channel drain characteristics. 


360 






POWER DISSIPATION (P D )-/iW 







File No. 811 



Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4085B Type 



COS/MOS Dual 2-Wide 
2-Input AND-OR-INVERT Gate 


Features: 

■ Medium-speed operation — tpj-jL = 90 ns; tp|_|_| = 125 ns (typ.) at 10 V 

■ Individual inhibit controls 

■ Standard B-series output drive 


The RCA-CD4085B contains a pair of AND-OR-INVERT gates, 
each consisting of two 2-input AND gates driving a 3-input OR 
gate followed by an inverter. Individual inhibit controls are 
provided for both A-O-l gates. This device has equal source- 
and sink-current capabilities and conforms to standard B-series 


MAXIMUM RATINGS, Absolute-Maximum Values: 

STORAGE-TEMPERATURE RANGE -65 to +150°C 

OPERATING-TEMPERATURE RANGE: 

CERAMIC-PACKAGE TYPES -55 to +125°C 

PLASTIC-PACKAGE TYPES -40 to +85 °C 

DC SUPPLY-VOLTAGE RANGE 

V DD * -0.5 to +18 V 

DEVICE DISSIPATION (PER PACKAGE) 200 mW 

ALL INPUTS V ss < V, < V DD 

LEAD TEMPERATURE (DURING SOLDERING). 

At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) 

from case for 10 seconds max 265°C 

* All voltage values are referenced to Vgg terminal. 


output drive (see Static Electrical Characteristics). 

The CD4085B is supplied in a 14-lead dual-in-line welded-seal 
ceramic package (D), plastic package (E), ceramic package (F), 
ceramic flat pack (K), and chip form (H). 


OPERATING CONDITIONS AT T A = 25°C 


For maximum reliability, nominal operating conditions should be 
selected so that operation is always within the following ranges. 


Characteristic 

V DD 

Min. 

Max. 

Units 

Fig. 

Supply Voltage Range 

- 

3 

18 

V 

- 

Input Voltage Swing 
(Recommended Vgg to Vpp) 


0.2 V DD 
to 

0 8 V DD 
(Any one 
input) 

-0.5 V 

to 

V DD + 
0.5 V 

V 



362 


8-74 







CD4085B, 


File No. 811 































File No. 811 


CD4085B 


STATIC ELECTRICAL CHARACTERISTICS 


CHARAC- 

TERISTIC 

SYMBOL 

TEST 

CONDI- 

TIONS 

CD4085BE 

PLASTIC PACKAGE LIMITS 

UNITS 

FIG. 

NO. 

v 0 

Volts 

VDD 

Volts 

— 40°C 

25°C 

85°C 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Quiescent Device 
Current 

'L 


5 

- 

- 

5 

- 

0.01 

5 

- 

- 

70 

MA 

13 

10 

- 

- 

10 

- 

0.01 

10 

- 

- 

140 

15 

- 

- 

- 

— 

0.01 

- 

- 

- 

- 

Output Voltage: 
Low-Level 

VOL 

■ 

5 

- 

- 

HSU 


0 

HI 

- 

- 

fcdlud 

1 

- 

MM 

- 

- 

fiTiTi 

- 

0 

u 

- 

- 

E3 

mm 

- 

- 

- 

- 

0 

- 

- 

- 

- 


VOH 

■ 

5_ 

KI4 L 1 

- 

- 


5 

- 

EE9 

- 

- 

MM 


- 

- 


10 

- 


- 

- 

worn 

- 

- 

- 

- 

15 

- 

- 

- 

- 


VNL 

EH 

5 

mm 

- 

- 

in 


- 

mm 

- 

- 

1 

14 

9 

mm 

3 

- 

- 

3 

4.5 

- 

MEM 

- 

- 


■a 

- 

- 

- 

- 


- 

- 

- 

- 

vnh 

mm 

mm 

1.4 

- 

- 

IB 


- 

mm 

- 

- 


B9 

E£JB 

- 

- 

3 

4.5 

- 

3 

- 

- 

■a 

■a 

- 

- 

- 

- 


- 

- 

- 

- 

Output Drive 
Current: 

N-Channel 

(Sink) 

idn 

0.4 

5 

0.45 

■ 

■ 


0.8 

■ 


■ 

■ 

mA 

■ 

ESI 

mm 

1 

- 

- 

n 

1.8 

- 

EES 


- 

MM 

mm 

hh 

- 

- 

ma 

6 

- 

- 

- 

- 

P-Channel 

(Source) 

idP 

ra 

:EI 

HH 

- 

- 

IBB 

I 

- 

mi 

| 

- 

mA 

6, 7 

tm 


nncui 

- 

- 

IB5H 

HU 

- 

filled 

| 

- 


mm 

HI 

- 

- 

S33 

iH 

- 

BUM 


- 


mm 


- 

- 

mm 

-6 

- 

- 

- 

- 

Input Current 

h 


Q 

| 

- 

- 

- 


±i 

- 

- 

- 


IH 1 


n -CHANNEL DRAIN CURRENT (I D N)-mA 

AMBIENT TEMPERATURE (T A ) = 25°C 

- 














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DRAIN - TO - SOURCE VOLTAGE (V DS )-V 

92CS-243I8 





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O 5 10 15 

DRAIN - TO - SOURCE VOLTAGE (V DS )-V 

92CS-243I9 


Fig. 4— Typical output n-channel drain characteristics. 


Fig. 5— Minimum output n-channel drain characteristics. 


365 

















CD4085B 


File No. 811 


DYNAMIC ELECTRICAL CHARACTERISTICS AT T A = 25°C, C L = 50 pF, Input t r ,tf = 20 ns 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

LIMITS 

UNITS 

FIG. NO. 


Q> 

> 

Typ. 


Propagation Delay 

Time (Data): 
High-to-Low Level 

tPHL 


5 

225 


ns 

8, 10 

10 

90 

180 

15 

65 

- 

Low-to-High Level 

tPLH 


5 

|QQ[| 

620 

ns 

9, 10 

10 


250 

15 

90 

- 

Propagation Delay 

Time (Inhibit): 
High-to-Low Level 

tPHLONH) 


5 


300 

ns 

- 



120 

15 

40 

- 

Low-to-High Level 

tPLH(INH) 


5 

250 

500 

ns 

- 

10 

100 

200 

15 

70 

- 

Transition Time 

^HL. 

*TLH 


5 

100 

200 

ns 

11 

10 

50 

100 

15 

40 

80 

Average Input 

Capacitance 

C| 

Any Input 

5 

- 

pF 

- 


DRAIN -TO -SOURCE VOLTAGE (V DS )-V 
!z]5 -10 -5 0 


AMBIENT TEMPERATURE IT. Is?*»c 1 







r 


: 



a 

■ 



a 

a 


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SI 

Q 














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9 

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■ 

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r/ 



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H 

GATE- TO- S 

0URCE VO 

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a 

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MAXIMUM PACKAGE 

■ 

■ 


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92CS-24320 


Fig. 6— Typical output p-channel drain characteristics. 


DRAIN -TO -SOURCE VOLTAGE (V DS )-V 



Fig. 7— Minimum output p-channel drain characteristics. 


31 

























































PROPAGATION DELAY TIME (tpHL. t PLH> _ 





File No. 812 


U1CBZ<D 

Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4086B Type 



COS/MOS Expandable 4-Wide 
2-Input AND-OR-INVERT Gate 


Features: 

■ Medium-speed operation — tpm_ = 90 ns; tp|_n = 140 ns (typ.) at 10 V 

■ INHIBIT and ENABLE inputs 

■ Standard B-series output drive 


The RCA-CD4086B contains o ne 4 -wide 2-input AND-OR- 
INVERT gate with an INHIBIT/EXP input and an ENABLE/ 
EXP input. For a 4-wide A-O-l function INHIBIT/EXP is tied 
t0 Vgs and ENABLE/EXP to Vpp. See Fig. 2 and its asso- 
ciated explanation for applications where a capability greater 
than 4-wide is required. This device has equal source- and 


MAXIMUM RATINGS, Absolute-Maximum Values: 

STORAGE-TEMPERATURE RANGE -65 to+150°C 

OPERATING-TEMPERATURE RANGE: 

CERAMIC-PACKAGE TYPES -55 to +125°C 

PLASTIC-PACKAGE TYPES -40 to +85 °C 

DC SUPPLY-VOLTAGE RANGE 

V DD * -0.5 to +18 V 

DEVICE DISSIPATION (PER PACKAGE) 200 mW 

LEAD TEMPERATURE (DURING SOLDERING): 

At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) 


sink-current capabilities and conforms to standard B-series 
output drive (see Static Electrical Characteristics). 

The CD4086B is supplied in the 14-lead dual-in-line welded- 
seal ceramic package (D), ceramic package (F), plastic package 
(E), ceramic flat pack (K), and in chip form (H). 


OPERATING CONDITIONS AT T A = 25°C 


For maximum reliability, nominal operating conditions should be 
selected so that operation is always within the following ranges. 


Characteristic 

V DD 

Min. 

Max. 

C 

3 

9 

Fig. 

Supply Voltage Range 

- 

3 

18 

V 

- 

Input Voltage Swing 
(Recommended Vgg to Vqq) 


0.2 V DD 
to 

0.8 V DD 
(Any one 
input) 

-05 V 

to 

V DD + 
0.5 V 

V 



from case for 10 seconds max 2(£°C 

* All voltage values are referenced to V gs terminal. 


368 


8-74 







File No. 812 


CD4086B 


Fig. 1—CD4086B schematic diagram. 



J2=AI Bl+CI DI4EI FI +61 HI + A2 B2 + C2 D2+-E2 F2+-G2 H2 


92CS -23871 

Fig. 2— Two CD4086B's connected as an 8-wide 2-input A-O-l gate. 

Fig. 2 above shows two CD4086B's utilized to obtain an output can be fed directly into the ENABLE/EXP input to 
8-wide 2-input A-O-l function. The output (J 1 ) of one obtain a 5-wide A-O-l function. In addition, any AND gate 
CD4086B is fed directly to the ENABLE/EXP2 line of the output can be fed directly into the INHIBIT/EXP input with 
second CD4086B. In a similar fashion, any NAND gate the same result. 



369 



CD4086B. 


File No. 812 


STATIC ELECTRICAL CHARACTERISTICS 


CHARAC- 

TERISTIC 


TEST 
CONDI- 
SYMBOL TiQ , NS 


CD4086BD CD4086BK 

CD4086BF CD4086BH 

CERAMIC PACKAGE LIMITS 



25°C 

125°C | 

1 Max. 

Min. 1 Typ. 

Max. 

Min. 

Typ. 

Max. 1 

IBS 

wawsm 

WEI 

_ 

_ 

ESI 

1 

tBUEESM 

i 

- 

- 

ES 

- 

B3UZM 

- 

- 

- 

_Z] 

ieeh 

wmmm 

gum 

- 

- 


IEEH 

_g_. 


- 

- 

ESIj 






























File No. 812 


CD4086B 


STATIC ELECTRICAL CHARACTERISTICS 


TEST 

CONDI- 


CD4086BE 


CHARAC- 

SYMBOL 

TIONS 

PLASTIC PACKAGE LIMITS 1 

UNITS 

TERISTIC 


v 0 1 VDD 

— 40°C 1 25°C 

85°C ! 




Input Current 





FIG. 

NO. 


14 



5.6 


7.8 




92CS-243I8 

Fig. 5— Typical output n-channel drain characteristics. 


< 

f 15 

AMBIENT TEMPERATURE ( T A ) = 25°C t 


::: 

ri 


E 



T 


~ 






















i 


- 














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Z 

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a 

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z 
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0 5 10 15 

DRAIN- TO -SOURCE VOLTAGE JV DS )-V 

92CS-243I 

Fig. 6— Minimum output n-channel drain characteristics. 


3; 






























CD4086B 


File No. 812 


DYNAMIC ELECTRICAL CHARACTERISTICS AT T A = 25°C, C L = 50 pF, Input t r ,t f = 20 ns 


CHARACTERISTIC 

SYMBOL 

TEST COND 

ITIONS 

LIMITS 

UNITS 

Fig. No. 

V DD 

Volts 

TYP. 


Propagation Delay 

Time (Data): 

High-to-Low Level 

*PHL 


5 

225 


ns 

9. 11 

10 

90 

180 

15 

60 

- 

Low-to-High Level 

*PLH 


5 

350 

700 

ns 

10, 11 

10 

140 

280 

15 

100 

- 

Propagation Delay 

Time (Inhibit): 

High-to-Low Level 

tPHLONH) 


5 


300 

ns 

- 

10 

60 

120 

15 

40 

- 

Low-to-High Level 

t PLH(INH) 


5 


500 

ns 

- 

10 

100 

200 

15 

70 

- 

Transition Time 

X THL> 

*TLH 


5 

100 

200 

ns 

12 

10 

50 

100 

15 

40 

80 

Average Input 

Capacitance 

C| 

Any Input 

5 

- 

pF 

- 


DRAIN- TO - SOURCE VOLTAGE (V DS )-V 



Fig. 7— Typical output p-channel drain characteristics. 


DRAIN -TO- SOURCE VOLTAGE (V os )-V 

-IS -10 -5 0 


AMBIENT TEMPERATURE (T A )*25* 

7E 



T- 

TT 

: 

£ 

£ 

■i 

■i 

iv 

»/ 

mi 


r 









ft 







HI U-j.] 

1 1 i-i-i | |iq 

=f£ 









,'i 







GATE- TO 

-SOURCE V 

DLT 

AG 

(V« 

)=- 

5 V f 


A' 

jJ 













_i_ 

1 it 



4H 


4 


rt 

■■ 

HI 








- 




-- 

— 

1 







M 


■! 

IS 

■Eg 








_ 






IE 







■1 


■l 

■■ 









_ 




1 

IO 

V 









4 


H 

Z 












3 













ce 

<r 

z> 












i 


:: 

























li; 





II 






--IO < 














— 





__ 






o 



4 






















_J 



-- 






-15 

V 









-- 



4 



lli 

' z 



; " 











::: 





:: 






< 

X 



; i 


4 




; 





li; 





;i 



:z 



; -l5 k 



: i 






:::: 





n: 














: i 






-± 


-- 



± : 





£ 

-1 


£ 


±\ 



92CS-24 32 1 

Fig. 8— Minimum output p-channel drain characteristics. 


372 




























































DELAY TIME (»p HL ) 


File No. 812 


iSEIii 


AMBIENT TEMPERATURE (T A )«2 

TTf 



20 40 60 

LOAD CAPACITANCE (C 



SUPPLY VOLTAGE {Vdd>— V 


Fig. 1 1— Typical DATA or ENABLE propagation delay 
time vs. supply voltage. 



PP| 








IlllSiiBiillI 


* -"v ~? jr J ' k 





LOAD CAPACITANCE (C L )— pF 

92CS-243 

Fig. 12— Typical transition time vs. load capacitance. 


51 AMBIENT TEMPERATURE (T A )• 25°C 



_ C (_« 50 pF 

C|_ »I5 pF 


FREQUENCY (f ) — kHz 

9ZCS-Z4323 

Fig. 13— Typical power dissipation vs. frequency. 


Fig. 14— Quiescent device current 
test circuit. 


Fig. 15— Noise immunity 
test circuit. 


’3 








□UGBZ/D 

Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

Preliminary CD4089BE 



COS/MOS Binary Rate Multiplier 


The RCA-CD4089B is a low-power 4-bit digital rate multiplier 
that provides an output pulse rate that is the dock-input-pulse 
rate multiplied by 1/16 times the binary input. For example, 
when the binary input number is 13, there will be 13 output 
pulses for every 16 input pulses. This device may be used to 
perform arithmetic operations (add, subtract, divide, raise to a 
power), solve algebraic and differential equations, generate 
natural and trigonometric functions, A/D and D/A conversions, 
and frequency division. 

For words of more than 4 bits CD4089B devices may be 
cascaded in two different modes: an Add mode and a Multiply 
mode (see Figs. 3 and 4). In the Add mode some of the gaps 
left by the more significant unit at the count of 15 are filled 
in by the less significant units. For example, when two units 
are cascaded in the Add mode and programmed to 11 and 13, 
respectively, the more significant unit will have 11 output 
pulses for every 16 input pulses and the other unit will have 13 
output pulses for every 256 input pulses for a total of 

11 13189 

16 256 ~ 256' 

In the Multiply mode the fraction programmed into the first 
rate multiplier is multiplied by the fraction programmed into 
the second multiplier. Thus the output rate will be 

21 13 143 

16 * 16 ~ 256 

The CD4089B has an internal synchronous 4-bit counter which, 
together with one of the four binary input bits, produces 
pulse trains as shown in Fig. 1. 

If more than one binary input bit is high, the resulting pulse 
train is a combination of the above separate pulse trains. 


CLOCK jumnnnn^ 

COUNTER STATE 0 12 3 4 5 6 7 8 9 10 II 12 13 14 15 0 I 

(LSB) INPUT A=H fl [_] 

l I 

INPUT B = H Tl fl |-4— 

INPUT C=H TL fl fl fl I— j. 

(MSB) INPUT D*H Jl_JLJLJl_n_JLJLjUrL 

I I 

92CS-25006 


*An output bit may be filled in in this counter state by a less 
significant CD4089B cascaded in the Add mode. 


Fig. 1 —Timing diagram. 


374 


9-74 






Preliminary CD4089B 


STATIC ELECTRICAL CHARACTERISTICS AT T A = 25°C 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

TYPICAL VALUES 

UNITS 


<o 

Q > 
> 

Quiescent Device Current 

»L 


5 

0.02 


10 

0.02 

Output Drive Current: 

All Outputs 

N-Channel (Sink) 




5 

0.8 

mA 


10 

1.8 

P-Channel (Source) 

■d p 


Esa 

5 

-0.8 

■za 

5 

-3.2 

9.5 

10 

-1.8 


DYNAMIC ELECTRICAL CHARACTERISTICS AT T A = 25°C, C L = 50 pF, Input t p tf = 20 ns 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

TYPICAL VALUES 

UNITS 


V DD 

V 

Propagation Delay 

tPHL* 

tPLH 

Clock to 

"Out” 

5 

180 

ns 

10 

90 

Clock to 

"Inhibit Out" 

5 

260 

10 

130 

Transition Time 

tfLH' 

X THL 


5 

100 

ns 

10 

50 

Maximum Clock Frequency 

fCL^ax.) 


5 

2 

MHz 

10 

4.5 

Maximum Clock Rise 
and Fall Time 

t r ,tf(Max.) 


5 

15 

jUS 

10 


MAXIMUM RATINGS, Absolute-Maximum Values: 

STORAGE-TEMPERATURE RANGE -65 to +150°C 

OPERATING-TEMPERATURE RANGE -40 to +85 °C 

DC SUPPLY-VOLTAGE RANGE 

V DD * -0.5 to +18 V 

DEVICE DISSIPATION (PER PACKAGE) 200 mW 

ALL INPUTS V ss < V, < V pD 

LEAD TEMPERATURE (DURING SOLDERING): 

At distance 1/16 ± 1/32 inch (1 .59 ± 0.79 mm) 

from case for 10 seconds max 265°C 

* All voltage values are referenced to Vgg terminal. 


OPERATING CONDITIONS AT T A = 25°C 


For maximum reliability, nominal operating conditions should be 
selected so that operation is always within the following ranges. 


Characteristic 

V DD 

Min. 

Max. 

Units 

Fig. 

Supply Voltage Range 

- 

3 

18 

V 

- 

Input Voltage Swing 
(Recommended V<jg to V pp ) 


0.2 V DD 
to 

0.8 V DD 
(Any one 
input) 

-0.5 V 

to 

V DD + 
0.5 V 

V 



375 






















Preliminary CD4089B 


TRUTH TABLE 













Number of Pulses 







Inputs 






or 

Output Logic Level 













(H or L) 






No. of 






Pin 6 

Pin 5 

Pin 7 

Pin 1 

D 

c 

B 

A 

Clock Pulses 

lnh, N 

Strobe 

Cascade 

Clear 

Set 

OUT 

OUT 

,nh OUT 

"15" 

0 

D 

0 

0 

16 

0 

0 

0 

0 

0 

L 

H 


mm 

0 

0 

0 

1 

16 

0 


0 

0 

0 

1 

1 


Wm 

0 

0 

1 

0 

16 

0 


0 

0 

■ 

2 



mm 

0 

0 

1 

1 

16 

0 

0 

0 

0 

0 

3 



Hi 

0 

n 


0 

16 

0 

0 



0 

4 

4 

■ 


0 

n 


1 

16 

0 

0 



0 

5 

5 

i 

i 

0 

n 


0 

16 

0 

0 



0 

6 

6 

i 

i 

0 

a 

H 

1 

16 

0 

0 



0 

7 

7 

i 

i 

n 

0 

0 

0 

mMrmm 


0 




8 

8 

i 

mm 

n 

0 

0 

1 



0 




9 

9 

i 

mm 

n 

0 

1 

0 



0 




10 

10 

i 

Wm 

u 

0 

1 

1 



0 


mm 


11 

11 

i 

H 

II 

a 



16 





0 

12 

12 


i 

n 

u 



16 




■ • 

0 

13 

13 


i 

n 

n 



16 




Bra 

0 

14 

14 


i 

n 

n 

H 


16 




wm 

0 

15 

15 


i 

X 

X 

X 

X 

16 

1 



B 



Depends on internal 

state of counter 

■ 

X 

X 

X 

X 

16 

0 





L 

H 

i 

i 

X 

X 

X 

X 

16 

0 

0 

1 

0 

0 

H 

* 

i 

i 

1 

X 

X 

X 

16 

0 

0 

0 

1 

0 

16 

16 

H 

L 

0 

X 

X 

X 

16 

0 

0 

0 

1 

0 

L 

H 

H 

L 

X 

X 

X 

X 

16 

0 

0 

0 

0 

1 

L 

H 

L 

H 


* Output same as the first 16 lines of this truth table (depending on values of A, B, C, D). 


376 





















Preliminary CD4089B 


* * * * -X -X 

3 2 15 14 10 12 



V SS Fig. 2— Logic diagram, CD4089B. 


MOST SIGNIFICANT LEAST SIGNIFICANT 



CL0CK 92CS-25008 92CS -25009 

Fig. 3— Two CD4089B's cascaded in the "Add" mode Fig. 4— Two CD4089B's cascaded in the "Multiply" mode 


with a preset number of 189. with a preset number of 143. 


377 






File No. 836 


[MM] 

Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4093B Type 



COS/MOS Quad 2-Input NAND 
Schmitt Triggers 


Features: 

■ Schmitt-trigger action on each input with no external components 

■ Hysteresis voltage typically 0.6 V at Vpp = 5 V 

and 2 Vat Vpp = 10 V 

■ Noise immunity greater than 50% 

■ Equal source and sink currents 

■ No limit on input rise and fall times 

■ Standard B-series output drive 


The RCA-CD4093B consists of four Schmitt-trigger circuits. 
Each circuit functions as a two-input NAND gate with 
Schmitt-trigger action on both inputs. The gate switches at 
different points for positive- and negative-going signals. The 
difference between the positive voltage (Vp) and the negative 
voltage (V|yj) is defined as hysteresis voltage (V^) (see Fig. 2). 
All outputs have equal source and sink currents and conform 
to standard B-series output drive (see Static Electrical Charac- 
teristics). 

The CD4093B is supplied in 14-lead dual-in-line plastic 
packages (E), welded-seal ceramic packages (D), ceramic 
packages (F), ceramic flat packs (K), and in chip form (H). 


V DD 



Fig. 1— Functional diagram— 1 of 4 Schmitt triggers. 


Applications: 

■ Wave and pulse shapers 

■ High-noise-environment systems 

■ Monostable multivibrators 

■ A stable multivibrators 

■ NAND logic 


MAXIMUM RATINGS, Absolute-Maximum Values: 


STORAGE-TEMPERATURE RANGE -65to+150°C 

OPERATING-TEMPERATURE RANGE: 

CERAMIC-PACKAGE TYPES -55 to +125°C 

PLASTIC-PACKAGE TYPES -40 to +85 °C 

DC SUPPLY-VOLTAGE RANGE 

V DD * -0.5 to +18 V 

DEVICE DISSIPATION (PER PACKAGE) 200 mW 

ALL INPUTS V ss < V, < V DD 

LEAD TEMPERATURE (DURING SOLDERING): 

At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) 

from case for 10 seconds max 265°C 


* All voltage values are referenced to Vgg terminal. 

OPERATING CONDITIONS AT T A = 25°C 


For maximum reliability, nominal operating conditions should be 
selected so that operation is always within the following ranges. 


Characteristic 

V DD 

Min. 

Max. 

Units 

Fig. 

Supply Voltage Range 

- 

3 

18 

V 

- 

Input Voltage Swing 
(Recommended Vgg to Vpp) 


0.2 Vpp 
to 

0.8 Vpp 
(Any one 
input) 

-0.5 V 

to 

V DD + 
0.5 V 

V 



378 


9-74 







File No. 836 


CD4093B 



TEST 

CHARACTERISTIC SYMBOL CONDI- 
TIONS 


Quiescent Device 
Current 


CD4093BD, BF, BK, BH 
CERAMIC PACKAGE LIMITS 





Positive Trigger 
Threshold Voltage 


Negative Trigger 
Threshold Voltage 


Hysteresis Voltage V^ 


Noise Immunity 


Output Drive Current: 
N-Channel 
(Sink) 


I 


| BSD ES3 ESDI ^231122^3 IED S2Z2 CSS 

BH 

BBBEBEZ3BB1E3 

BH 

BOBBDBBO 

BH 

BBBESOBBIBB 

BH 

BEOBBIEDBIBE^ 

BH 

BEEOBmEEUBiBB 


//A 20 





P-Channel 

(Source) 


H§o 

■Kami 


\m\ 

IB 


ISUEE1BES3I 


V 3,21 


mA 8, 9 


Input Current 





















































CD4093B File No. 836 


STATIC ELECTRICAL CHARACTERISTICS 


CHARACTERISTIC 

SYMBOL 

TEST 

CONDI- 

TIONS 

CD4093BE 

PLASTIC PACKAGE LIMITS 

UNITS 

FIG. 

NO. 

v 0 

V 


— 40°C 

25°C 

85°C 


EH 

^22 

U3J 

BIB 

02 H 

U3I 

CHI 

33 

Quiescent Device 
Current 

■ 


m 

- 

- 

5 

- 

0.01 

L 3 

- 

- 

m 

ma 

20 

m 

- 


m 

- 

3HI 

KM 

- 

- 

mi 

m 

- 

- 


- 


- 

- 

- 


Output Voltage: 
Low-Level 

V 0 L 


D 

- 

- 

OH 

- 

0 

[flu 

- 

- 

S3 

V 


m 

- 

- 

HU 

- 

■31 

0.01 

- 

- 

33 

KM 

- 

- 

- 

- 

0 

- 

- 

- 

- 

High-Level 

v OH 


5 


- 

- 

4.99 

5 

- 


- 

- 

m 


- 

- 

123 

mm 

- 


- 

- 

m 

- 

- 

- 


mm 

- 

- 

- 

- 

Positive Trigger 
Threshold Voltage 

D 


5 

- 

3 

- 

33 

wrm 

33 

- 

03 

- 

V 

H 

m 

- 


- 

ESI 

fj 

7 

- 

ESI 

- 

KM 

- 


- 


E 

- 

- 

- 

- 

Negative Trigger 
Threshold Voltage 

V N 


5 

- 

03 

- 

m 

331 

m 

- 

EDI 

- 

■ 

1 

O 

- 

4 

- 

3 

3.9 

m 

- 

ESI 

- 

■a 

- 

- 

- 

- 

EM 

- 

- 


- 

Hysteresis Voltage 

V H 


5 

- 

a 

- 

EDI 

131 

- 

- 

ESI 

- 

V 

B 

O 

- 

ID 

- 

1 

mm 

- 

- 

33 

- 

KM 

- 

- 

- 

- 


- 

- 


- 

Noise Immunity 

Vnl 

0 

m 

- 

3 

- 

3 

■ 

33 

- 

HI 

- 

V 

3,21 

0 

m 

- 


- 

d 

SI 


- 

5.9 

- 

0 

ra 

- 


- 


ESI 

Hi 

- 

- 

- 

Vnh 

5 

5 

- 


- 

03 

ESB 

03 

- 


- 

m 

B3 

- 

6 

- 

UM 



- 


- 

m 

O 


- 

- 


W$M 

1 

- 

- 

- 

Output Drive Current: 
N-Channel 
(Sink) 



5 

ESS 

- 

- 

1 

0.8 

lZ 

H3 

- 

- 

mA 

1 

Hi 

KM 

HI 

- 

- 

3 

ra 

mm 

K2S! 

- 

- 


KM 

^H 

- 

- 

3 

6 



- 

- 

P-Channel 

(Source) 

q 


5 

mm 

- 

- 

m 


OH 

331 

- 

- 

mA 

8,9 

03 

u 

3 

- 

- ' 

ES 

-0.8 

LT 


Hi 

- 

Ed 

B3 

■ 

- 

- 


BE3 

a 


- 

- 

SB 

KM 


- 

- 

El 

-6 


- 

- 

- 

Input Current 

'l 


m 

- 

- 

- 

- 


IB 

B 

- 

- 

/iA 

IB^ 


380 












































File No. 836 


.CD4093B 












CD4093B . 


.File No. 836 


AMBIENT TEMPERATURE (T A )-25*C 


DRAIN- TO -SOURCE VOLTAGE (V D$ )-V 







File No. 836 


CD4093B 


AMBIENT TEMPERATURE (T A )*25°C 


SSI: 


5 10 

SUPPLY VOLTAGE (V DD )-V 

92CS-2483I 

Fig. 13— Typical trigger threshold voltage vs. V DD- 



92CS-24832 

Fig. 14— Typical per cent hysteresis vs. supply voltage. 




92CS-24833 


Fig. 15— Typical dissipation characteristics. Fig. 16— Power dissipation vs. rise and fall times. 



TO CONTROL 
SIGNAL 
OR V 0D 

-klH- 

1/4 CD4093B 


FREQUENCY RANGE OF WAVE SHAPE 
IS FROM DC TO I MHz 


APPLICATIONS 


jut: 


JJ_ 


TO CONTROL 
SIGNAL 
► OR Voo 


M 

_ru 


V DD 

VSS 


t M 3 RCj>n,-^, 

50 kn < R < I Mil 
loo pF < C < \ fiF 


92CS- 23884 


FOR THE RANGE OF R AND C 
GIVEN 5/xs < t M < 0.5s 


Fig. 17— Wave shaper. 


Fig. 18— Monostable multivibrator. 


92CS- 23886 



T 


T 

VNL 


V SS 


92CS-24838 


Fig. 19—Astable multivibrator. 


Fig. 20— Quiescent device current test circuit. Fig. 21— Noise immunity test circuit. 


383 








OaCBZ/D 

Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

Preliminary CD4094BE 



COS/MOS 8-Stage Shift-and-Store 
Bus Register 


The RCA-CD4094B is an 8-stage serial shift register having a 
storage latch associated with each stage for strobing data from 
the serial input to parallel buffered 3-state outputs. Data is 
shifted on positive clock transitions. The data in each shift 
register stage is transferred to the storage register when the 
strobe input is high. Data in the storage register appears at the 
outputs whenever the output-enable signal is high. 

Two serial outputs are available for cascading a number of 
CD4094B devices. Data is available at the Q S serial output 
terminal on positive clock edges to allow for high-speed 
operation in cascaded systems in which the clock rise time is 
fast. The same serial information, available at the q’s terminal 
on the next negative clock edge, provides a means for cascading 
CD4094B devices when the clock rise time is slow. 

The CD4094B is supplied in a 16-lead dual-in-line plastic 
package. 


TRUTH TABLE 


cl a 

Output 

Enable 

Strobe 

Data 

Q, 

Out 

q n 

Out 

Q s 

Serial 

Output 

Q 's 

Serial 

Output 

J- 

0 

X 

X 

OC 

OC 

Q7 

NC 


0 

X 

X 

OC 

OC 

NC 

Q7 

J- 

1 

0 

X 

NC 

NC 

Q7 

NC 

s 

1 

1 

0 

0 

°N-I 

Q7 

NC 

y 

1 

1 

1 

1 

°N-I 

Q7 

NC 

A. 

1 

1 

1 

NC 

NC 

NC 

Q7 


A - Level Change Logic 1 = High 

X = Don't Care Logic 0 = Low 

NC = No Change 
OC = Open Circuit 


MAXIMUM RATINGS, Absolute-Maximum Values: 

STORAGE-TEMPERATURE RANGE -65 to +150°C 

OPERATING-TEMPERATURE RANGE -40 to +85 °C 

DC SUPPLY-VOLTAGE RANGE: 

(V DD *I -0.5 to +18 V 

DEVICE DISSIPATION (PER PACKAGE) 200 mW 

ALL INPUTS V ss < V, < V DD 

LEAD TEMPERATURE (DURING SOLDERING) 

At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) 

from case for 10 s max +265°C 


* All voltage values are referenced to Vgg terminal. 


OPERATING CONDITIONS AT T A = 25°C 


For maximum reliability, nominal operating conditions should be 
selected so that operation is always within the following ranges. 


Characteristic 

V DD 

Min. 

Max. 

Units 

Fig. 

Supply Voltage Range 

- 

3 

18 

V 

- 

Input Voltage Swing 
(Recommended Vgg to Vqq) 


02 v DD 

to 

0.8 V DD 
(Any one 
input) 

-0.5 V 

to 

V DD + 
0.5 V 

V 



384 


8-74 







Preliminary CD4094BE 


STATIC ELECTRICAL CHARACTERISTICS AT T A = 25°C 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

TYPICAL VALUES 

UNITS 



v 0 

Volts 

V DD 

Volts 



Quiescent Device Current 

l, 



5 

0.5 

[iA 

'L 



mm 

1 

Output Drive Current: 

N-Channel (Sink) 

i d n 

_< 

ii 

< 

CO 

CO 

0.4 

m 

0.8 


I3H 

EH 

1.8 

mA 




is 

5 

-0.8 

P-Channel (Source) 

■ 



5 

-3.2 






10 

-1.8 



DYNAMIC ELECTRICAL CHARACTERISTICS AT T A = 25°C, C L = 50pF, Input t r ,tf = 20 ns (except t r CL andt f CL) 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

TYPICAL VALUES 

UNITS 



V DD 

Volts 



Propagation Delay Time: 

Clock to Serial Out Qg 


5 

300 



10 

120 


Clock to Serial Out Q'g 


5 

215 



10 

90 


Clock to Parallel Out 

t PHL' 

5 

375 

ns 

tPLH 

10 

150 

Strobe to Parallel Out 


5 

300 



10 

120 


Output Enable to Output 


5 

175 



10 

70 


Transition Time 

tTHL' 

5 

100 

ns 

*TLH 

10 

50 

Minimum Strobe 

tWL' 

5 

75 


Pulse Width 

*WH 

10 

40 


Clock Rise and 

■ 

5 

>15 

Us 

Fall Time 

■ 

10 

>15 

Setup Time 

*SU 

5 

45 

ns 

10 

30 

Maximum Clock Frequency 

f CL 

5 

2 


(50% Duty Cycle) 

10 

4 

Average Input Capacitance 

C| 

Any Input 

5 

pF 


385 

























































□UCBZ/D 

Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

Preliminary CD4095BE 
Preliminary CD4096BE 


COS/MOS Gated J-K 
Master-Slave Flip-Flops 

With Set-Reset Capability 


CD4095B Non-Inverting J and K Inputs 
CD4096B Inverting and Non-Inverting J and K Inputs 


SYNCHRONOUS OPERATION (S=0, R=0) 


The RCA-CD4095B and -CD4096B are JK Master/Slave Flip- 
Flops featuring separate AND gating of multiple J and K inputs. 
The gated JK inputs control transfer of information into the 
master section during clocked operation. Information on the 
JK inputs is transferred to the Q and Q outputs on the positive 
edge of the clock pulse. SET and RESET inputs (active high) 
are provided for asynchronous operation. 

The CD4095B and CD4096B are supplied in 14-lead dual-in- 
line plastic packages (CD4095BE, CD4096BE). 


Inputs Before 

inputs After 

Positive Clock 

Positive Clock 

Transition 

Transition 

J* 

tm 

IO 

O 

0 

0 

No Change 

0 

i 

0 I 1 

1 

0 

1 1 0 

1 

i 

Toggles 


•For CD4095B 
J = J1 • J2 • J3 
K = K1 * K2 • K3 
For CD4096B_ 

J = J1 • J2 • J3 

K = K1 • K2 • K3 


ASYNCHRONOUS OPERATION (J and K = DON'T CARE) 


S 

R 

Q 

01 

0 

0 

No Change 1 

0 

1 

0 

1 

1 

0 

1 

0 

1 

1 

1 

1 



CD4095B Functional Diagram 


MAXIMUM RATINGS, Absolute-Maximum Values: 


STORAGE-TEMPERATURE RANGE -65 to +150°C 

OPERATING-TEMPERATURE RANGE -40 to +85 °C 

DC SUPPLY-VOLTAGE RANGE: 

( V DD* } -0.5 to +18 V 

DEVICE DISSIPATION (PER PACKAGE) 200 mW 

ALL INPUTS V ss < V, < V DD 

LEAD TEMPERATURE (DURING SOLDERING) 

At distance 1/16 ± 1/32 in. (1.59 ±0.79 mm) 

from case for 10 s max +265°C 


* All voltage values are referenced to V ss terminal. OPERATING CONDITIONS AT T A = 25°C 


For maximum reliability, nominal operating conditions should be 
selected so that operation is always within the following ranges. 


Characteristic 

V DD 

Min. 

Max. 

Units 

Fig. 

Supply Voltage Range 

- 

3 

18 

V 

- 

Input Voltage Swing 
(Recommended Vg S to V DD ) 


0.2 V DD 
to 

0.8 V DD 
(Any one 
input) 

-0.5 V 

to 

V DD + 
0.5 V 

V 



386 


9-74 













Preliminary CD4095B, CD4096B 


STATIC ELECTRICAL CHARACTERISTICS AT T A = 25°C 


CHARACTERISTIC 

SYMBOL 

TEST 

CONDITIONS 

CD4095B, CD4096B 
TYPICAL 

VALUES 

UNITS 

v o 

V DD V SS 

Quiescent Device Current 

«L 


5 

0.01 

/iA 


10 

0.02 

Output Device Current: 

N-Channel (Sink) 

i d n 

0.4 

5 

0.8 

mA 

0.5 

10 

1.8 

P-Channel (Source) 

l D p 

4.6 

5 

- 0.8 

2.5 

5 

- 1.8 

9.5 

10 

- 1.8 


DYNAMIC ELECTRICAL CHARACTERISTICS AT T A = 25°C, C L = 50 pF, Input t r ,tf = 20 ns 




TEST 

CONDITIONS 

CD4095B, CD4096B 
TYPICAL 


CHARACTERISTIC 

SYMBOL 

v 0 

V DD* V SS 

VALUES 

UNITS 

| Clocked Operation (Synchronous) | 

Propagation Delay Time 

X PHL> 


5 

200 

ns 

t PLH 


10 

100 

Transition Time 

X JHL> 


5 

100 


*TLH 


10 

50 


Minimum Clock Pulse Width 

twL' 


5 

75 

ns 

X \NH 


10 

30 

Maximum Clock Rise 

t r CL, 


5 

15 


and Fall Time 

t f CL 


10 

5 


Setup Time 

tSUHL' 


5 

150 


tSULH 


10 

75 


Maximum Clock Frequency 

f CL 


5 

6 

MHz 

(Toggle Mode) 


10 

16 

Set and Reset Operation (Asynchronous) | 

Propagation Delay Time 

tPHLfR)' 


5 

175 


tPLH(S) 


10 

85 


Minimum Pulse Width 

%H( S)' 


5 

100 


t WH(R) 


10 

50 


Average Input Capacitance 

C| 

Any Input 

5 

pF 


387 





TOtEZE 

Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

Preliminary CD4098BE 



COS/MOS Dual Monostable 
Multivibrator 

R et r i ggera b I e/ R esetta b I e 
Features: 

■ Trigger propagation delays independent 
of R X' C X 

■ Triggering from leading or trailing edge 

■ Q and Q buffered outputs available 

■ Separate resets 

■ Wide range of output-pulse widths 

■ Equal source and sink currents 


Applications: 

■ Pulse delay and 
timing 

■ Pulse shaping 

■ Astable Multivibrator 


The RCA CD4098BE dual monostable multivibrator provides 
stable retriggerable/resettable one-shot operation for any fixed- 
voltage timing application. 

An external resistor (Rx) and an external capacitor (Cx) 
control the timing for the circuit. Adjustment of Rx and Cx 
provides a wide range of output pulse widths from the Q and Q 
terminals. The time delay from trigger input to output tran- 
sition (trigger propagation delay) is independent of Rx and C x . 

Leading-edge-triggering (+Tr) and trai ling-edge-triggering (— Tr) 
inputs are provided for triggering from either edge of an input 
pulse. An unused +Tr input should be tied to Vgs- An unused 
— Tr input should be tied to Vq[). A RESET (on low level) is 
provided for immediate termination of the output pulse or to 
prevent output pulses when power is turned on. An unused 
RESET input should be tied to Vqq. However, if an entire 

MAXIMUM RATINGS, Absolute-Maximum Values: 


STORAGE-TEMPERATURE RANGE -65 to +150 °C 

OPERATING-TEMPERATURE RANGE -40 to +85 °C 

DC SUPPLY-VOLTAGE RANGE 

V DD * -0.5 to +18 V 

DEVICE DISSIPATION (PER PKG.) 200 mW 

ALL INPUTS V ss <V, < V DD 


OPERATING CONDITIONS AT T A = 25°C 


For maximum reliability, nominal operating conditions should be 
selected so that operation is always within the following ranges. 


Characteristic 

V DD 

Min. 

Max. 

Units 

Fig. 

Supply Voltage Range 

- 

3 

18 

V 

- 

Input Voltage Swing 
(Recommended Vgg to Vqq) 


0.2 Vqq 
to 

0.8 Vqq 
(A ny one 
input) 

-0.5 V 

to 

V DD + 
0.5 V 

V 



* All voltage values are referenced to Vgg terminal. 


section of the CD4098BE is not used, its RESET should be tied 
to Vgs- See Table I. 

In normal operation, the circuit retriggers on the application 
of each new pulse. To prevent retriggering when leading-edge 
triggering is used, Q must be connected to — Tr. To prevent 
retriggering when trailing-edge triggering is used, Q must be 
connected to +Tr. 

The time period (T) for this multivibrator can be approximated 
by: T X = R X Cx* Time periods as a function of R x for values 
of C x and Vqq are given in Fig. 1. 

All outputs are independently buffered to provide equal 
source- and sink-current capabilities.TheCD4098BE is available 
in a 16-lead dual-in-line plastic package (CD4098BE). This 
device is similar to type MCI 4528. 



388 


8-74 



Preliminary CD4098BE 


TABLE I 


CD4098BE FUNCTIONAL TERMINAL CONNECTIONS 


FUNCTION 

TO Vpp 

TO V ss 

INPUT PULSE TO 

OTHER CONNECTIONS | 

MONO-] 

mono 2 

MONO-] 


MONO-, 









n 

12 



LEADING-EDGE 

TRIGGER/ 

NON-RETRIGGERABLE 

3 


■ 


n 


D 


TRAILING-EDGE 

TRIGGER/ 

RETRIGGERABLE 

3 

13 

n 

12 

5 

11 

■ 


TRAILING-EDGE 

TRIGGER/ 

NON-RETRIGGERABLE 

3 

13 




11 

D 



5 

11 

KOI 

12, 13 






NOTES: 

1. A RETRIGGERABLE ONE-SHOT MULTI- 
VIBRATOR HAS A TIME PERIOD T x 
REFERENCED FROM THE APPLICATION 
OF THE LAST INPUT PULSE. 

2. A NON-RETRIGGERABLE ONE-SHOT 
MULTIVIBRATOR HAS A TIME PERIOD 
T x REFERENCED FROM THE APPLICA- 
TION OF THE FIRST INPUT PULSE. 


INPUT PULSE TRAIN 


jiruuT 


RETRIGGERABLE MODE PULSE WIDTH 
(+TR MODE) 




NON-RETRIGGERABLE MODE PULSE 

WIDTH 

(+TR MODE) 


V DD V DD 



Fig. 2 — CD4098BE dual monostable multivibrator logic diagram. 


389 





















Preliminary CD4098BE 


STATIC ELECTRICAL CHARACTERISTICS at T A = 25°C 




TEST 

CHARACTERISTIC 

SYMBOL 

CONDITIONS 



v 0 

V DD 



VOLTS 

VOLTS 

Quiescent Device Current 

l L 


5 




10 

Quiescent Device Dissipation/ 

PD 


5 

Package 


10 


Noise Immunity (Any Input) 





Output Drive Current: 

i d n 

0.4 

5 

N-Channel (Sink) 

0.5 

10 




4.6 

5 

P-Channel (Source) 

'dp 

9.5 

10 



2.5 

5 



DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, C L = 50 pF, Input t r ,tf = 20 ns 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

V DD 

V 

TYPICAL VALUES 

UNITS 

R x (k£2) 

C x (pF) 

Trigger Propagation Delay Time 

+TR, -TR to Q, Q 

tpLH' 

tPHL 

5 

15 

5 

10 

350 

125 

ns 

10 

1000 

5 

10 

350 

125 

Minimum Trigger 

Pulse Width 


5 

15 

5 

10 

75 

30 

ns 


1000 

5 

10 

75 

30 

Transition Time 


5 

15 

5 

10 

100 

50 

ns 

10 

1000 


125 

75 

Reset Propagation Delay Time 

t PLH' 

t PHL 

5 

15 

5 

10 

400 

150 

ns 


1000 

5 

10 

1100 

700 

Minimum Reset Pulse Width 

%L 

5 

15 

5 

10 

50 

25 

ns 

10 

1000 

5 

10 

750 

500 

Average Input Capacitance 

C| 

Any Input 


5 

PF 


390 





















































































Preliminary CD4098BE 


APPLICATIONS 



Fig. 3 — Pulse delay. 

V DD v dd 



92CS-24257 

Fig. 4 — Astable multivibrator. 


391 








Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

Preliminary CD4099BE 


Preliminary Data* 



CD4099B Functional Diagram 


COS/MOS 8-Bit Addressable Latch 




MODE SELECTION | 

Write 

Disable 

Reset 

Addressed Latch 

Unaddressed Latch 

0 

0 

Follows Data 

Holds Previous State 

0 

1 

Follows Data 

Reset to "0" 

1 

0 

(Active High 8-Channel Demultiplexer) 
Holds Previous State 1 Holds Previous State 

1 

1 

Reset to "0" 

Reset to "0" 


MAXIMUM RATINGS, Absolute-Maximum Values: 


The RCA-CD4099B 8-bit addressable latch is a serial-input, 
parallel-output storage register that can perform a variety 
of functions. 

Data is input to a particular bit in the latch when that bit is 
addressed (by means of inputs AO, A1, A2) and when WRITE 
DISABLE is at a low level. When WRITE DISABLE is high, 
data entry is inhibited; however, all 8 outputs can be con- 
tinuously read independent of WRITE DISABLE and address 
inputs. 

A master RESET input is available, which resets all bits to a 
logic "0” level when RESET and WRITE DISABLE are at a 
high level. When RESET is at a high level, and WRITE DISABLE 
is at a low level, the latch acts as a 1-of-8 demultiplexer; the bit 
that is addressed has an active output which follows the data 
input, while all unaddressed bits are held to a logic "0" level. 

The CD4099B is supplied in a 16-lead dual-in-line plastic 
package (CD4099BE). 


STORAGE-TEMPERATURE RANGE -65 to +150°C 

OPERATING-TEMPERATURE RANGE -40 to +85 °C 

DC SUPPLY-VOLTAGE RANGE: 

(Vdd>* -0.5 to +18 V 

DEVICE DISSIPATION (PER PACKAGE) 200 mW 

ALL INPUTS V ss < V, < V QD 

LEAD TEMPERATURE (DURING SOLDERING) 

At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) 

from case for 10 s max +265°C 

* All voltage values are referenced to Vgs terminal. 

OPERATING CONDITIONS AT T A = 25°C 


For maximum reliability, nominal operating conditions should be 
selected so that operation is always within the following ranges. 


Characteristic 

V DD 

Min. 

Max. 

Units 

Fig. 

Supply Voltage Range 

- 

3 

18 

V 

- 

Input Voltage Swing 
(Recommended Vgg to Vqq) 


0.2 V DD 
to 

0.8 V DD 
(Any one 
input) 

-0.5 V 

to 

V DD + 
0.5 V 

V 




CHANGE FOR THE MINIMUM DURATION SPECIFIED BY tsETUP + 
♦HOLD- 


392 


9-74 







Preliminary CD4099BE 


STATIC ELECTRICAL CHARACTERISTICS at T A = 25°C 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

TYPICAL 

VALUES 

UNITS 


V 0 

Volts 

V D D 

Volts 

Quiescent Device 

Current 

'L 



5 

0.01 

HA 

10 

0.02 

Output Drive Current: 

N-Channel (Sink) 

i d n 

V| = v DD 

0.4 

5 

0.8 

mA 

0.5 

10 

1.8 




4.6 

5 

-0.8 


P-Channel (Source) 

l D p 

V| = v ss 

2.5 

5 

-3.2 

mA 




9.5 

!°_j 

-1.8 



DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, C L = 50 pF, Input t r ,tf = 20 ns 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

TYPICAL 

VALUES 

UNITS 



Q 3 
O o 
> > 

Propagation Delay: 

Data to Output 

t PLH' 

tPHL 

A0, A1, A2 Stable 

Write Disable, Reset = "0" 

© 

5 

200 

ns 

10 

85 

Write Disable 

to Output 


A0, A1, A2 Stable 

Reset = "0" 


5 

225 

10 

100 

Reset to Output 




5 

190 

10 

85 

Minimum Pulse Width: 

Data 

u 



5 

15 

ns 

10 

5 

Address 

twL« 

%H 



5 

0 

10 

0 

Reset 

*WH 


© 

5 

120 

10 

60 

Setup Time: 

Data to Write Disable 

*su 

A0, A1 , A2 Stable 

Reset = "0" 

© 

5 

235 

ns 

10 

105 

Write Disable 

to Address 

Reset = "0" 

© 

5 

80 

10 

35 

Hold Time: 

Address to Write Disable 

t HOLD 

Reset = "0" 

© 

5 

200 

ns 

10 

100 

Data to Write Disable 

t HOLD 

A0, A1 , A2 Stable 

Reset = "0" 

© 

5 

45 

10 

15 


*Circled numbers refer to times indicated on master timing diagram. 


393 











Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

Preliminary CD4502BE 



COS/MOS Strobed Hex Inverter/Buffer 

Special Features: 

■ 2-TTL-Load Output-Drive Capability 

■ 3-State Outputs 

■ Common Output-Disable Control 

■ Inhibit Control 

Applications: 

■ 3-State Hex Inverter for Interfacing IC's 

with Data Buses 

■ COS/MOS-to-TTL Hex Buffer 


RCA-CD4502B contains six inverter/buffers with 3-state out- 
puts. When the disable control input is at a logical 1, all six 
outputs become high impedance (> 10 M£2). This feature sim- 
plifies design by allowing common bussing of the outputs. 

The CD4502B is also provided with an inhibit control which, 
when at logical 1, switches all six outputs to logical 0. 

The CD4502B is supplied in a 16-lead dual-in-line plastic 
package (CD4502BE). 

This device is similar to type MCI 4502. 

OPERATING CONDITIONS AT T A = 25°C 


For maximum reliability, nominal operating conditions should be 
selected so that operation is always within the following ranges. 


Characteristic 

V DD 

Min. 

Max. 

Units 

Fig. 

Supply Voltage Range 

- 

3 

18 

V 

- 

Input Voltage Swing 
(Recommended Vgg to Vpp) 


0.2 Vpp 
to 

0.8 Vpp 
(Any one 
input) 

-0.5 V 

to 

V DD + 
0.5 V 

V 



MAXIMUM RATINGS, Absolute-Maximum Values: 


STORAGE-TEMPERATURE RANGE -65 to +150°C 

OPERATING-TEMPERATURE RANGE: 

CERAMIC-PACKAGE TYPES -55to+125°C 

PLASTIC-PACKAGE TYPES -40 to +85 °C 

DC SUPPLY-VOLTAGE RANGE 

V DD * -0.5 to +18 V 

DEVICE DISSIPATION (PER PACKAGE) 200 mW 

LEAD TEMPERATURE (DURING SOLDERING): 

At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) 

from case for 10 seconds max 265°C 


* All voltage values are referenced to Vgg terminal. 




394 


6-74 







Preliminary CD4502BE 


STATIC ELECTRICAL CHARACTERISTICS AT Ta = 25°C 
















Preliminary CD4502BE 



CHARACTERISTIC 

SYMBOL 

Data or Inhibit 

Delay Times: 

High to Low 

*PHL 

Low to High 

*PLH 

Disable Delay Times: 

Output 1 to 

High Impedance 

tl-H 

High Impedance 
to Output 1 

tH-1 

Output 0 to 

High Impedance 

tO-H 

High Impedance 
to Output 0 

tH-0 

Transition Times: 


Low to High 

tTLH 

High to Low 

tTHL 

Average Input Capacitance 

C| 


CHARACTERISTIC CURVES 
AND TEST CIRCUITS 
Fig. No. 















































Preliminary CD4502BE 



92CS-24I00 


Fig. 4 — Typical n-channel drain characteristics. 


DRAIN -TO -SOURCE VOLTAGE (V os )-V 
M5 -1 0 -5 0 


AMBIENT TEMPERATURE IT. I = ?5*C 

TT 

-- 

- 



- 

T 

- 



A 









__ 















+++ 


AG 

-M 

4 



4- 

I 

* 




• 5 1 










t iv GS )--- 









— 




~r 

TT 


- 




































a 














4 

TT 

44 

-- 

— 














:: 



::: 




it 

id: 

XJ 

:: 

: 























i 

V 

.4 

* 




= 





2T 

Ui 


t MAXIMUM 

package: 





:: 






it 








DISSIPATION - 200 mW} 




— 

+ 

“ 




-- 





I z 








__L 

TT 

c 












II 





- -20 <c 





T* 



Tr 

TT 

t 









:: 


II 





ce 

o 





-H 




15 

V 







- 









_J 














s: 

_ 









- -25 z 





-- 




--- 

















r 








__ 



_ 





. 


I 


1 1 


_ _ 





<i 

X 





- J 




— 







* J 










I -3o , 





__ 






„ 






ii 

_ 


II 


I _ 




II' 






;r 




::: 

I 





II 

:i 

I 


II 


II 




Ii; 

: 





— 



-- 

--- 

- 





x 

x 



x 


x 


-jz: 


X! 

- 


92CS- 24 320 

Fig. 8— Typical output-P-channel drain characteristics. 


397 




Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

Preliminary CD4511BE 



The RCA-CD4511B is a BCD-to-Seven-Segment Latch Decoder 
Driver constructed with COS/MOS logic and n-p-n bipolar 
transistor output drivers on a single monolithic structure. This 
device combines the low quiescent power dissipation and high 
noise immunity features of RCA COS/MOS with n-p-n bipolar 
output transistors capable of sourcing up to 25 mA. This 
capability allows the CD4511B to drive LED's and other 
displays directly. 


Lamp Test (LT) Blanking (Bl) and Latch Enable (LE) inputs 
are provided to test the display, shut off or intensity modulate 
it, and store a BCD code, respectively. Several different 
signals may be multiplexed and displayed when external 
multiplexing circuitry is used. 

The CD4511B is supplied in a 16-lead dual-in-line plastic 
package (CD4511BE). 

This device is similar to type MC14511. 


MAXIMUM RATINGS, Absolute-Maximum Values: 

STORAGE-TEMPERATURE RANGE -65 to +150°C 

OPERATING-TEMPERATURE RANGE -40 to +85 °C 

DC SUPPLY-VOLTAGE RANGE 

V DD * -0.5 to +18 V 

MAXIMUM CONTINUOUS OUTPUT 

DRIVE CURRENT/OUTPUT 25 mA 

MAXIMUM CONTINUOUS OUTPUT 

POWER/OUTPUT 50 mW 

ALL INPUTS < V, < V DD 

LEAD TEMPERATURE (DURING SOLDERING): 

At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) 

from case for 10 seconds max 265°C 

* All voltage values are referenced to V SS terminal. 


OPERATING CONDITIONS AT T A = 25°C 


For maximum reliability, nominal operating conditions should be 
selected so that operation is always within the following ranges. 


Characteristic 

V DD 

Min. 

Max. 

Units 

Fig. 

Supply Voltage Range 

- 

3 

18 

V 

- 

Input Voltage Swing 
(Recommended Vgg to Vqq) 


0.2 V DD 
to 

0.8 V DD 
(Any one 
input) 

-0.5 V 

to 

V DD + 
0.5 V 

V 



398 


9-74 







Preliminary CD4511B 


STATIC ELECTRICAL CHARACTERISTICS AT T A = 25°C 




TEST CONDITIONS 



CHARACTERISTIC 

SYMBOL 

•oh 

mA 

v OL 

V 

V DD 

V 

TYPICAL VALUES 

UNITS 

Quiescent Device Current 




5 

5 

nA 

'l 



10 

10 

Output Drive Voltage 


0 


5 

4.5 




10 


5 

4.1 


High-Level (Source) 

V OH 

25 


5 

3.5 


0 


10 

9.5 

V 



10 


10 

9.1 




25 


10 

8.7 


Output Drive Current 

'OL 


0.4 

5 

0.8 

mA 

(Sink) 


0.5 

10 

2 


DYNAMIC ELECTRICAL CHARACTERISTICS AT T A = 25°C, C L = 15 pF, Input t r ,tf = 20 ns 




TEST CONDITIONS 



CHARACTERISTIC 

SYMBOL 


Q > 
> 

TYPICAL VALUES 

UNITS 

Propagation Delay: 



5 

720 


High-to-Low 

tpHL 


10 

290 


Low-to-High 

tPLH 


5 

640 



10 

250 


Transition Time: 

*THL 


5 

30 


High-to-Low 


10 

17 

ns 

Low-to-High 

*TLH 


5 

1000 


10 

1000 


Setup Time 

l SU 


5 

90 

ns 


10 

38 

Hold Time 

tHOLD 


5 

-90 



10 

-38 

ns 

Minimum Latch Enable 

tyy(LE) 


5 

260 

ns 

Pulse Width 


10 

110 

Average Input Capacitance 

C| 

Any Input 


5 

pF 


399 





Preliminary CD451 IB 


TRUTH TABLE 

LEBILTDCBAabcdefg Display 

XX0XXXX11 11111 Q 

X 0 1 XXX X 00 00000 Blank 

0 1 1 00001111110 

0 1 1 0001 0110000 I 

0 1 1 00101101101 |p 

0 1 1 0011 1111001 ^ 

0 1 1 01000110011 if 

0 1 1 0101 1011011 £ 

0 1 1 01100011111 

0 1 1 0111 1110000 

0 1 1 10001111111 

0 1 1 1001 11 10011^ 

0 1 1 1010 0000000 Blank 

0 11 101 1 0000000 Blank 

0 T 1 1 100 0000000 Blank 

0 1 1 1 101 0000000 Blank 

0 1 1 1110 0000000 Blank 

0 1 1 111 1 0000000 Blank 

1 1 1 X X X X 

X = Don't Care ^Depends on BCD code previously 

applied when LE = 0 

Note: Display is blank for all illegal input codes (BCD > 1001). 


OUTPUT 

f PHL - 


DYNAMIC WAVEFORMS 


V 90% 

\ 50% 

\ 10% c 

■u. *tlh 

Jjf 90% 

r / 50% 

S r ^4- 10 % 


10% J /j 
- 1 su-+- t i 


OUTPUT _ 
LE (STROBED) — 


/ 

/‘ / F0R HOLD 


t — s 

P — tw(LE) — *| 


400 




File No. 814 



Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4514B Types 
CD4515B Types 



COS/MOS 4-Bit Latch/4-to-16 
Line Decoder 

CD4514B Output "High" on Select 
CD4515B Output "Low" on Select 


Features: 

■ Strobed input latch 
n Inhibit control 


The RCA-CD4514 B a and -CD4515B A are monolithic integrated 
circuits consisting of a 4-bit strobed latch and a 4-to-16- 
line decoder. The latches hold the last input data presented 
prior to the strobe transition from 1 to 0. Inhibit control 
allows all outputs to be placed at 0 (CD4514B) or 1 (CD4515B) 
regardless of the state of the data or strobe inputs. 

The decode truth table indicates all combinations of data 
inputs and appropriate selected outputs. 

These devices are supplied in 24-lead ceramic packages. They 
are also available in chip form. These devices are similar to 
the types MC14514 and MC14515. 

A Formerly CD4064A and CD4065A, respectively. 


MAXIMUM RATINGS, Absolute-Maximum Values: 

STORAGE-TEMPERATURE RANGE -65to+150°C 

OPERATING-TEMPERATURE RANGE -55to+125°C 

DC SUPPLY-VOLTAGE RANGE 

V DD * -0.5 to +18 V 

DEVICE DISSIPATION (PER PACKAGE) 200 mW 

ALL INPUTS V ss < V| < V DD 

LEAD TEMPERATURE (DURING SOLDERING): 

At distance 1/16 ± 1/32 inch (1 .59 ± 0.79 mm) 

from case for 1 0 seconds max 265°C 

* All voltage values are referenced to Vgg terminal. 


Applications: 

° Digital multiplexing 
n Address decoding 
a Hexadecimal/BCD decoding 
n Program-counter decoding 
n Control decoder 


DECODE TRUTH TABLE (Strobe = 1) 


INHIBIT 

DATA INPUTS 

SELECTED OUTPUT 
CD4514B = Logic 1 (High) 
CD4515B = Logic 0 (Low) 

D 

c 

B 

A 

0 

0 

0 

0 

0 

SO 

0 

0 

0 

0 

1 

SI 

0 

0 

0 

1 

0 

S2 

0 

0 

0 

1 

1 

S3 

0 

0 

1 

0 

0 

S4 

0 

0 

1 

0 

1 

S5 

0 

0 

1 

1 

0 

S6 

0 

0 

1 

1 

1 

S7 

0 

1 

0 

0 

0 

S8 

0 

1 

0 

0 

1 

S9 

0 

1 

0 

1 

0 

S10 

0 

1 

0 

1 

1 

S11 

0 

1 

1 

0 

0 

SI 2 

0 

1 

1 

0 

1 

Si 3 

0 

1 

1 

1 

0 

S14 

0 

1 

1 

1 

1 

SI 5 





x 

All Outputs = 0, CD4514B 

1 





All Outputs = 1 , CD451 5B 


X = Don't Care 


8-74 


401 





CD4514B, CD4515B 

OPERATING CONDITIONS AT T A = 25°C 


For maximum reliability, nominal operating conditions should be 
selected so that operation is always within the following ranges. 


Characteristic 

V DD 

Min. 

Max. 

Units 

Fig. 

j Supply Voltage Range 

- 

3 

18 

V 

- 

Input Voltage Swing 

- 

0.2 V DD 

-0.5 V 

V 

- 

(Recommended Vgg to Vqq) 


to 

to 




0.8 V DD 

V DD + 





(Any one 

0.5 V 





input) 




Setup Time 

5 

250 

None 

ns 

A 


10 

100 




Strobe Pulse Width 

5 

350 

None 

ns 

A 


10 

100 





File No. 814 



92CS-24598 


Fig. A— Waveforms for setup time and strobe pulse width. 



Fig. 1— Logic diagram for CD4514B and CD45 15B. 


402 





File No. 814 


CD4514B, CD4515B 


STATIC ELECTRICAL CHARACTERISTICS 


CHARAC- 

TERISTIC 

SYMBOL 

TEST 

CONDI- 

TIONS 

CERAMIC PACKAGE LIMITS 

UNITS 

FIG. 

NO. 

> 

O 

> 

VDD 

V 

— 55°C 

25°C 

125°C 


rr 


ESS 


E2Q| 

Typ. 

E2JS 


Pfi 


Quiescent Device 
Current 

n 

1 

1 

5 

- 

- 

mm 

- 

K&Sm 

5 

- 

_ 

300 


3 

10 

- 

- 

■El 

- 


mm 

- 

- 

Whim 

IB 

- 

- 


- 



- 

B 


Output Voltage 
Low-Level 

VOL 

■ 

1 

5 

- 

- 

Eg 

- 

0 

Mu ■ 

- 

B 

EEI 


1 

wm 

- 

- 


- 

0 

eh 

- 

- 

EH 

wm 

- 

- 

- 

- 

0 

- 

- 

- 

- 

High-Level 


■ 

1 

5 

wm 

- 

- 


5 

- 

KE3 

- 

_ 

EES 

K 

- 

- 

ram 

10 

- 

EOl 

- 

- 

i m 

- 

- 

- 

- 

15 

- 

- 

- 

- 

Noise Immunity 
Any Input 

m 

EB 

m 

5 

mm 

_ 

- 

IB 

2.25 

- 

mm 

- 

- 


1 


9 

mm 

3 

- 

- 

3 

mm 

- 

m ei 

- 

- 



IB 

- 

- 

- 

- 

ES9I 

- 

- 

- 

- 

VNH 

m 

m 

5 

mm 

- 

- 

KB 

Ksm 

- 

mm 

- 

- 

mm 

i 

wm 

o 

- 

- 

3 

4.5 

- 

3 

- 

- 

dQ 

m 

IB 

- 

- 

- 

- 


- 

- 

- 

- 

Output Drive 
Current: 

N-Channel 

(Sink) 

IdN 


1 


« 

■ 

0.4 

0.8 


0.3 



mA 

4, 7. 8 

0.5 

IB 

i.i 

- 

- 

0.9 

2 

- 


- 

- 

1.5 

15 

- 

- 

- 

- 

mm 



- 

- 

P-Channel 

(Source) 

«dp 

4.6 

5 


- 

- 

B*M 

Bl 

- 

nm 

- 

- 


4, 9.10 

2.5 

5 


- 

- 

CEJ 

mm 

- 


- 

- 

9.5 

■B 


- 

- 


EEI 

- 

BHKEI 

- 

- 

13.5 

mm 


- 

- 

- 

EJsl 

- 

- 

- 

- 

Input Current 

■l 

Any Input 

Qj 


- 

- 

- 

±10-5 

±i 

- 

- 

- 

/iA 

- 


A For CD4514B 
• For CD4515B 




Fig. 2— Noise immunity test circuit. 


Fig. 3— Quiescent device current test circuit. 


403 



































CD4514B, CD4515B 


File No. 814 


DYNAMIC ELECTRICAL CHARACTERISTICS AT T A = 25°C; Input t r ,tf = 20 ns, C L = 50 pF 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

LIMITS 

UNITS 

CHARAC- 
TERISTIC 
CURVES & 

TEST CKTS. 
Fig. No. 


V DD 

Volts 

TYP. 

MAX. 

Propagation 

Delay Time: 

Strobe or Data 

tPHL' 

tPLH 


5 

550 

1100 

ns 

6, 11, 15 

10 

HB9I 

450 

15 

1 


Inhibit 

5 

400 

Bum 

6, 12 

10 

150 

300 

15 

100 

- 

Transition Time: 

High-to-Low 

l THL 


5 

100 

200 

ns 

6, 14 

10 

! 

50 

100 

15 

40 

80 

Low-to-High 

tTLH 


5 

200 

400 

6, 13 

10 

100 

200 

15 

80 

160 

Average Input Capacitance 

C l 

Any Input 

5 

- 

PF 

- 


V DD 


FOR CD45I4B 

I. FOR p-CHANNEL : 

INHIBIT = V SS AND Dl -D4 
CONSTITUTE BINARY CODE 
FOR "OUTPUT UNDER TEST 1 

2. FOR n -CHANNEL: 

INHIBIT = V 0D 


KD- 

®- 

®~ 

(H>— 


i 


12) V SS 




iJJ 


FOR CD45I5B 

. FOR p-CHANNEL: 

= V DD 


INHIBIT = 




2. FOR n-CHANNLL: 

INHIBIT - VgS AND DI-D4 
CONSTITUTE BINARY CODE 
FOR "OUTPUT UNDER TEST" 


EXTERNAL 

POWER 

SUPPLY 




Fig. 4— Drain characteristics test circuit. 


404 




























































15 








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rE 

bsk! 

|S!!*! 

>SSSSS8EI{38SSSS^L 

Bill 

iiiiiiiiiiiili 



mid 


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an 

■SIB 

BBBBiiiiBEIli 

IliiilBill 

m 

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iiiiiil 

mm\ 

iiiiiil 

IMMHW 

HBH 

II 

gli 

BHiiHHIiBiiiffli 

SSBSBi 

iiiii 

iliiiif 

iiiiiilifjl 

iiiii 

jjjjjjgjB 

il 

MISIS 

::::::: 

imtfKii 


m 

mwmm 

Iiiii! 

ilfiiii 

1SB 

MIBB 

1 

ijillipii! 

Ill 

liillii 

ttfljjgjl 

Hill 

i 

Hjjliiiiijil 

iiiiiii 

ilillll 







iiiiiil 





:::: 

iiiiiil 


Iiiiiiii 

:s!is:ixjSjs:ss |ii 

IHSSSIU^i Sk 
iKiSS in 

iii 

ijj 

is. 

iiiii!! 

iiiiiii 

iiiiiiii:: 

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mm 

mnwniiSii 

SS Hoi lilil 

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ysgiilliliihiiis 

riiiiliili 

m SpHu 

ill 


ill 

iiiiiiiii: 

Iiiii 

Wm 

iii 

Hi 

iii 

si: 

iiiiiii 

::::::: 

MIBB 

HB 

Hi 

Hill!! 1 

lifilliiiP 


1 

|i| 

111 

pli 

mfiSm 

liffliiSiiil' 

I 



jjjjjjjjjl 

iMnwfllliis 

Iliiiiliiiiii 

iiii 


Si 

lid 


Biiiiii 

BBiliH 

liililp 

mmM r 
BBBSPl I 

/ iu Si! * i 

11 

Iiiii 

11 

in il 

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:::::::: 

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iiiii 

iiiiiiii 

iiiaiiiii 

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mm 

iiiilEi 


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iiiiiiii 

SSSSZKfiSal 

lid 

M^iNiliilii 

1 1 iiii: 

ip 

ilB 

HlillBiliB 

ii iiiii 

iiiiiiii 

ROStSSS 
nil EO: 
shirks i 


LOAD CAPACITANCE (C L ) — pF 


PHI! 


HI 


Jiill 



iiiiiiii 


!ns:s:fl 

KISH!*? 


:::: 


iiii 




iiiiiiiiiiiiiiil 


iiiiiiiii iiiii iii;:| 


LOAD CAPACITANCE (C L )-pF 


Fig. 13— Typical low-to-high transition time 
vs. load capacitance. 


Fig. 14— Typical high-to-low transition time 
vs. load capacitance. 








File No. 808 



Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4518B Types 
CD4520B Types 



COS/MOS Dual Up Counters 

CD4518B Dual BCD Up Counter 
CD4520B Dual Binary Up Counter 
Features: 

■ Medium-speed operation — 6-MHz typical clock frequency at 10 V 

■ Positive- or negative-edge triggering 

■ Standard B-series output drive 

■ Synchronous internal carry propagation 

Applications: 

■ Multistage synchronous counting 

■ Multistage ripple counting 

■ Synchronous frequency dividers 


The RCA-CD4518B* Dual BCD Up Counter and CD4520B* 
Dual Binary Up Counter each consist of two identical, internally 
synchronous 4-stage counters. The counter stages are D-type 
flip-flops having interchangeable Clock and Enable lines for 
incrementing on either the positive-going or negative-going 
transition. For single-unit operation the Enable input is main- 
tained "high" and the counter advances on each positive-going 
transition of the Clock. The counters are cleared by high 
levels on their Reset lines. 

The counter can be cascaded in the ripple mode by connecting 
Q4 to the enable input of the subsequent counter while the 
clock input of the latter is held low. 

All outputs have equal source- and sink-current capabilities 
and conform to standard B-Series output drive (see Static Elec- 
trical Characteristics). 

The CD4518B and CD4520B are available in 16-lead dual-in- 
line plastic packages (E), dual-in-line welded-seal ceramic 
packages (D), dual-in-line ceramic packages (F), ceramic flat 
packs (K), and in chip form (H). 

These devices are similar to types MC14518 and MC14520. 
* Formerly CD4083A and CD4084A, respectively. 

MAXIMUM RATINGS, Absolute-Maximum Values: 


STORAGE-TEMPERATURE RANGE -65 to+150°C 

OPERATING-TEMPERATURE RANGE: 

CERAMIC-PACKAGE TYPES -55 to+125°C 

PLASTIC-PACKAGE TYPES -40 to +85 °C 

DC SUPPLY-VOLTAGE RANGE 

V DD ^ -0.5 to +18 V 

DEVICE DISSIPATION (PER PACKAGE) 200 mW 

LEAD TEMPERATURE (DURING SOLDERING): 

At distance 1/16 ± 1/32 inch (1 .59 ± 0.79 mm) 

from case for 10 seconds max 265°C 


A All voltage values are referenced to V 55 terminal. 


OPERATING CONDITIONS AT T A = 25°C 


For maximum reliability , nominal operating conditions should be 
selected so that operation is always within the following ranges. 


Characteristic 

V DD 

Min. 

Max. 

Units 

Fig. 

Supply Voltage Range 

- 

3 

18 

V 

- 

Input Voltage Swing 

- 

0.2 V DD 

-0.5 V 

V 

- 

(Recommended Vgg to V DD ) 


to 

to 




0.8 V DD 

V DD + 





(Any one 

0.5 V 





input) 





5 

440 




Enable Pulse Width 

10 

200 

None 

ns 

- 


15 

140 





5 

200 




Clock Pulse Width 

10 

100 

None 

ns 

- 


15 

70 





5 


1.5 



Clock Input Frequency 

10 

DC 

3 

MHz 

- 


15 


4 



Clock or Enable Input 

4-15 

None 

15 

ps 


Rise or Fall Time 



5 

250 




Reset Pulse Width 

10 

110 

None 

ns 

- 


15 

80 





8-74 


407 






CD4518B, CD4520B 

STATIC ELECTRICAL CHARACTERISTICS 


File No. 808 



N-Channel 

(Sink) 

P-Channel 

(Source) 


Input Current 


CHARACTERISTIC 

SYMBOL 

Propagation Delay Time: 

Clock or Enable 
to Output 

tpHD 

Reset to Output 

tPLH 

Transition Time 

tTHL- 

tTLH 

Average Input Capacitance 

C| 


25°C, I nput t r , tf = 20 ns, and C|_ = 50 pF 


CHARACTERISTIC 
CURVES & 
TEST CIRCUITS 
FIG. NO. 



408 



























File No. 808 


CD4518B, CD4520B 


STATIC ELECTRICAL CHARACTERISTICS 


CHARAC- 

SYMBOL 

TEST 

CONDI- 

TIONS 

CD4518BE, CP4520BE 

PLASTIC PACKAGE LIMITS 

UNITS 

FIG. 

TERISTIC 


vo 

VDD 

— 40°C ! 

25°C | 

85°C 1 


NO. 



Volts 

Volts 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 

Min. 

Typ. 

Max. 






5 

- 

- 

50 

- 

0.02 

50 

- 

- 

700 



Quiescent Device 
Current 

'l 


10 

- 

- 

100 

- 

0.02 

100 

- 

- 

1400 

pA 

16 




15 

- 

- 

- 

- 

0.02 

- 

- 

- 

- 






5 

- 

- 

0.01 

- 

0 

0.01 

- 

- 

0.05 



Output Voltager 

VOL 


10 

- 

- 

0.01 

- 

0 

0.01 

- 

- 

0.05 



Low-Level 



15 

- 

- 

- 


0 

- 

- 

- 

- 

\j 





5 

4.99 

- 

- 

4.99 

5 

- 

4.95 

- 

- 



High-Level 

Vqh 


10 

9.99 

- 

- 

9.99 

10 

- 

9.95 

- 

I 





P-Channel 

(Source) 


Input Current 



ALU INPUTS PROTECTED BY T | 

STANDARD COS/MOS PROTECTION ? 

NETWORK V S S 

Fig. 1 —Decade counter (CD4518B) logic diagram for 



19 













File No. 808 


CD4518B, CD4520B 


AMBIENT TEMPERATURE (T A )*25«CL 


-GATE- TO- SOURCE VOLTAGE (V GS )=i5V 


<1^;:-: | : •|qV : : : : | : : : : ( 


DRAIN -TO -SOURCE VOLTAGE (V DS )- 


AMBIENT TEMPERATURE (T A )x25»C 
I 1 | [|| - i |- GATE-TO-SOURCE VOLTAGE (V GS )*- 5 V 


I MAXIMUM PACKAGE TT 
-| DISSIPATION = 200 mwf 



DRAIN -TO -SOURCE VOLTAGE (V DS )-V 


Fig. 5— Minimum output-N-channel drain characteristics. 


Fig. 6— Typical output-P-channel drain characteristics. 


DRAIN -TO -SOURCE VOLTAGE (V DS )-V 


AMBIENT TEMPERATURE (T A ) = 25°CL 


' AMBIENT TEMPERATURE (T A ) = 25 e C t 


Tmr rm ttttt i t n ftt r - ht ti# - 2 

I GATE-TO-SOURCE VOLTAGE ( V GS )»- 5 V T~ ~ 





ifiiiiiiiB 


■miiiiiiiiignffl 



-CHANNEL DRAIN CURRENT (X D P)-mA 






CD4518B, CD4520B 


File No. 808 



Fig. 1 1— Typical power dissipation characteristics. 


V DD 



r»— 20 ns 


r 


i. 


h-20 ns 
V DD 


F \I0% 

VARIABLE ^ 


V SS 


WIDTH 

92CS-245IO 

Fig. 12— Power dissipation test circuit and waveform. 


CLOCK 



92CM-240II 

Fig. 13— Ripple cascading of four counters with positive-edge triggering. 


V DD 




92CM-245I2 

Fig. 14— Synchronous cascading of four binary counters with negative-edge triggering. 


Fig. 15— Noise immunity test circuit. 



Fig. 16— Quiescent device current 
test circuit. 


412 








COS/MOS BCD Rate Multiplier 


BCD 

RATE 

SELECT- 

INPUTS ,-STROBE 


T 10 

RATE 

c 

■*“ SELECT 

u 

LOGIC 

N 

T 


E 


R 

— ► "9" OUT 


CD4527B Functional Diagram 


The RCA-CD4527B is a low-power 4-bit digital rate multiplier 
that provides an output-pulse rate which is the clock-input- 
pulse rate multiplied by 1/10 times the BCD input. For 
example, when the BCD input is 8, there will be 8 output 
pulses for every 10 input pulses. This device may be used to 
perform arithmetic operations (add, subtract, divide, raise to a 
power), solve algebraic and differential equations, generate 
natural logarithms and trigonometric functions, A/D and D/A 
conversion, and frequency division. 


For fractional multipliers with more than one digit, CD4527B 
devices may be cascaded in two different modes: the Add 
mode and the Multiply mode. See Figs. 3 and 4. In the Add 
mode, 

Output Rate = (Clock Rate) 

(0.1 BCD-j +0.01 BCD 2 + 0.001 BCD 3 + • • •.). 

In the Multiply mode, the fraction programmed into the first 
rate multiplier is multiplied by the fraction programmed into 
the second one, g ^ 20 

e.g. — x — = — , or 36 output 
10 10 100 

pulses for every 100 clock input pulses. 


MAXIMUM RATINGS, Absolute-Maximum Values: 

STORAGE-TEMPERATURE RANGE -65 to +150°C 

OPERATING-TEMPERATURE RANGE -40 to +85 °C 

DC SUPPLY-VOLTAGE RANGE 

V DD * -0.5 to +18 V 

DEVICE DISSIPATION (PER PACKAGE) 200 mW 

ALL INPUTS V ss < V, < V DD 

LEAD TEMPERATURE (DURING SOLDERING): 

At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) 

from case for 10 seconds max 265°C 


OPERATING CONDITIONS AT T A = 25°C 

For maximum reliability, nominal operating conditions should be 
selected so that operation is always within the following ranges. 

F Characteristic [ Vppl Min. I Max. I Units I Fig. ] 


Characteristic 

V DD 

Min. 

Max. 

Supply Voltage Range 

- 

3 

18 

Input Voltage Swing 

- 

0.2 V DD 

-0.5 V 

(Recommended Vgg to Vpp) 


to 

to 


0.8 V DD 

+ 

O 

O 

> 



(Any one 

0.5 V 


* All voltage values are referenced to V ss terminal. 


9-74 


413 




Preliminary CD4527B 


TRUTH TABLE 


Number of Pulses 


Output Logic Level 
(H or L) 


No. of 

Clock Pulses lnh|ty Strobe 



Output same as the first 16 lines of this truth table (depending on values of A, B, C, D). 


STATIC ELECTRICAL CHARACTERISTICS AT Ta = 25°C 



Output Drive Current: 
All Outputs 

N-Channel (Sink) 


P-Channel (Source) 


































































































Preliminary CD4527B 


01234567890 1234 

clmk fuuinniinjinnnimnii 

00 _n_n TUI TLTL 

°° _J L_ 

_rL_n_ 

ot n 

n n_ 

Qd |”" 

— i r 

r , f~j_ 

n. 

R2 n 

ji n 

r5 Jiii_ruT_nji 

" — LT 

OUTPUT (PIN 6) n 

A ENABLED 1 1 

— u — LT 
n 

B ENABLED [~| 

n n 

C ENABLED |*| [“j 

juinn 

° enabled nnnn nnnn n nn n 

INH- OUT 

u 

OUPUT (PIN 6) H 

! n 

(PRESET No- OF 2) J“j 

n | n 

(PRESET No- OF 3) fl f) 

n| nil 

(PRESET No- OF 4) f]X! 

_n_ri_o_ 


,p " EsET * ° f 51 _n_fin_n_n n_n_ 

(PRESET Na OF 6) f] fl fl fl 1111 11 FI FI 

(PRESET No- OF 7) _fumjuinrUum 

(PRESET No- OF 8) Jinniuinniuiniu^ 
(PRESET No- OF 9) jinjuuiMuuinniL 

i 

| 92CM-249I5 

Fig. 2-Timing diagram. 


MOST SIGNIFICANT 
DIGIT 


LEAST SIGNIFICANT 
DIGIT 



0 I 234567890 I 234567890 

CLOCK 

0 r©-JLTUl^^ 

ONE OF FOUR OUTPUT PULSES CONTRIBUTED BY / 
DRM @ TO OUTPUT FOR EVERY 100 CLOCK PULSES 
IN FOR PRESET No- 94 

92CS-249IT 


Fig. 3— Two CD4527B's cascaded in the "Add" mode 
with a preset number of 94. 



Fig. 4 -Two CD4527B's cascaded in the "Multiply" mode 
with a preset number of 36. 


416 








Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

Preliminary CD4532BE 



The RCA-CD4532B consists of combinational logic that 
encodes the highest priority input (D7-D0) to a 3-bit binary 
code. The eight inputs, D7 through DO, each have an assigned 
priority; D7 is the highest priority and DO is the lowest. The 
priority encoder is inhibited when the chip-enable input E| is 
low. When E| is high, the binary representation of the highest- 
priority input appears on output lines Q2-Q0, and the group 


MAXIMUM RATINGS, Absolute-Maximum Values: 

STORAGE-TEMPERATURE RANGE -65 to +150°C 

OPERATING-TEMPERATURE RANGE. 1 -40 to +85 °C 

DC SUPPLY-VOLTAGE RANGE: 

(V DD *) -0.5 to +18 V 

DEVICE DISSIPATION (PER PACKAGE) 200 mW 

ALL INPUTS V ss < V, < V DD 

LEAD TEMPERATURE (DURING SOLDERING) 

At distance 1/16 ± 1/32 in. (1 .59 ± 0.79 mm) 

from case for 10 s max +265°C 

* All voltage values are referenced to Vgg terminal. 


select line GS is high to indicate that priority inputs are 
present. The enable-out (Eg) is high when no priority inputs 
are present. 

The CD4532B is available in the 16-lead dual-in-line plastic 
package (CD4532BE). 

This device is similar to type MC14532. 

OPERATING CONDITIONS AT T A = 25°C 


For maximum reliability, nominal operating conditions should be 
selected so that operation is always within the following ranges. 


Characteristic 

V DD 

Min. 

Max. 

Units 

Fig. 

Supply Voltage Range 

- 

3 

18 

V 

- 

Input Voltage Swing 
(Recommended Vgg to V DD ) 


0 2 V DD 
to 

0.8 V DD 
(Any one 
input) 

-0.5 V 

to 

V DD + 
0.5 V 

V 



TRUTH TABLE 


Input | 

Output | 

E| 

D7 

D6 

D5 

D4 

D3 

D2 

D1 

DO 

GS 

Q2 

Q1 

Q0 

EO 

0 

X 

X 

X 

X 

X 

X 

X 

X 

0 

0 

0 

0 

0 

1 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

1 

1 

1 

X 


X 

X 

X 

X 

X 

1 

1 

1 

1 

0 

mm 


1 






X 

■■ 

MM 




m 


0 






X 

H 

■■ 




H 


0 






X 

mm 

11 




i 

0 

0 

0 


1 

X 


X 

i 

0 

1 

1 

0 

i 

0 

0 

0 

0 

0 

1 


X 

i 

0 

1 

0 

0 

i 

0 

0 

0 

0 

0 



X 

i 

0 

0 

1 

0 

i 

0 

0 

0 

0 

0 



1 

i 

0 

0 

0 

0 


X = Don't Care Logic 1= High Logic 0 = Low 


8-74 


417 








Preliminary CD4532BE 


STATIC ELECTRICAL CHARACTERISTICS AT T A = 25°C 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

TYPICAL VALUES 

UNITS 



v 0 

Volts 

V DD 

Volts 



Quiescent Device Current 




5 

0.02 

HA 

'L 



10 

0.02 

Output Drive Current: 

N-Channel (Sink) 

i d n 


0.4 

5 

0.8 



0.5 

10 

1.8 

mA 




4.6 

5 

-0.8 

P-Channel (Source) 

'dP 


2.5 

5 

-3.2 





9.5 

10 

-1.8 



DYNAMIC ELECTRICAL CHARACTERISTICS AT T A = 25°C; C L = 15 pF, Input t r ,tf = 20 ns 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

V DD 

Volts 

TYPICAL VALUES 

UNITS 

Propagation Delay Time: 

E| to Eq 


5 

150 



10 

80 


Ej to GS 


5 

120 


t PHL' 

t PLH 

10 

60 

ns 

E| to Qn 

5 

225 

10 

110 


Dn to Qn 


5 

250 



10 

120 


Dn to GS 


5 

225 



10 

100 


Transition Time 

tTHL' 

5 

60 

ns 

tTLH 

10 

30 


For Operating and Handling Considerations, see RCA Application Note ICAN-6000. 


418 












File No. 858 



Solid State 
Division 


Digital Integrated Circuits 

Monolithic Silicon 

CD4555B Types 
CD4556B Types 


COS/MOS Dual Binary to 1 of 4 
Decoder/Demultiplexers 

CD45555: Outputs High on Select 
CD4556B: Outputs Low on Select 
Features: 

■ Standard "B" series output drive 

■ Expandable with multiple packages 


Applications: 

■ Decoding ■ Code conversion ■ Function selection 

■ Demultiplexing (using Enable input as a data input) 

■ Memory chip-enable selection 

The RCA-CD4555B and CD4556B* are dual one-of-four de- 
coders/demultiplexers. Each decoder has two select inputs 
(A and B), an Enable input (E), and four mutually exclusive 
outputs. On the CD4555B the outputs are high on select; 
on the CD4556B the outputs are low on select. 

When the Enable input is high, the outputs of the CD4555B 
remain low and the outputs of the CD4556B remain high 
regardless of the state of the select inputs A and B. All 
outputs have equal source- and sink-current capabilities and 
conform to standard "B" series output drive (see Static 
Electrical Characteristics). The CD4555B and CD4556B are 
similar to types MCI 4555 and MCI 4556, respectively. 

These devices are supplied in 16-lead dual-in-line plastic 
packages (E), welded-seal ceramic packages (D), ceramic 
packages (F), ceramic flat packs (K), and in chip form (H). 

* Formerly CD4091A & CD4092A, respectively. 


MAXIMUM RATINGS, Absolute-Maximum Values: 

STORAGE-TEMPERATURE RANGE -65 to +150°C 

OPERATING-TEMPERATURE RANGE: 

CERAMIC-PACKAGE TYPES -55 to +125°C 

PLASTIC-PACKAGE TYPES -40 to +85 °C 

DC SUPPLY-VOLTAGE RANGE 

V DD * -0.5 to +18 V 

DEVICE DISSIPATION (PER PACKAGE) 200 mW 

ALL INPUTS V ss < V l ^ V DD 

LEAD TEMPERATURE (DURING SOLDERING): 

At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) 

from case for 1 0 seconds max 265°C 

* All voltage values are referenced to V 55 terminal. 



[a \r~ 

Vss v ss 

CD4555B CD4556B 


92CS- 24220 


Functional Diagrams 


TRUTH TABLE 


INPUTS 

OUTPUTS 

CD4555B 

OUTPUTS 

CD4556B 

ENABLE 

SELECT 

WBM 

B 

D 

133 

El 

m 

□ 

03 

02 

oT 

QO 


D 


a 

a 

a 

1 

1 

1 

1 

0 


D 

D 

D 

a 

n 

0 

1 

1 

0 

1 



D 

a 

- 


0 

1 

0 

1 

1 


fl 

m 

m 

a 

D 

0 

0 

1 

1 

1 

WKM 

D 

D 

D 

D 

D 

~0~ 

1 

1 

1 

1 


X = DON’T CARE LOGIC 1 = HIGH 

LOGIC 0 = LOW 


OPERATING CONDITIONS AT T A = 25°C 


For maximum reliability, nominal operating conditions should be 
selected so that operation is always within the following ranges. 


Characteristic 

V DD 

Min. 

Max. 

Units 

Fig. 

Supply Voltage Range 

- 

3 

18 

V 

- 

Input Voltage Swing 
(Recommended Vgg to Vpp) 


0-2 V DD 
to 

0.8 V DD 
(Any one 
input) 

-0.5 V 

to 

V DD + 
0.5 V 

V 



9-74 


419 









TEST 

CONDI- 

CHARAC- sYMROI TIONS 

TER,ST,C V 0 I vbo 

Volts Volts 


Quiescent Device 
Current 


Output Voltage 
Low-Level 


High-Level 


CD4555BD, BF, BK, BH CD4556BD, BF, BK, BH 

CERAMIC PACKAGE LIMITS 


125°C 


Typ. 



BH 

H 


— 

yH 

ESI 

OB 


mm 

BEES HI 



ESI 

\mmmm 


■ 


HI 


HU 



wm 

■ 



EES! 

IH 

Bl 

bei 

HI ■□HEED 

Hi 

he 

eh 


Hi 

B 

HBH 


HEP 



ieesii 


Noise Immunity 
(Any Input) 


I BUI 


Output Drive 
Current: 

N-Channel 

(Sink) 



EWI] 





























File No. 858 


CD4555B, CD4556B 


STATIC ELECTRICAL CHARACTERISTICS 


CHARAC- 

TERISTIC 

SYMBOL 

TEST 

CONDI- 

TIONS 

CD4555BE, CD4556BE 

PLASTIC PACKAGE LIMITS 

UNITS 

FIG. 

NO. 


vo 

Volts 


— 40°C 

25°C 

85°C 


El 

U22SI 

I22j 

Esai 

■2H 


B33I 

Eg 


D 

■ 

5 

- 

- 


nj| ; 

SEEM 


- 

- 

700 

JiA 

15 

■a 

- 

- 

ITiTili 

- 

BS 


- 

■ 

lEHIf 

■a 

- 

- 

- 

- 

mm 

- 

- 

- 

- 

Output Voltage: 
Low-Level 

V 0 L 

■ 

mm 

- 

- 

w 

_ 

0 

BTiTi 

- 

- 

SB3 

V 

1 

ma 

- 

- 

EES 

- 

0 

TO 

- 

- 

Esa 

mm 

- 

- 

- 

- 

0 

- 

- 

- 

- 

High-Level 

v OH 

■ 

5 

HEI 

- 

- 


5 

- 


- 

- 

KB 



- 


■01 

- 

HE3I 

- 

- 

MM 

- 

- 

- 

- 

15 

- 

- 

- 

- 

Noise Immunity 
(Any Input) 

vnl 

EQI 

5 

mm 

- 

- 

IB 

9 

- 

mm 

- 

- 

1 

16, 17 

9 

m 

3 

- 

- 

ms 

mam 

- 

wm 

- 

- 

mn 

■a 

- 

- 

- 

- 

esei 

- 

- 

- 

- 

vnh 


5 

msa 

- 

- 

KQ 

B&B 

- 

■a 

- 

- 

i 

mm 

mms 

- 

- 

3 

BEOS 

- 

3 

- 

- 

■a 

■a 

~ 

- 

- 

- 

■so 

- 

- 

- 

- 

Output Drive 
Current: 

N-Channel 

(Sink) 

IdN 

0.4 

5 

0.45 

■ 

■ 

0.4 

0.8 

■ 

0.36 

■ 

■ 

1 

1 

B3E 

ma 

1 

- 

- 


1.8 


eeh 




15 

- 

- 

- 

□I 

6 

- 


B 

E 

P-Channel 

(Source) 

IdP 

03 


BO 

- 

- 

HO 

ISO 

- 

mi 


- 

mA 

■ 

tm 

EB 


- 

- 

BEH 

-0.8 

- 

iEEEI 


~ 

EU3I[ 

mm 

BOH 

- 

- 

Hilii 

-1.8 

- 

EEE3 


- 

IBM 

mm 

■SB 

- 

- 

El 

IHOI 

- 

- 

- 

- 

Input Current 

'l 

l: 

1 15 


- 

- 

- 

±10-5 

±1 

- 

- 

- 

ma 

- 


DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Input t r . tf = 20 ns, and C L = 50 pF 


CHARACTERISTIC 

SYMBOL 

TEST CONDITIONS 

ALL TYPES 
LIMITS 

UNITS 

CHARACTERISTIC 
CURVES & 

TEST CIRCUITS 
FIG. NO. 


V DD 

Volts 

Typ. 

Max. 

Propagation Delay Time: 



5 

220 

440 



A or B Input to 



10 

95 

190 

ns 

7,9, 19, 20 

Any Output 

tPHL- 


15 

70 

140 




*PLH 


5 

200 

400 



E Input to Any 



10 

85 

170 

ns 

8. 9, 19, 20 

Output 



15 

65 

130 




*THL 


5 

100 




Transition Time 



10 

50 


ns 

10 


*TLH 


15 

40 

B b 



Average input Capacitance 

C| 

Any Input 

5 

■ 

pF 



421 




















































CD4555B, CD4556B 


File No. 858 


DRAIN -TO -SOURCE VOLTAGE (V os )-V 

rJ5 -io -5 

AMBIENT TEMPERATURE (T A )=25°C I II ZI 1 1 it 1 1! 
:IIIIIII:GATE-T0-S0URCE VOLTAGE (V gs )=-5V;; 


DRAIN -TO -SOURCE VOLTAGE (V DS )-V 

H5 -10 -S 

AMBIENT TEMPERATURE (T A ).25«C III IIIII II II! 

ti h h 1 1 n ffff 1 1 1 1 i 1 1 1 1 1 1 1 1 Hiltttt ttt 

IIIIIIIIi: GATE-TO-SOURCE VOLTAGE (Vgs)— 5 V;; 


: MAX I MUM PACKAGE TT 
-{DISSIPATION = 200 mWf 










File No. 858 


CD4555B, CD4556B 



AMBIENT TEMPERATURE (Tft )»25 *c[ 111 111 [1 1 [-L1.1 1 1 U-IJ 



■■■■ 

■■■■ 

ssss 

asss 

■■■■ 


sssssssasss 

■■■■■■■■■■■■a ■■■■■■■ 
aaaaaaaaaaaaa BBaaaaa 
aaaaaaaaaaaaa aaaaaaa 

■•■■■■■■■•■■a ■■•■■■■ 


■SSECDCES 

Jaaaaaaaaaaaa aaaaaaa 

aaaaaaaaaaaaa aaaaaaa 
aaaaaaaaaaaaa aaaaaaa 
aaaaaaaaaaaaa aaaaaaa 

ssssnaasae^^sssss: 

aaaaaaaaaaaaa bbbbbbb 

aaaaaaaaaaaaa aaaaaaa 
aaaaaaaaaaaaa aaaaaaa 
aaaaaaaaaaaaa aaaaaaa 
aaaaaaaaaaaaa aaaaaaa 

aaaaaaaaaaaaa aaaaaaa 


aaaaaaaaaaaaa aaaaaaa 

aaaaaaaaaaaaa aaaaaaa 

8Ss:asHs:sss»sssi^i3 






! :: :::: 


Hill! 


I:: 


III IiII< 





■is:::: 




i$N 
li m 






mi 

EBBEDE 

BEEBE 

DOEHUDO 

HI 

□□□DDE 

EEEDE 

pi 

Ell 

EEDEEE 

EBOBBfl 

BEEBE 

EEEEE 

BOBBED 

BOBBED 

Of 

EDDEEE 

BEEBE 

DOBDDD 

Ol 

Ell 

Ol 

EEDEEE 

EEDEEE 

ddoeee 

BEEBE 

EDEBB 

EEEBB 

dddbdb 

wmmmmm 

Dl 

Ol 

Ol 

Ol 

Dl 

DODEEE 

EEDEEE 

EEKIEEE 

EEDEEE 

EDDBEE 

BEEBE 

EEEBB 

EEEBB 

EEEBB 

DDEIEIDn 

mmmmmm 

mmmmmm 

mmmmmm 

mmmmmm 

□1 

DEEDED 

EEEBB 

BOBBED 

Dl 

DDDDDD 

QEIGDD 

BOBBED 

□1 

DDDEIDD 

□□□□□ 

BDBBBD 

Ol 

inn 

0BBDD 

DDDDEn 

Dl 

BBBBBD 

BDBBB 

DDDDDD 






CD4555B, CD4556B 


File No. 858 



TRUTH TABLE 



92CS- 24227 

Fig. 14— 1 -of -8 decoder using CD4555B. 
Vqd 


Brown 

Q OUTPUTS | 

■a 

□ 

□ 

□ 

m 

B 

B 

□ 

□ 

□ 

a 

as 

□ 

□ 

D 

□ 

□ 

□ 

□ 

□ 

Q 

a 

iKI 

□ 

n 

□ 

D 

□ 

□ 

□ 

□ 

□ 

a 

m 

n 

□ 

□ 

□ 

D 

□ 

□ 

□ 

□ 

a 

m 

D 

D 

□ 

□ 

□ 

a 

□ 

□ 

a 

El 

m 

□ 

□ 

□ 

□ 

□ 

□ 

□ 

□ 

□ 

a 

m 

□ 

n 

□ 

□ 

□ 

□ 

□ 

D 

□ 

a 

m 

D 

□ 

□ 

□ 

□ 

□ 

□ 

□ 

a 

El 

UL 

1 

T 

° 

° 

° 


° 

0 

° 

3 



X L MEASURED 
WITH INPUTS 
HIGH AND 
INPUTS LOW 


92CS - 24944 

Fig. 15— Quiescent device current test circuit. 


92CS- 24945 


Fig. 16—CD4555B noise immunity test circuit. 





Fig. 19—CD4555B B input to Q3 output dynamic signal waveforms. Fig. 20—CD4556B B input to Q3 output dynamic signal waveforms. 




Fig. 21—CD4555B E input to Q3 output dynamic signal waveforms. Fig.22—CD4556B E input to Qj output dynamic signal waveforms. 









425 


Appendix 


DRIVE CURRENT TEST CIRCUIT CONNECTIONS To be used as an example of test method. 


Example: Example: 

CD4000A l D P 16-Lead Types 


05 c£-@- : 

- 1 14 - 

-2 13 - 

"3 12 - 

V DD v _ 

r° s -€hz 

1 16 

2 15 

3 M 

V dd -0.5 V9.5 V ’ 

v 0D * io v 4= 

-4 II ~ 

-5 10 - 

-6 9 - 

-7 8 - 

*-©- = 

5 12 

6 II 

7 10 

8 9 


Type 

M+ 

Ground 

Vdd 

v 0 

CD4000A 

idN 

1-4,7.8.11.13 

5,14 

6 

■d p 

1-5,7,8.11-13 

14 

CD4001A 

IdN 

2,5-9.12.13 

1,14 

3 

•d p 

1,2,5-9,12.13 

14 

CD4002A 

i d n 

3-5,7,9-12 

2,14 

1 

'D p 

2-5,7,9-12 

14 

CD4006A * 

idn 

1,4-7 

14 

13 

lD p 

4-7 

1,14 

CD4007A 

IqN 

3.7.10 

6,14 

8 

>D p 

3,6,7,10 

14 

13 

CD4008A 

idn 

1-9,15 

16 

14 

1 D p 

8 

1-7,9,15,16 

CD4009A 

Id n 

5,7-9,11,14 

1.3,16 

2 

lD p 

3,5,7-9,11,14 

1.16 

CD401 OA 

Idn 

3,5,7-9,11,14 

1.16 

2 

'D p 

5,7-9,11,14 

1,3,16 

CD4011A 

idn 

5-9,12,13 

1.2.14 

3 

lD p 

1,5-9,12,13 

2,14 

CD4012A 

Idn 

7,9-1 2 

2-5,14 

1 

1 D p 

2,7,9-12 

3-5,14 

CD4013A 

Idn 

3,5-1 1 

4,14 

1 

<D p 

3-5.7-1 1 

6,14 

CD4014A* 

Idn 

1,4-8,11,13-15 

9,16 

3 

lD p 

4-8,11,13-15 

1,9,16 

CD401 5A* 

Idn 

1,6-8,14,15 

16 

5 

'D p 

1,6,8,14,15 

7,16 

CD4017A 

id n 

8 

13-16 

3 

<D p 

8 

13-16 

2 

CD4018A 

i d n 

1-3,7-10.12 

14-16 

11 

•D p 

1-3,7,8,10 

9,12,14-16 

CD4019A 

i d n 

1-9 

14-16 

13 

•D p 

1-8 

9,14-16 

CD4020A* 

idn 

8,11 

16 

9 

'D p 

8,11 

16 

CD4021A 

lD N 

1,4-8,10.11. 

13-15 

9,16 

3 


4-8,10,11,13-15 

1,9,16 

CD4022A * 

Id n 

8,13,15 

16 

2 

'D p 

8,13,15 

16 

CD4023A 

Idn 

1,2,7,8,11-13 

3-5,14 

6 

•d p 

1-3,7,8,11-13 

4.5,14 


Refer to applicable data sheet for Vq values. 

Voltage outputs shall be supplied by an external power supply. 


Type 

M^ 

Ground 

Vdd 

Vo 

CD4024A* 

(K.D.E) 

idn 

1,7 

2,14 

12 

IdP 

2.7 

14 

CD4024A* 

(T) 

IqN 

1,12 

2,3 

11 

IdP 

3.12 

2 

CD4025A 

i d n 

1-4,7.8.11-13 

5.14 

6 

IdP 

1-5,7,8,11-13 

14 

CD4026A 

IdN 

1-3,8,15 

16 

10 

IdP 

1,2.8 

3,1 5,16 

CD4027A 

idn 

3,5-13 

4,16 

1 

IdP 

3-6.8-13 

7,16 

CD4028A 

l D l\l 

8,10-13 

16 

2 

IdP 

8,10-13 

16 

3 

CD4029A 

IdN 

3,4,8,10,12, 

13,15 

1,5.9,16 

6 

IdP 

5,8,15 

1,3,4,9,10,12, 

13,16 

CD4030A 

IdN 

1,2,5-9,12,13 

14 

3 

IdP 

2,5-9,12.13 

1,14 

CD4031A 

IqN 

1,2,8,10,15 

7,16 

6 

»dp 

1,2,7,8,10,15 

16 

CD4032A 

IdN 

2,3,5-8,10-15 

16 

9 

IdP 

2,3,5,6,8.10-15 

7,16 

CD4033A 

idn 

1-3,8,14 

15,16 

10 

IdP 

1-3,8,15 

14,16 

CD4034A 

idn 

1-8,10-12,15 

9,13,14,24 

16 

IdP 

10-12,15 

1-9,13,14,24 

CD4035A 

idn 

2-4,6-12 

2,5,16 

1 

IdP 

2-4,6-12 

5,16 

CD4036A 

IdN 

3-12,21-23 

1.2,24 

13 

IdP 

11,12,21-23 

1-10.24 

CD4037A 

IdN 

7 

1-5,14 

10 

IdP 

2-7 

14 

CD4038A 

i d n 

2,3,5-8,10-15 

10,11,16 

9 

l D p 

2,3,5,6,8,1 2-15 

7,10,11,16 

CD4039A 

i d n 

3-12,21-23 

1,2,24 

13 

IdP 

11,12,21-23 

1-10,24 

CD4040A* 

IdN 

8,10 

11,16 

9 

IdM 

8,11 

16 

CD4041A 

(TRUE) 

l 0 N 

3,6,7,10,13 

14 

1 

l D p 

6,7,10,13 

3,14 

CD4041A 

(COMP) 

IdN 

6,7,10,13 

3,14 

2 

'd p 

3,6,7,10,13 

14 


♦ M = Measurement 

* These types must be clocked into the proper state. 


426 





DRIVE-CURRENT TEST-CIRCUIT CONNECTIONS (Cont'd) 


Appendix 


Type 

CD4042A 


CD4057A 
ZERO IND 


M+ Ground 
l D ISJ 4.7,8,13,14 
' 7,8,13,14 


l D N 1-3,5,7-9,14,19 
22,23,25,27,28 


OVERFLOW IND 
OTHER OUTPUTS 
DATA OUT 1 & 3 
CD4060A* 


CD4062AK* 

CLD 


l D N 2-5,8 
3-5,8 



l D N 1-3,6.14,21,23. 
25,27,28 

7-9,13,15,19 

20,22,26 

l D P 1-3,6,7,14,21, 
23,25,27.28 

8,9,13,15,19, 

20,22,26 



V DD 

11.13.16 

2.11.13.16 



1,2,7-10 

15,16 

1,2,7,8,10,15 

16 


♦ M = Measurement 

* These types must be clocked into the proper s 





















































TERMINAL ASSIGNMENT DIAGRAMS - Top View 


1 • 

J 

14 

— V DD 

A — 

L. 

I* 

J 

14 

_ vdd 

J=A+B+C+D — 

V. 

1 • 

> 

14 

2 

13 

— F 

B — 

2 

13 

— H 

A — 

2 

13 

3 

12 

— E 

j*a+b— 

3 

12 

— G 

B — 

3 

12 

4 

II 

— D 

K*C+D — 

4 

II 

— M*G+H 

C — 

4 

II 

5 

10 

— K=0+E+F 

c — 

5 

10 

— L=E+F 

D — 

5 

10 

6 

9 

— L = G 

D — 

6 

9 

— F 

NC — 

6 

9 

7 

8 

— G 

V SS~ 

7 

8 

— E 

v ss — 

7 

8 


- V DD 

- K=E+F+G+H 


L. 

I* 

J 

14 

— v D d 

02 (PI SOURCE — 

v 

1 • 

J 

14 

2 

13 

— D|+4 

Q2(P) DRAIN — 

2 

13 

3 

12 

— D 2 +5 

Q2 GATES — 

3 

12 

4 

II 

— 02+4 

Q2(N) SOURCE “ 

4 

II 

5 

10 

— D 3 +4 

Q2(N) DRAIN — 

5 

10 

6 

9 

— D« + 5 

Ql GATES — 

6 

9 

7 

8 

— D 4 +4 

V ss ,QiaQ2aQ3(N) — 
SUBSTRATES. Ql!N) 

7 

8 


VDD,QiaQ2aQ3(P) 

’ SUBSTRATES.QMP) DRAIN 
• QI(P) SOURCE 

- Q3(N) DRAIN, Q3(P) SOURCE 

- Q3(P) DRAIN 

- Q3 GATES 

- Q3(N) SOURCE 

- QI(N) DRAIN 





A _ 

L_ 

1 • 

J 

14 

— V D0 

J= ABCD — 

)• 

J 

14 

- V DD 

Ql — 

1 • 

J 

14 

B — 

2 

13 

— H 

A — 

2 

13 

— K=EFGH 

Ql — 

2 

13 

J = AB — 

3 

12 

— G 

B — 

3 

12 

— H 

CLOCK, — 

3 

12 

K=CD — 

4 

II 

— M-GH 

C — 

4 

II 

— G 

RESET, — 

4 

II 

C — 

5 

10 

— L= EF 

D — 

5 

10 

— F 

D, — 

5 

10 

D — 

6 

9 

— F 

NC — 

6 

9 

— E 

SET, — 

6 

9 

v ss — 

7 

8 

h E 

V S S — 

7 

8 

— NC 

V SS — 

7 

8 


^ 

1 • 

J 

16 

— v dd 

CLOCK B 

V 

I# 

J 

16 

- v DD 


V. 

J 

2 

15 

— PI-7 

04 B 

2 

15 

— DATA 8 

SIG A ,N 

1 • 

14 

3 

14 

— PI-6 

Q3 A — 

3 

14 

— RESET B 

OUT — 

2 

13 

4 

13 

— PI-5 

Q2A 

4 

13 

— Ql B 

S,G S OUT - 

3 

12 

5 

12 

— Q7 

Ql A — 

5 

12 

— Q2B 

4 

II 

6 

1 1 

— SERIAL IN 

RESET A — 

6 

II 

— Q3B 

CONTROL B — 

5 

10 

7 

10 

— CLOCK 

DATA A — 

7 

10 

— Q4 A 

CONTROL C — 

6 

9 

8 

9 

— PARALLEL/SERIAL 
CONTROL 

V SS — 

8 

9 

— CLOCK A 

vss — 

7 

8 


• CONTROL A 
■ CONTROL D 


428 

















TERMINAL ASSIGNMENT DIAGRAMS - Top View 



92CS-24459 

CD4017A 


92CS-24460 

CD4018A 


92CS-2446I 

CD4019A 



92CS-24462 

C04020A 


92CS-24463 

CD4021A 


92CS-244G4 

CD4022A 



92CS-24465 92CS-24466 

CD4023A CD4024A (D, E, F, K) 


Vss 



V 0 5 


92CS-24467 

CD4024AT 



CD4025A 


92CS-24469 


CD4026A 



92CS-24470 

92CS-2447I 

92CS-24472 

CD4027A 

CD4028A 

CD4029A 


429 
















TERMINAL ASSIGNMENT DIAGRAMS - Top View 




MODE CONTROL 
CL D 


SUM 3 
INVERT 3 
CLOCK 
SUM 2 
INVERT 2 
CARRY RESET 
INVERT I 

vss 



CLOCK 
CLOCK ENABLE 
RIPPLE BLANKING IN 
RIPPLE BLANKING OUT 
CARRY OUT 



"A" ENABLE 
SERIAL INPUT 
A/B 
V SS 



QI/QI — 

V 

I* 

J 

16 

TRUE /COMR — 

2 

15 

K — 

3 

14 

J — 

4 

13 

RESET — 

5 

12 

CLOCK 

6 

II 

P/S — 

7 

10 

vss— 

8 

9 



CHIP INHIBIT 
READ INHIBIT 


24 — VDD 
23 — WORD 3 
22 — WORD 4 
21 — WORD 2 


L. 

J 


SUM 3 

L 

!• 

J 

16 

1 • 

14 

— V DD 

INVERT 3 — 

2 

15 

2 

13 

— Dl 

CLOCK — 

3 

14 

3 

12 

— El 

SUM 2 — 

4 

13 

4 

II 

— E2 

INVERT2 — 

5 

12 

5 

10 

— D2 

CARRY RESET — 

6 

1 1 

6 

9 

— E3 

INVERT 1 — 

7 

10 

7 

8 

— D3 

Vss — 

8 

9 


V. 

1# 

J 

16 

— V D D 


V. 

J 

2 

15 

— Qll 

E = A — 

1 • 

14 

4 

13 

— 08 

A — 

3 

12 

5 

12 

— 09 

G = B — 

4 

II 

6 

II 

— R 

H="B — 

5 

10 

7 

10 

— * 

B — 

6 

9 

8 

9 

— 01 

v ss — 

7 

8 


L. 

I* 

J 

16 

— V DD 

04 

v. 

I« 

J 

16 

2 

15 

— 54 

01 — 

2 

15 

3 

14 

— D4 

Rl — 

3 

14 

4 

13 

— D3 

SI — 

4 

13 

5 

12 

— 03 

ENABLE — 

5 

12 

6 

II 

— Q3 

S2 

6 

1 1 

7 

10 

— Q2 

R2 — 

7 

10 

8 

9 

— 02 

V SS — 

8 

9 


430 

















CD4044A 


CD4045A 


CD4046A 










[ 7-SEGMENT 
OUTPUTS 




7-SEGMENT 

OUTPUTS 


431 















TERMINAL ASSIGNMENT DIAGRAMS - Top View 


PARALLEL DATA 4 


NEGATIVE INDICATOR 


CONDITIONAL INPUT A 

CONDITIONAL INPUT C 

RIGHT SERIAL DATA 
LINE 

BYPASS 



'DATA OUT "CONTROL 


CONDITIONAL INPUTS 
LEFT SERIAL DATA LINE 


OVERFLOW INDICATOR 


* NOTE: NON-STANDARD TERMINAL LOCATIONS FOR 
V S S AND V DD . MOST OTHER COS/MOS TYPES 
USE CORNER TERMINALS FOR POWER- 
SUPPLY CONNECTIONS 

92CS- 20253RI 

CD4057A 







CL | = PHASE I OF 2-PHASE CLOCK 

CL id = DELAYED CL| 

CL 2 = PHASE 2 OF 2- PHASE CLOCK 
CL 2D = DELAYED CL 2 

CD4062AK 

92CS-22694 



CONTROL C 
V SS 




11 I CHANNEL 
| 2 f IN /OUT 





432 












TERMINAL ASSIGNMENT DIAGRAMS • Top View 






CD4085B 


92CS-23889RI 




433 










TERMINAL ASSIGNMENT DIAGRAMS - Top View 




92CS-24426 92CS-25I28 92CS-25084 

CD4099B CD4502B CD4511B 





CD4532B CD4555B CD4556B 


434 













Appendix 


DIMENSIONAL OUTLINES 
Ceramic Flat Packs 


OPTIONAL END 
CONFIG. TYPICAL 



1. Refer to Rules for Dimensioning Peripheral Lead Outlines 

2. Leads within .005” (.12 mm) radius of True Position (TP) 
maximum material condition. 

3. N is the maximum quantity of lead positions. 

4. Z and Z] determine a zone within which all body and lead 
irregularities lie. 


JEDEC MO-004-AF 14-LEAD 


SYMBOL 

INCHES 

NOTE 

MILLIMETERS 

MIN. 

MAX. 

MIN. 

MAX. 

A 

0.008 

0.100 


0.21 

2.54 

B 

0.015 

0.019 

1 

0.381 

0.482 

C 

0.003 

0.006 

1 

0.077 

0.152 

e 

0.050 TP 

2 

1.27 TP 

E 

0.200 

0.300 


5.1 

7.6 

H 

0.600 

1.000 


15.3 

25.4 

L 

0.150 

0.350 


3.9 

8.8 

N 

14 

3 

1 

4 

Q 

0.005 

0.050 


0.13 

1.27 

S 

0.000 

0.050 


0.00 

1.27 

z 

0.300 

4 

7.62 ! 

Zl 

0.400 

4 

10.16 j 


92SS -4300RI 


JEDEC MO-004-AG 16-LEAD 


SYMBOL 

INCHES 

NOTE 

MILLIMETERS 

MIN. 

MAX. 

MIN. 

MAX. 

A 

0.008 

0.100 


0.21 

2.54 

B 

0.015 

0.019 

1 

0.381 

0.482 

C 

0.003 

0.006 

1 

0.077 

0.152 

e 

0.050 TP 

2 

1.27 TP 

E 

0.200 

0.300 


5.1 

7.6 

H 

0.600 

1.000 


15.3 

25.4 

L 

0.150 

0.350 


3.9 

8.8 

N 


16 

3 


6 

Q 

0.005 

0.050 


0.13 

1.27 

S 

0.000 

0.025 


0.00 

0.63 

z 

0.300 

4 


7.62 

Zl 

0.400 

4 

10.16 


92CS-I727IRI 


24-LEAD 


SYMBOL 

INCHES 

NOTE 

MILLIMETERS 

MIN. 

MAX. 

MIN. 

MAX. 

A 

0.075 

0.120 


1.91 

3.04 

B 

0.018 

0.022 

1 

0.458 

0.558 

C 

0.004 

0.007 

1 

0.102 

0.177 

e 

0.050 TP 

2 

1.27 TP 

E 

0.600 

0.700 


15.24 

17.78 

H 

1.150 

1.350 


29.21 

34.29 

L 

0.225 

0.325 


5.72 

8.25 

N 

24 

3 

24 

Q 

0.035 

0.070 


0.89 

1.77 

S 

0.060 

0.110 

1 

1.53 

2.79 

Z 

0.700 

4 

17.78 

Zi 

0.750 

4 

19.05 


92CS-I9949 


28-LEAD 


SYMBOL 

INCHES 

NOTE 

MILLIMETERS 

MIN. 

MAX. 

MIN. 

MAX. 

A 

0.075 

0.120 


1.91 

3.04 

B 

0.018 

0.022 

1 

0.458 

0.558 

C 

0.004 

0.007 

1 

0.102 

0.177 

e 

0.050 TP 

2 

1.27 TP 

E 

0.600 

0.700 


15.24 

17.78 

H 

1.150 

1.350 


29.21 

34.29 

L 

0.225 

0.325 


5.72 

8.25 

N 

28 

3 

28 

Q 

0.035 

0.070 


0.89 

1.77 

S 

0 

0.060 

. 

0 

1.53 

z 

0.700 

4 

17.78 

Zi 

0.750 

4 

19.05 


92CS-20972 


When these devices are supplied solder-dipped, the maximum lead thickness (narrow portion) will not exceed 0.013”. 


435 







Appendix 


DIMENSIONAL OUTLINES 
Ceramic Dual-in-Line Packages 



JEDEC MO-OOI -AD 
14-Lead Welded-Seal 


SYMBOL 

INCHES 

NOTE 

MILLIMETERS 

MIN. 

MAX. 

MIN. 

MAX. 

A 

0.120 

0.160 


3.05 

4.06 

Al 

0.020 

0.065 


0.51 

1.65 

B 

0.014 

0.020 


0.356 

0.508 

Bl 

0.050 

0.065 


1.27 

1.65 

C 

0.008 

0.012 


0.204 

0.304 

D 

0.745 

0.770 


18.93 

19.55 

E 

0.300 

0.325 


7.62 

8.25 

El 

0.240 

0.260 


6.10 

6.60 

ei 

0.100 TP 

2 

2.54 TP 

eA 

0.300 TP 

2,3 

7.62 TP 

L 

0.125 

0.150 


3.18 

3.81 

L2 

0.000 

0.030 


0.000 

0.76 

a 

0o 

150 

4 

0o 

150 

N 

,4 

5 

14 

Nl 


0 

6 


o ! 

Qi 

0.050 

0.085 


1.27 

2.15 

S 

0.065 

0.090 


1.66 

2.28 


92SS-44IIRI 


NOTES: 

1. Refer to Rules for Dimensioning (JEDEC Publication No. 13) 
for Axial Lead Product Outlines. 

2. Leads within 0.005” (0.12 mm) radius of True Position (TP) at 
gauge plane with maximum material condition and unit installed. 

3. e A applies in zone L 2 when unit installed. 

4. a applies to spread leads prior to installation. 

5. N is the maximum quantity of lead positions. 

6. N-j is the quantity of allowable missing leads. 


JEDEC MO-OOI-AE 
16-Lead Welded-Seal 


SYMBOL 

INCHES 

NOTE 

MILLIMETERS 

MIN. 

MAX. 

MIN. 

MAX. 

A 

0.120 

0.160 


3.05 

4.06 

Al 

0.020 

0.065 


0.51 

1.65 

B 

0.014 

0.020 


0.356 

0.508 

Bl 

0.035 

0.065 


0.89 

1.65 

C 

0.008 

0.012 


0.204 

0.304 

D 

0.745 

0.785 


18.93 

19.93 

E 

0.300 

0.325 


7.62 

8.25 

E 1 

0.240 

0.260 


6.10 

6.60 

e 1 

0.100 TP 

2 

2.54 TP 

e A 

0.300 TP 

2,3 

7.62 TP 

L 

0.125 

0.150 


3.18 

3.81 

L 2 

0.000 

0.300 


0.000 

0.76 

a 

0° 

15° 

4 

0° 

15° 

N 

16 

5 

16 

N 1 


0 

6 


0 

Q 1 

0.050 

0.085 


1.27 

2.15 

S 

0.015 

0.060 


0.39 

1.52 


92SS-4286R2 


When these devices are supplied solder-dipped, the maximum lead thickness (narrow portion) will not exceed 0.013". 


436 







Appendix 


DIMENSIONAL OUTLINES 
Ceramic Dual-in-Line Packages (Cont'd) 



NOTES: 

1. REFER TO RULES FOR DIMENSIONING 
(JEDEC PUBLICATION No. 13) AXIAL LEAD 
PRODUCT OUTLINES. 

2. WHEN BASE OF BODY IS TO BE ATTACHED 
TO HEAT SINK, TERMINAL LEAD STAND- 
OFFS ARE NOTREQUIRED AND = 0. 
WHEN At = 0, THE LEADS EMERGE FROM 
THE BODY WITH THE Bt DIMENSION AND 
REDUCE TO THE B DIMENSION ABOVE THE 
SEATING PLANE. 

3. e-j AND e A APPLY IN ZONE L 2 WHEN UNIT 
INSTALLED. LEADS WITHIN .005" RADIUS 
OF TRUE POSITION (TP) AT GAUGE PLANE 
WITH MAXIMUM MATERIAL CONDITION. 

4. APPLIES TO SPREAD LEADS PRIOR TO 
INSTALLATION. 

5. N IS THE MAXIMUM QUANTITY OF LEAD 
POSITIONS. 

6. N-j IS THE QUANTITY OF ALLOWABLE 
MISSING LEADS. 


24-Lead Welded-Seal 


SYMBOL 

INCHES 

NOTE 

MILLIMETERS | 

MIN. 

MAX. 

MIN. 

MAX. 

A 

0.090 

0.150 


2.29 

3.81 

Al 

0.020 

0.065 

2 

0.51 

1.65 

B 

0.015 

0.020 


0.381 

0.508 

Bl 

0.045 

0.055 


1.143 

1.397 

C 

0.008 

0.012 


0.204 

0.304 

D 

1.15 

1.22 


29.21 

30.98 

E 

0.600 

0.625 


15.24 

15.87 

El 

0.480 

0.520 


12.20 

13.20 

ei 

0.100 TP 

3 

2.54 TP 

e A 

0.600 TP 

3 

15.24 TP 

L 

0.100 

0.180 


2.54 

4.57 

L2 

0.000 

0.030 

3 

0.00 

0.76 

a 

0° 

15° 

4 

0° 

15° 

N 

24 

5 

24 

Ni 


3 

6 


D 

Ql 

0.020 

0.080 


0.51 

2.03 

S 

0.020 

0.060 


0.51 

1.52 


92CS-I9948 


JEDEC MO-01 5-AH 
28-Lead Welded-Seal 


SYMBOL 

INCHES 

MILLIMETERS 

NOTES 

MIN. 

MAX. 

MIN. 

MAX. 

A 

.100 

.200 

2.6 

5.0 


Al 

.000 

.070 

0 

1.77 


B 

.015 

.020 

.381 

.508 


Bl 

.015 

.055 

.39 

1.39 


C 

.008 

.012 

.204 

.304 


D 

1.380 

1.420 

35.06 

36.06 


E 

.600 

.625 

15.24 

15.87 


El 

.485 

.515 

12.32 

13.08 


e 1 

.100 TP 

2.54 TP 

3 

e A 

.600 TP 

15.24 TP 

3 

L 

.100 

.200 

2.6 

5.0 


l 2 

.000 

.030 

0 

.76 


a 

0 

15 

0° 

15° 

4 

N 

28 

28 

5 

Nl 

0 

0 

6 

Qi 

.020 

.070 

.51 

1.77 


S 

.040 

.070 

1.02 

1.77 


See Note 

> 




92CM-20250 


When these devices are supplied solder-dipped, the maximum lead thickness (narrow portion) will not exceed 0.013". 


437 






Appendix 


DIMENSIONAL OUTLINES 
Ceramic Dual-in-Line Packages (Cont'd) 




1. Refer to Rules for Dimensioning (JEDEC 
Publication No. 13) for Axial Lead Pro- 
duct Outlines. 

2. Leads within 0.005" (0.12 mm) radius 

of True Position (TP) at gauge plane with 
maximum material condition and unit 
installed. 


JEDEC MO-001 -AC 
16-Lead 

(except types CD4026AF, CD4029AF, 
CD4031AF, CD4033AF) 


SYMBOL 

INCHES 

NOTE 

MILLIMETERS 

MIN. 

MAX. 

MIN. 

MAX. 

A 

0.155 

0.200 


3.94 

5.08 

Al 

0.020 

0.050 


0.51 

1.27 

B 

0.014 

0.020 


0.356 

0.508 

®1 

0.035 

0.065 


0.89 

1.65 

C 

0.008 

*0.012 


0.204 

0.304 

D 

0.745 

0.785 


18.93 

19.93 

E 

0.300 

0.325 


7.62 

8.25 

El 

0.240 

0.260 


6.10 

6.60 

e 1 

0.100 TP 

2 

2.54 TP 

e A 

0.300 TP 

2,3 

7.62 TP 

L 

0.125 

0.150 


3.18 

3.81 

L 2 

0.000 

0.030 


0.000 

0.76 

a 

0° 

15° 

4 

0° 

15° 

N 

16 

5 

w 

Ni 


0 

6 


0 

Q 1 

0.040 

0.075 


1.02 

1.90 

S 

0.015 

0.060 


0.39 

T52 


92CM- 1 5967RI 


3. e/\ applies in zone L2 when unit installed. 

4. a applies to spread leads prior to installation. 

5. N is the maximum quantity of lead positions. 

6. Ni is the quantity of allowable missing leads. 

7. B-j applies to all leads except the four end 
leads which have one-half the normal width 
(B-| min. = 0.025 in.) 


JEDEC MO-001-AB 
14-Lead 


SYMBOL 

INCHES 


MILLIMETERS | 

MIN. 

MAX. 


MIN. 

MAX. 

A 

0.155 

0.200 


3.94 

5.08 

Al 

0.020 

0.050 


0.51 

1.27 

B 

0.014 

0.020 


0.356 

0.508 

Bl 

0.050 

0.065 


1.27 

1.65 

C 

0.008 

•0.012 


0.204 

0.304 

D 

0.745 

0.770 


18.93 

19.55 

E 

0.300 

0.325 


7.62 

8.25 

El 

0.240 

0.260 


6.10 

6.60 

ei 

0.100 TP 

2 

2.54 TP 

eA 

0.300 TP 

2,3 

7.62 TP 

L 

0.125 

0.150 


3.18 

3.81 

L2 

0.000 

0.030 


0.000 

0.76 

a 

0° , 

150 

4 

0O 

150 

N 

14 

5 

14 

Ni 


0 

6 


0 

Ql 

0.040 

0.075 


1.02 

1.90 

S 

0.065 

0.090 


1.66 

2.28 


92SS-4296RI 


When these devices are supplied solder-dipped, the 


JEDEC MO-001-AG 
16-Lead 

(Types CD4026AF, CD4029AF, 
CD4031AF, CD4033AF) 


SYMBOL 

INCHES 


MILLIMETERS | 

MIN. 

MAX. 

NOTE 

MIN. 

MAX. 

A 

0.165 

0.210 


4.20 

5.33 

Al 

0.015 

0.045 


0.381 

1.14 

B 

0.015 

0.020 


0.381 

0.508 

Bl 

0.045 

0.070 

7 

1. 15 

1.77 

C 

0.009 

•0.011 


0.229 

0.279 

D 

0.750 

0.795 


19.05 

20.19 

E 

0.295 

0.325 


7.50 

8.25 

El 

0.245 

0.300 


6.23 

7.62 

•1 

0.100 TP 

2 

2.54 TP 

eA 

0.300 TP 

2,3 

7.62 TP 

L 

0.120 

0.160 


3.05 

4.06 

L2 

0.000 

0.030 


0.000 

0.76 

a 

29 

150 


29 

15° 

N 


16 

5 

16 

Ni 


0 

6 


0 

Qi 

0.050 

0.080 


1.27 

2.03 

s 

0.010 

0.060 


0.254 

1.52 


92CM-22284 


This outline differs from the standard 16- 
Lead frit-seal ceramic package MO-001 -AC 
as indicated by the values in italics shown 
in the chart above. 

lead thickness (narrow portion) will not exceed 0.013". 


438 







Appendix 


DIMENSIONAL OUTLINES 

Ceramic Dual-in-Line Welded Seal Plastic Dual-in-Line Packages 

16-Lead Side-Brazed 




WHEN THIS DEVICE IS SUPPLIED SOLDER -DIPPED, THE MAX. LEAD 
THICKNESS (NARROW PORTION) WILL NOT EXCEED 0.013 (0.33mm) 

NOTE: DIMENSIONS IN PARENTHESES ARE IN MILLIMETERS ANO 
ARE DERIVED FROM THE BASIC INCH DIMENSIONS 


1. Refer to Rules for Dimensioning (JEDEC Publication No. 13) 
for Axial Lead Product Outlines. 

2. Leads within 0.005" (0.12 mm) radius of True Position (TP) at 
guage plane with maximum material condition and unit installed. 


3. e^ applies in zone L2 when unit installed. 

4. a applies to spread leads prior to installation. 


5. N is the maximum quantity of lead positions. 


6. N-j is the quantity of allowable missing leads. 


JEDEC MO-OOI-AB 
14- Lead 


SYMBOL 


NOTE 


mm 


f 


A 

0.155 

0.200 


3.94 


Al 


0.050 


0.51 

mm 


0.014 

0.020 


0.356 



0.050 

0.065 


1.27 

1.65 



*0.012 


0.204 



0.745 

0.770 


18.93 


mi 

0.300 

0.325 


7.62 










■ 




Mm 1 


■ ■ 

wiam 

BiEUU 

■ 

■STB 

ESI 


0.000 

0.030 


0.000 

0.76 

« 

OO 

150 

4 

0 o 

150 

■g 

14 

■B 

14 ! 

Warn 


0 

B 


0 

191 

0.040 

0.075 


1.02 

1.90 


0.065 

0.090 


1.66 

2.28 


92SS-4296RI 


JEDEC MO-OOI-AC 
16-Lead 


SYMBOL 

INCHES 

NOTE 

MILLIMETERS 

MIN. 

MAX. 

MIN. 

MAX. 

A 

0.155 

0.200 


3.94 

5.08 

A 1 

0.020 

0.050 


0.51 

1.27 

B 

0.014 

0.020 


0.356 

0.508 

Bl 

0.035 

0.065 


0.89 

1.65 

C 

0.008 

®0.012 


0.204 

0.304 

D 

0.745 

0.785 


18.93 

19.93 

E 

0.300 

0.325 


7.62 

8.25 

El 

0.240 

0.260 


6.10 

6.60 

e 1 

0.100 TP 

2 

2.54 TP 

e A 

0.300 TP 

2, 3 

7.62 TP 

L 

0.125 

0.150 


3.18 

3.81 

L 2 

0.000 

0.030 


0.000 

0.76 

a 

0° 

15° 

4 

0° 

15° 

N 

16 

5 

.6 

Ni 


0 

6 


0 

Q 1 

0.040 

0.075 


1.02 

1.90 

S 

0.015 

0.060 


0.39 

1.52 


92CM- 1 5967RI 


When these devices are supplied solder-dipped, the maximum lead thickness (narrow portion) will not exceed 0.013". 


439 










TO-5-Style Package 



JEDEC MO-006-AG 
12-Lead 


SYMBOL 

imosnsii 

NOTE 

MILLIMETERS 


MIN. | MAX. 

a 


2 

5.84 TP 

Al 

0 

• 0 


0 

0 

A2 

0.165 

0.185 


4.19 

4.70 

< pB 

0.016 

0.019 

3 

0.407 

0.482 

<*>Bi 

0 

0 


0 

0 

<t> B2 

Enm 

BBTiESB 

3 

0.407 

0.533 

<pD 

T 9 

23 


8.51 

9.39 





7.75 

8.50 





0.51 

1.01 

i 




0.712 

0.863 

k 



4 

0.74 

1.14 

Li 


23 

3 

0.00 

1.27 

L2 



3 

6.4 

12.7 

L3 

■jraj 


3 

12.7 

14.27 

a 

360 TP 


360 TP 

N 

12 

6 

12 

Ni 

1 

5 

1 


NOTES: 

1. Refer to Rules for Dimensioning Axial Lead Product Out- 
lines. 

2. Leads at gauge plane within 0.007" (0.178 mm) radius of 
True Position (TP) at maximum material condition. 

3. 0 B applies between Li and L2- 0B2 applies between L2 
and 0.500" (12.70 mm) from seating plane. Diamerer is 
uncontrolled in Li and beyond 0.500" (12.70 mm). 

4. Measure from Max. 0D. 

5. Ni is the quantity of allowable missing leads. 

6. N is the maximum quantity of lead positions. 


92CS-19774 






Application Notes 


441 



□UQBZ/D 

Solid State 
Division 


Solid State Devices 

Operating Considerations 
ICE-402 


Operating Considerations for 
RCA Solid State Devices 


Solid state devices are being designed into an increasing 
variety of electronic equipment because of their high 
standards of reliability and performance. However, it is 
essential that equipment designers be mindful of good 
engineering practices in the use of these devices to achieve 
the desired performance. 

This Note summarizes important operating recommen- 
dations and precautions which should be followed in the 
interest of maintaining the high standards of performance of 
solid state devices. 

The ratings included in RCA Solid State Devices data 
bulletins are based on the Absolute Maximum Rating 
System, which is defined by the following Industry Standard 
(JEDEC) statement: 

Absolute-Maximum Ratings are limiting values of opera- 
ting and environmental conditions applicable to any electron 
device of a specified type as defined by its published data, 
and should not be exceeded under the worst probable 
conditions. 

The device manufacturer chooses these values to provide 
acceptable serviceability of the device, taking no responsi- 
bility for equipment variations, environmental variations, and 
the effects of changes in operating conditions due to 
variations in device characteristics. 

The equipment manufacturer should design so that 
initially and throughout life no absolute-maximum value for 
the intended service is exceeded with any device under the 
worst probable operating conditions with respect to supply- 
voltage variation, equipment component variation, equip- 
ment control adjustment, load variation, signal variation, 
environmental conditions, and variations in device charac- 
teristics. 

It is recommended that equipment manufacturers consult 
RCA whenever device applications involve unusual electrical, 
mechanical or environmental operating conditions. 

GENERAL CONSIDERATIONS 

The design flexibility provided by these devices makes 
possible their use in a broad range of applications and under 


many different operating conditions. When incorporating 
these devices in equipment, therefore, designers should 
anticipate the rare possibility of device failure and make 
certain that no safety hazard would result from such an 
occurrence. 

The small size of most solid state products provides 
obvious advantages to the designers of electronic equipment. 
However, it should be recognized that these compact devices 
usually provide only relatively small insulation area between 
adjacent leads and the metal envelope. When these devices 
are used in moist or contaminated atmospheres, therefore, 
supplemental protection must be provided to prevent the 
development of electrical conductive paths across the 
relatively small insulating surfaces. For specific information 
on voltage creepage, the user should consult references such 
as the JEDEC Standard No. 7 “Suggested Standard on 
Thyristors,” and JEDEC Standard RS282 “Standards for 
Silicon Rectifier Diodes and Stacks”. 

The metal shells of some solid state devices operate at the 
collector voltage and for some rectifiers and thyristors at the 
anode voltage. Therefore, consideration should be given to 
the possibility of shock hazard if the shells are to operate at 
voltages appreciably above or below ground potential. In 
general, in any application in which devices are operated at 
voltages which may be dangerous to personnel, suitable 
precautionary measures should be taken to prevent direct 
contact with these devices. 

Devices should not be connected into or disconnected 
from circuits with the power on because high transient 
voltages may cause permanent damage to the devices. 

TESTING PRECAUTIONS 

In common with many electronic components, solid-state 
devices should be operated and tested in circuits which have 
reasonable values of current limiting resistance, or other 
forms of effective current overload protection. Failure to 
observe these precautions can cause excessive internal heating 
of the device resulting in destruction and/or possible 
shattering of the enclosure. 


442 


9-74 





ICE-402 


TRANSISTORS AND THYRISTORS 
WITH FLEXIBLE LEADS 

Flexible leads are usually soldered to the circuit elements. 
It is desirable in all soldering operatings to provide some 
slack or an expansion elbow in each lead to prevent 
excessive tension on the leads. It is important during the 
soldering operation to avoid excessive heat in order to 
prevent possible damage to the devices. Some of the heat can 
be absorbed if the flexible lead of the device is grasped 
between the case and the soldering point with a pair of pliers. 

TRANSISTORS AND THYRISTORS 
WITH MOUNTING FLANGES 

The mounting flanges of JEDEC-type packages such as 
the TO-3 or TO-66 often serve as the collector or anode 
terminal. In such cases, it is essential that the mounting 
flange be securely fastened to the heat sink, which may be 
the equipment chassis. Under no circumstances, however, 
should the mounting flange of a transistor be soldered 
directly to the heat sink or chassis because the heat of the 
soldering operation could permanently damage the device. 
Soldering is the preferred method for mounting thyristors; 
see “Rectifiers and Thyristors,” below. Devices which cannot 
be soldered can be installed in commercially available 
sockets. Electrical connections may also be made by 
soldering directly to the terminal pins. Such connections may 
be soldered to the pins close to the pin seals provided care is 
taken to conduct excessive heat away from the seals; 
otherwise the heat of the soldering operation could crack the 
pin seals and damage the device. 

During operation, the mounting-flange temperature is 
higher than the ambient temperature by an amount which 
depends on the heat sink used. The heat sink must have 
sufficient thermal capacity to assure that the heat dissipated 
in the heat sink itself does not raise the device mounting- 
flange temperature above the rated value. The heat sink or 
chassis may be connected to either the positive or negative 
supply. 

In many applications the chassis is connected to the 
voltage-supply terminal. If the recommended mounting 
hardware shown in the data bulletin for the specific 
solid-state device is not available, it is necessary to use either 
an anodized aluminum insulator having high thermal con- 
ductivity or a mica insulator between the mounting-flange 
and the chassis. If an insulating aluminum washer is required, 
it should be drilled or punched to provide the two mounting 
holes for the terminal pins. The burrs should then be 
removed from the washer and the washer anodized. To insure 
that the anodized insulating layer is not destroyed during 
mounting, it is necessary to remove the burrs from the holes 
in the chassis. 

It is also important that an insulating bushing, such as 
glass-filled nylon, be used between each mounting bolt and 
the chassis to prevent a short circuit. However, the insulating 
bushing should not exhibit shrinkage or softening under the 
operating temperatures encountered. Otherwise the thermal 
resistance at the interface between device and heat sink 
may increase as a result of decreasing pressure. 


PLASTIC POWER TRANSISTORS AND THYRISTORS 

RCA power transistors and thyristors (SCR’s and triacs) 
in molded-silicone-plastic packages are available in a wide 
range of power-dissipation ratings and a variety of package 
configurations. The following paragraphs provide guidelines 
for handling and mounting of these plastic-package devices, 
recommend forming of leads to meet specific mounting 
requirements, and describe various mounting arrangements, 
thermal considerations, and cleaning methods. This informa- 
tion is intended to augment the data on electrical character- 
istics, safe operating area, and performance capabilities in the 
technical bulletin for each type of plastic-package transistor 
or thyristor. 

Lead-Forming Techniques 

The leads of the RCA VERSAWATT in-line plastic 
packages can be formed to a custom shape, provided they are 
not indiscriminately twisted or bent. Although these leads 
can be formed, they are not flexible in the general sense, nor 
are they sufficiently rigid for unrestrained wire wrapping 
Before an attempt is made to form the leads of an in-line 
package to meet the requirements of a specific application, 
the desired lead configuration should be determined, and a 
lead-bending fixture should be designed and constructed. The 
use of a properly designed fixture for this operation 
eliminates the need for repeated lead bending. When the use 
of a special bending fixture is not practical, a pair of 
long-nosed pliers may be used. The pliers should hold the 
lead firmly between the bending point and the case, but 
should not touch the case. 

When the leads of an in-line plastic package are to be 
formed, whether by use of long-nosed pliers or a special 
bending fixture, the following precautions must be observed 
to avoid internal damage to the device: 

1. Restrain the lead between the bending point and the 
plastic case to prevent relative movement between the 
lead and the case. 

2. When the bend is made in the plane of the lead 
(spreading), bend only the narrow part of the lead. 

3. When the bend is made in the plane perpendicular to that 
of the leads, make the bend at least 1/8 inch from the 
plastic case. 

4. Do not use a lead-bend radius of less than 1/16 inch. 

5. Avoid repeated bending of leads. 

The leads of the TO-220AB VERSAWATT in-line 
package are not designed to withstand excessive axial pull. 
Force in this direction greater than 4 pounds may result in 
permanent damage to the device. If the mounting arrange- 
ment tends to impose axial stress on the leads, some method 
of strain relief should be devised. 

Wire wrapping of the leads is permissible, provided that 
the lead is restrained between the plastic case and the point 
of the wrapping. Soldering to the leads is also allowed. The 
maximum soldering temperature, however, must not exceed 
275°C and must be applied for not more than 5 seconds at a 
distance not less than 1/8 inch from the plastic case. When 


443 



ICE-402 


wires are used for connections, care should be exercised to 
assure that movement of the wire does not cause movement 
of the lead at the lead-to-plastic junctions. 

The leads of RCA molded-plastic high-power packages 
are not designed to be reshaped. However, simple bending of 
the leads is permitted to change them from a standard 
vertical to a standard horizontal configuration, or conversely. 
Bending of the leads in this manner is restricted to three 
90-degree bends; repeated bendings should be avoided. 
Mounting 

Recommended mounting arrangements and suggested 
hardward for the VERSAWATT package are given in the data 
bulletins for specific devices and in RCA Application Note 
AN-4142. When the package is fastened to a heat sink, a 
rectangular washer (RCA Part No. NR231 A) is recommended 
to minimize distortion of the mounting flange. Excessive 
distortion of the flange could cause damage to the package. 
The washer is particularly important when the size of the 
mounting hole exceeds 0.140 inch (6-32 clearance). Larger 
holes are needed to accommodate insulating bushings; 
however, the holes should not be larger than necessary to 
provide hardware clearance and, in any case, should not 
exceed a diameter of 0.250 inch. 

Flange distortion is also possible if excessive torque is 
used during mounting. A maximum torque of 8 inch-pounds 
is specified. Care should be exercised to assure that the tool 
used to drive the mounting screw never comes in contact 
with the plastic body during the driving operation. Such 
contact can result in damage to the plastic body and internal 
device connections. An excellent method of avoiding this 
problem is to use a spacer or combination spacer-isolating 
bushing which raises the screw head or nut above the top 
surface of the plastic body. The material used for such a 
spacer or spacer-isolating bushing should, of course, be 
carefully selected to avoid “cold flow” and consequent 
reduction in mounting force. Suggested materials for these 
bushings are diallphtalate, fiberglass-filled nylon, or 
fiberglass-filled polycarbonate. Unfilled nylon should be 
avoided. 

Modification of the flange can also result in flange 
distortion and should not be attempted. The package should 
not be soldered to the heat sink by use of lead-tin solder 
because the heat required with this type of solder will cause 
the junction temperature of the device to become excessively 
high. 

The TO-220AA plastic package can be mounted in 
commercially available TO-66 sockets, such as UID 
Electronics Corp. Socket No. PTS-4 or equivalent. For 
testing purposes, the TO-220AB in-line package can be 
mounted in a Jetron Socket No. DC74-104 or equivalent. 
Regardless of the mounting method, the following 
precautions should be taken: 

1. Use appropriate hardware. 

2. Always fasten the package to the heat sink before the 

leads are soldered to fixed terminals. 

3. Never allow the mounting tool to come in contact with 

the plastic case. 


4. Never exceed a torque of 8 inch-pounds. 

5. Avoid oversize mounting holes. 

6. Provide strain relief if there is any probability that axial 
stress will be applied to the leads. 

7. Use insulating bushings to prevent hot-creep problems. 
Such bushings should be made of diallphthalate, fiber- 
glass-filled nylon, or fiberglass-filled polycarbonate. 

The maximum allowable power dissipation in a solid 
state device is limited by the junction temperature. An 
important factor in assuring that the junction temperature 
remains below the specified maximum value is the ability of 
the associated thermal circuit to conduct heat away from the 
device. 

When a solid state device is operated in free air, without a 
heat sink, the steady-state thermal circuit is defined by the 
junction-to-free-air thermal resistance given in the published 
data for the device. Thermal considerations require that a 
free flow of air around the device is always present and that 
the power dissipation be maintained below the level which 
would cause the junction temperature to rise above the 
maximum rating. However, when the device is mounted on a 
heat sink, care must be taken to assure that all portions of 
the thermal circuit are considered. 

To assure efficient heat transfer from case to heat sink 
when mounting RCA molded-plastic solid state power 
devices, the following special precautions should be 
observed: 

1. Mounting torque should be between 4 and 8 inch- 
pounds. 

2. The mounting holes should be kept as small as possible. 

3. Holes should be drilled or punched clean with no burrs or 
ridges, and chamfered to a maximum radius of 0.010 
inch. 

4. The mounting surface should be flat within 0.002 
inch/inch. 

5. Thermal grease (Dow Corning 340 or equivalent) should 
always be used on both sides of the insulating washer if 
one is employed. 

6. Thin insulating washers should be used. (Thickness of 
factory-supplied mica washers range from 2 to 4 mils). 

7. A lock washer or torque washer, made of material having 
sufficient creep strength, should be used to prevent 
degradation of heat sink efficiency during life. 

A wide variety of solvents is available for degreasing and 
flux removal. The usual practice is to submerge components 
in a solvent bath for a specified time. However, from a 
reliability stand point it is extremely important that the 
solvent, together with other chemicals in the solder-cleaning 
system (such as flux and solder covers), do not adversely 
affect the life of the component. This consideration applies 
to all non-hermetic and molded-plastic components. 

It is, of course, impractical to evaluate the effect on 
long-term device life of all cleaning solvents, which are 
marketed with numerous additives under a variety of brand 
names. These solvents can, however, be classified with 


444 



ICE-402 


respect to their component parts as either acceptable or 
unacceptable. Chlorinated solvents tend to dissolve the outer 
package and, therefore, make operation in a humid atmos- 
phere unreliable. Gasoline and other hydrocarbons cause the 
inner encapsulant to swell and damage the transistor. Alcohol 
is an acceptable solvent. Examples of specific, acceptable 
alchols are isopropanol, methanol, and special denatured 
alcohols, such as SDA1 , SDA30, SDA34, and SDA44. 

Care must also be used in the selection of fluxes for lead 
soldering. Rosin or activated rosin fluxes are recommended, 
while organic or acid fluxes are not. Examples of acceptable 
fluxes are: 

1 . Alpha Reliaros No. 320-33 

2. Alpha Reliaros No. 346 

3. Alpha Reliaros No. 711 

4. Alpha Reliafoam No. 807 

5. Alpha Reliafoam No. 809 

6. Alpha Reliafoam No. 811-13 

7. Alpha Reliafoam No. 815-35 

8. Kester No. 44 

If the completed assembly is to be encapsulated, the 
effect on the molded-plastic transistor must be studied from 
both a chemical and a physical standpoint. 

RECTIFIERS AND THYRISTORS 

A surge-limiting impedance should always be used in 
series with silicon rectifiers and thyristors. The impedance 
value must be sufficient to limit the surge current to the 
value specified under the maximum ratings. This impedance 
may be provided by the power transformer winding, or by an 
external resistor or choke. 

A very efficient method for mounting thyristors utilizing 
the “modified TO-5” package is to provide intimate contact 
between the heat sink and at least one half of the base of the 
device opposite the leads. This package can be mounted to 
the heat sink mechanically with glue or an expoxy adhesive, 
or by soldering, the most efficient method. 

The use of a “self-jigging” arrangement and a solder 
preform is recommended. If each unit is soldered individ- 
ually, the heat source should be held on the heat sink and the 
solder on the unit. Heat should be applied only long enough 
to permit solder to flow freely. For more detailed thyristor 
mounting considerations, refer to Application Note AN3822, 
“Thermal Considerations in Mounting of RCA Thyristors”. 

MOS FIELD-EFFECT TRANSISTORS 

Insulated-Gate Metal Oxide-Semiconductor Field-Effect 
Transistors (MOS FETs), like bipolar high-frequency 
transistors, are susceptible to gate insulation damage by the 
electrostatic discharge of energy through the devices. 
Electrostatic discharges can occur in an MOS FET if a type 
with an unprotected gate is picked up and the static charge, 
built in the handler’s body capacitance, is discharged through 
the device. With proper handling and applications 
procedures, however, MOS transistors are currently being 
extensively used in production by numerous equipment 
manufacturers in military, industrial, and consumer applica- 


tions, with virtually no problems of damage due to 
electrostatic discharge. 

In some MOS FETs, diodes are electrically connected 
between each insulated gate and the transistor’s source. 
These diodes offer protection against static discharge and 
in-circuit transients without the need for external shorting 
mechanisms. MOS FETs which do not include gate- 
protection diodes can be handled safely if the following basic 
precautions are taken: 

1. Prior to assembly into a circuit, all leads should be kept 
shorted together either by the use of metal shorting 
springs attached to the device by the vendor, or by the 
insertion into conductive material such as “ECCOSORB* 
LD26” or equivalent. 

(NOTE: Polystyrene insulating “SNOW” is not suffi- 
ciently conductive and should not be used.) 

2. When devices are removed by hand from their carriers, 
the hand being used should be grounded by any suitable 
means, for example, with a metallic wristband. 

3. Tips of soldering irons should be grounded. 

4. Devices should never be inserted into or removed from 
circuits with power on. 

RF POWER TRANSISTORS 
Mounting and Handling 

Stripline rf devices should be mounted so that the leads 
are not bent or pulled away from the stud (heat sink) side of 
the device. When leads are formed, they should be supported 
to avoid transmitting the bending or cutting stress to the 
ceramic portion of the device. Excessive stresses may destroy 
the hermeticity of the package without displaying visible 
damage. 

Devices employing silver leads are susceptible to 
tarnishing; these parts should not be removed from the 
original tarnish-preventive containers and wrappings until 
ready for use. Lead solderability is retarded by the presence 
of silver tarnish; the tarnish can be removed with a silver 
cleaning solution, such as thiourea. 

The ceramic bodies of many rf devices contain beryllium 
oxide as a major ingredient. These portions of the transistors 
should not be crushed, ground, or abraded in any way 
because the dust created could be hazardous if inhaled. 

Operating 

Forward-Biased Operation. For Class A or AB operation, 
the allowable quiescent bias point is determined by reference 
to the infrared safe-area curve in the appropriate data 
bulletin. This curve depicts the safe current/voltage combina- 
tions for extended continuous operation. 

Load VSWR. Excessive collector load or tuning mismatch 
can cause device destruction by over-dissipation or secondary 
breakdown. Mismatch capability is generally included on the 
data bulletins for the more recent rf transistors. 

See RCA RF Power Transitor Manual, Technical Series 
RMF-430, pp 39-41, for additional information concerning 
the handling and mounting of rf power transistors. 


♦Trade Mark: Emerson and Cumming, Inc. 


445 



ICE-402 


INTEGRATED CIRCUITS 

Handing 

All COS/MOS gate inputs have a resistor/diode gate 
protection network. All transmission gate inputs and all 
outputs have diode protection provided by inherent p-n 
junction diodes. These diode networks at input and output 
interfaces protect COS/MOS devices from gate-oxide failure 
in handling environments where static discharge is not 
excessive. In low-temperature, low-humidity environments, 
improper handling may result in device damage. See 
ICAN-6000, “Handling and Operating Considerations for 
MOS Integrated Circuits”, for proper handling procedures. 

Mounting 

Integrated circuits are normally supplied with lead-tin 
plated leads to facilitate soldering into circuit boards. In 
those relatively few applications requiring welding of the 
device leads, rather than soldering, the devices may be 
obtained with gold or nickel plated Kovar leads.* It should be 
recognized that this type of plating will not provide complete 
protection against lead corrosion in the presence of high 
humidity and mechanical stress. The aluminum-foil-lined 
cardboard “sandwich pack” employed for static protection 
of the flat-pack also provides some additional protection 
against lead corrosion, and it is recommended that the 
devices be stored in this package until used. 

When integrated circuits are welded onto printed circuit 
boards or equipment, the presence of moisture between the 
closely spaced terminals can result in conductive paths that 
may impair device performance in high-impedance appli- 
cations. It is therefore recommended that conformal coatings 
or potting be provided as an added measure of protection 
against moisture penetration. 

In any method of mounting integrated circuits which 
involves bending or forming of the device leads, it is 
extremely important that the lead be supported and clamped 
between the bend and the package seal, and that bending be 
done with care to avoid damage to lead plating. In no case 
should the radius of the bend be less than the diameter of the 
lead, or in the case of rectangular leads, such as those used in 
RCA 14-lead and 16-lead flat-packages, less than the lead 
thickness. It is also extremely important that the ends of the 
bent leads be straight to assure proper insertion through the 
holes in the printed-circuit board. 

Operating 

Unused Inputs 

All unused input leads must be connected to either Vss 
or Vdd, whichever is appropriate for the logic circuit 
involved. A floating input on a high-current type, such as the 
CD4049 or CD4050, not only can result in faulty logic 
operation, but can cause the maximum power dissipation of 
200 milliwatts to be exceeded and may result in damage to 
the device. Inputs to these types, which are mounted on 
printed-circuit boards that may temporarily become 
unterminated, should have a pull-up resistor to Vss or ^DD- 
A useful range of values for such resistors is from 10 kilohms 
to 1 megohm. 


Input Signals 

Signals shall not be applied to the inputs while the device 
power supply is off unless the input current is limited to a 
steady state value of less than 10 milliamperes. Input 
currents of less than 10 milliamperes prevent device damage; 
however, proper operation may be impaired as a result of 
current flow through structural diode junctions. 

Output Short Circuits 

Shorting of outputs to V$s or Vj)D can damage many of 
the higher-output-current COS/MOS types, such as the 
CD4007, CD4041 , CD4049, and CD4050. In general, these 
types can all be safely shorted for supplies up to 5 volts, but 
will be damaged (depending on type) at higher power-supply 
voltages. For cases in which a short-circuit load, such as the 
base of a p-n-p or an n-p-n bipolar transistor, is directly 
driven, the device output characteristics given in the 
published data should be consulted to determine the 
requirements for a safe operation below 200 milliwatts. 

For detailed COS/MOS IC operating and handling 
considerations, refer to Application Note ICAN-6000 
“Handling and Operating Considerations for MOS Integrated 
Circuits”. 

SOLID STATE CHIPS 

Solid state chips, unlike packaged devices, are non- 
hermetic devices, normally fragile and small in physical size, 
and therefore, require special handling considerations as 
follows: 

1 . Chips must be stored under proper conditions to insure 
that they are not subjected to a moist and/or contam- 
inated atmosphere that could alter their electrical, 
physical, or mechanical characteristics. After the shipping 
container is opened, the chip must be stored under the 
following conditions: 

A. Storage temperature, 40°C max. 

B. Relative humidity, 50% max. 

C. Clean, dust-free environment. 

2. The user must exercise proper care when handling chips 
to prevent even the slightest physical damage to the chip. 

3. During mounting and lead bonding of chips the user must 
use proper assembly techniques to obtain proper elec- 
trical, thermal, and mechanical performance. 

4. After the chip has been mounted and bonded, any 
necessary procedure must be followed by the user to 
insure that these non-hermetic chips are not subjected to 
moist or contaminated atmosphere which might cause 
the development of electrical conductive paths across the 
relatively small insulating surfaces. In addition, proper 
consideration must be given to the protection of these 
devices from other harmful environments which could 
conceivably adversely affect their proper performance. 


*Mil-M-38510A, paragraph 3.5.6.1 (a), lead material. 


446 




Solid State 
Division 


Digital Integrated Circuits 

Application Note 
ICAN-6000 


Handling and Operating Considerations 
for MOS Integrated Circuits 

by S. Dansky 
R. E. Funk 


This Note describes practices for handling and operating 
MOS integrated circuits that will guard against device damage 
and assure optimum performance. 

Handling Considerations 

The input protection networks incorporated in all RCA 
COS/MOS devices are effective in a wide variety of device 
handling situations. To be totally safe, however, it is 
desirable to restate the general conditions for eliminating all 
possibilities of device damage. 

Because MOS devices have extremely high input resistance, 
they are susceptible to damage when exposed to extremely 
high static electrical charges. To avoid possible damage to 
the devices duriiig handling, testing, or actual operation, 
therefore, the following procedures should be followed: 

1. The leads of devices should be in contact with a 
conductive material, except when being tested or in 
actual operation, to avoid build-up of static charge. 

2. Soldering-iron tips, metal parts of fixtures and tools, 
and handling facilities should be grounded. 

3. Devices should not be inserted into or removed from 
circuits with the power on because transient voltages 
may cause permanent damage. 

4. Signals should not be applied to the inputs while the 
device power supply is off. 

5. All unused input leads must be connected to either 
Vss (ground) or Vdq (device supply), whichever is 
appropriate for the logic circuit involved. 

Table I indicates general handling procedures recommended 
to prevent damage from static electrical charges. 


Table I — General Handling Considerations 


Should be 
conductive 


Handling Equipment 

Metal Parts of Fixtures 
and Tools 

Handling Trays 
Soldering Irons 
Table Tops 
Transport Carts 


Manufacturing Operating 
Personnel 


General Handling of Devices 


Should be 
grounded to 
common point 


X 

X 

X 

X 

(Static Dis- 
charge Straps) 

o (Utilize 

grounded metal 
wrist straps) 

• (Utilize 

grounded metal 
wrist straps) 


Total protection results when personnel and materials are all at 
the same or ground potential. 

Dry weather (relative humidity less than 30%) tends to multiply 
the accumulation of static charges on any surface. Conversely, 
higher humidity levels tend to reduce the magnitude of the 
static voltage generated. In a low-humidity environment, the 
handling precautions listed above take on added importance and 
should be adhered to without exceptions. 


1 -megohm series resistor. 


Handling of Unmounted Chips 

In handling of unmounted chips, care should be taken to 
avoid differences in voltage potential. A conductive carrier, 
or a carrier having a conductive overlay, should be used. 

Another important consideration is the sequence in 
which bonds are made; the Vqd (device supply) connection 
should always be made before the Vss (ground) bond. 

Handling of Subassembly Boards 

After COS/MOS units have been mounted on circuit 
boards, proper handling precautions should still be observed. 
Until these subassemblies are inserted into a complete system 


in which the proper voltages are applied, the board is no 
more than an extension of the leads of the device mounted 
on the board. 

It is good practice to put conductive clips or conductive 
tape 1 2 3 4 5 on the circuit-board terminals. This precaution prevents 
static charges from being transmitted through the board 
wiring to the devices mounted on the board. 

Automatic Handling Equipment 

When automatic handling equipment is used, static 
electricity may not always be eliminated through grounding 

1 See Table II for sources of anti-static materials. 


3-74 


447 




I CAN-6000 


techniques alone. Automatic feed mechanisms must be 
insulated from the devices under test at the point where the 
devices are connected to the test set. The device-insulated 
part of the automatic handling mechanism (anvil transport) 
can generate very high levels of static electricity which are 
developed by the continuous flow of devices sliding over and 
then separating from the anvil. Total control of these static 
voltages is critical because of the high throughputs associated 
with automatic handling. 

Fortunately, the resolution of this problem is simple, 
practical, and inexpensive. Ionized-air blowers, which supply 
large volumes of ionized air to objects that are to be charge 
neutralized, are commercially available from many supply 
sources. Field experience with ionized-air techniques reveals 
this method to be extremely effective in eliminating static 
electricity when grounding techniques cannot be used. 

Lead Bending and Forming Considerations 

Other problems that can occur in handling COS/MOS 
devices relate to the proper handling of leads during 
mounting of devices. In any method of mounting integrated 
circuits that involves bending or forming of the device leads, 
it is extremely important that the leads be supported and 
clamped between the bend and the package seal, and that 
bends be made with extreme care to avoid damage to lead 
plating. In no case should the radius of the bend be less than 
the diameter of the lead, or in the case of rectangular leads, 
such as those used in RCA 14-lead flat-packaged integrated 
circuits, less than the lead thickness. It is also extremely 
important that the ends of the bent leads be perfectly 
straight and parallel to assure easy insertion through the holes 
in the printed-circuit board. 

Bending, forming, and clinching of integrated-circuit 
leads produce stresses in the leads and can cause stresses in 
the seals if the above precautions are not taken. In addition, 
wide variations in temperature during normal use result in 
stresses in the device leads. Tests of 14-lead flat-pack 
integrated circuits, conducted under worst-case conditions in 
which the. packages were rigidly attached to postsextending 
from the printed-circuit board, showed that over a tempera- 
ture swing of 180°C (from -55°C to +125°C) the stress 
developed in the leads, the tensile pull on the leads, the shear 
stress introduced on the seal, and the tensile stress developed 
in the seal were all well within the limits for these materials. 
The use of thermal- stress-relief bends is, therefore, not 
necessary. 


Soldering Time and Temperature 

All device leads can withstand exposure to temperatures 
as high as 265°C for as long as ten seconds, and as close as 
1/16 ± 1/32 inch from the body of the device. 


Storing of COS/MOS Chips 

COS/MOS chips, unlike most packaged devices, are 
non-hermetic devices, fragile and small in physical size, and 


therefore require the following special handling considera- 
tions: 

1. Chips must be stored under proper conditions to 
assure that they are not subjected to a moist and/or 
contaminated atmosphere that could alter their 
electrical, physical, or mechanical characteristics. 
After the shipping container is opened, the storage 
temperature should not exceed 40°C and the 
environment should be clean, dust-free, and less than 
50% relative humidity. 

2. After mounting and bonding, these non-hermetic 
chips should not be subjected to moist or contam- 
inated atmospheres that might cause the development 
of electrical conductive paths across the relatively 
small insulating surfaces. In addition, proper consid- 
eration must be given to the protection of these 
devices from other harmful environments which 
could conceivably adversely affect their proper 
performance. 

For further information on COS/MOS chip handling, refer to 
File No. 517, “CD4000AH Series COS/MOS Chips”. 

Storing of Printed-Circuit Boards 

Excessive humidity (greater than 60%) should be avoided 
during circuit-board check-out to prevent the false impres- 
sion of excessive device internal leakage. High relative 
humidity may cause leakage paths between closely spaced 
elements of the circuit boards, such as the terminals and 
insulated metallized connection strips. Normally this added 
leakage is not significant in non-COS/MOS devices. However, 
when the nanoampere-leakage advantages of COS/MOS 
devices are desired, leakage currents on circuit boards or 
non-hermetic modules which are affected by high humidity 
become of major concern and must be controlled by coating, 
cleaning, or better environmental controls. 

Effects of Humidity on Static Electricity 

Dry weather (relative humidity less than 30%) tends to 
multiply the accumulation of static charges on any surface. 
Conversely, higher humidity levels tend to reduce the 
magnitude of the static voltage generated. In a low-humidity 
environment, the handling precautions listed in Table I take 
on added importance and should be adhered to without 
exceptions. 

Electrical Failure Modes Due To Improper Handling 

When the possibilities exist for appreciable static-energy 
discharge, and proper handling techniques are not used, 
electrical damage can result as follows: 

(a) shorted input protection diodes, 

(b) shorted or open gates, 

(c) opening in metal paths from the device input. 

The presence of this type of device damage can be detected 
by curve-tracer checks of the input protection diodes of the 
gate-oxide protection circuits described on page 3, and also 
by a check of the device characteristics, especially mutual 
transconductance (gm). 


448 



ICAN-6000 


Operating Considerations 

Maximum Ratings 

Storage-Temperature Range 
Operating-Temperature Range: 
Ceramic-Package Types 
Plastic-Package Types 
DC Supply-Voltage Range: 

VDD " vss 

VDD " vee 

vcc- vss 

DC Input-Voltage Range 
for CD4009A, CD4010A 
for CD4049A, CD4050A 
for CD4051A, CD4052A, CD4053A: 

Controls 

Signals 

Device Dissipation (per package) 

Lead Temperature (during soldering) 
at a distance 1 /1 6 ± 1 /32 inch 
( 1 .59 ± 0.79 mm) from case for 
10 seconds maximum 


CD4000A Series 
-65 to + 150°C 

-55 to + 125°C 
- 40 to + 85° C 

-0.5 to +15 V 
-0.5 to + 15 V 
-0.5 to +15 V 
V S S<V|< V DD 

Vss < V| < Vdd > v cc 

V SS <V| < 15 V 
Vss<V|<V DD 

vee < V| < vqd 

200 mW 


+ 265°C 


Operating Voltage 

When operating near the maximum supply-voltage range 
of 15 volts, care should be taken to avoid or suppress 
power-supply turn-on or turn-off transients, power-supply 
ripple or regulation, and ground noise; any of the above 
conditions must not cause (Vj)j) — Vss) to exceed the 
absolute maximum rating. 

Power supplies should have a current compliance 
compatible with actual COS/MOS current drain. 

Another good power-supply practice is to use a zener 
protection diode in parallel with the power bus. The zener 
value should be above the expected maximum regulation 
excursion, but should not exceed 15 volts. Fig. 1 illustrates a 
practical zener shunt circuit. A current-limiting resistor is 
included if the supply-current compliance is higher than the 
zener power-dissipation rating for a given zener voltage. The 
shunt capacitance value is chosen to supply required peak 
current switching transients. 



92CS- 22885 


Fig. 1 - Zener-diode shunt circuit. 


Unused Inputs 

All unused input leads must be connected to either Vss 
or Vdd> whichever is appropriate for the logic circuit 


involved. A floating input on a high-current type (such as the 
CD4009A, CD4010A. CD4041A, CD4049A, CD4050A) not 
only can result in faulty logic operation, but can cause the 
maximum power dissipation of 200 milliwatts to be 
exceeded and may result in damage to the device. Another 
consideration with these high-current types is that a pull-up 
resistor from their inputs to \’ss or Vdd should be used if 
there is any possibility that the device may become 
temporarily unterminated (e.g., if the printed circuit board 
driving the high-current types is removed from the chassis). 
A useful range of values for such resistors is from 0.2 to 1 
megohm. 

Input Signals 

Signals shall not be applied to the inputs while the device 
power supply is off unless the input current is limited to a 
steady -state value of typically less than 10 milliamperes. Input 
signal interfaces having the allowable 0.5 volt above Vdd or 
below Vss, respectively, should be current-limited to 
typically 10 milliamperes or less. 

Whenever the possibility of exceeding 10 milliamperes of 
input current exists, a resistor in series with the input is 
recommended. The value of this resistor can be as high as 
10 kilohms without affecting static electrical characteristics. 
Speed, however, will be reduced due to the added RC delay. 
Particular attention should be given to long input-signal lines 
where high inductance can increase the likelihood of large 
signal pickup in noisy environments. In these cases, series 
resistance with shunt capacitance at the IC input terminals is 


449 



I CAN-6000 


recommended. The shunt capacitance should be made as 
large as possible consistent with the system speed 
requirements. 

Interfacing with T2|_ Devices 

The COS/MOS hex buffers (CD4009A, CD4010A, 
CD4049A, and CD4050A) are designed to drive two 
normal-power T 2 L loads. Other device types (such as the 
CD4041A, CD4048A, and CD4031A) can also directly drive 
at least one T 2 L load. Always consult the published data on 
the particular COS/MOS type for this capability. Most gates 
and inverters and some MSI types can drive one or more 
low-power T 2 L loads. To provide a good noise margin in the 
logic “1” state, T 2 L devices that drive COS/MOS devices 
require a pull-up resistor at the COS/MOS input. The 
COS/MOS hex buffers can also convert COS/MOS logic levels 
(5 to 15 volts) to T 2 L logic levels (5 volts), i.e., down-level 
conversion. 

Rules for safe system design when COS/MOS interfaces 
with T 2 L and both logic systems have independent power 
supplies of the same voltage level but possibly on at different 
times are as follows: 

a) T 2 L driving COS/MOS -- use 1 kilohm in series 

with COS/MOS input 

b) COS/MOS driving T 2 L - connect directly 

Interfacing with p-MOS Devices 

COS/MOS devices can operate at Vpo = 0 and V$s = -3 
to -15 volts to interface directly with p-MOS devices with no 
degradation in noise immunity or other characteristics. 

Interfacing with n-MOS Devices 

COS/MOS devices can be interfaced directly with n-MOS 
devices over the +3 to +15 volt range of power supplies. 

Fan-Out - COS/MOS to COS/MOS 

All RCA COS/MOS devices have a dc fan-out capability of 
50. The reduction in COS/MOS switching speed caused by 
added capacitive loading should, however, be consistent with 
high-speed system design. The input capacitance is typically 
5 pF for most types; the CD4009A and CD4049A buffers 
have an input capacitance of typically 15 pF. 

Maximum Clock Rise and Fall Time 

All COS/MOS clocked devices show maximum clock rise- 
and fall-time ratings (normally 5 to 15 microseconds). With 
longer rise or fall times, a device may not function properly. 

Parallel Clocking 

When two or more different COS/MOS devices use a 
common clock, the clock rise time must be kept at a value 
less than the sum of the propagation delay time, the output 
transition time, and the setup time. Most flip-flop and 
shift-register types are included in this rule and are so noted 
in the indiv'lual data sheets. 

Noise Immunity 

COS/MOS inputs normally switch at 30 to 70 per cent of 
the power-supply voltage. For example, for a 10-volt supply, 


a logic “0” is 0 to 3 volts, and a logic “1” is 7 to 10 volts. 
For 5-volt operation, a logic “0” is 0 to 1 .5 volts, and a logic 
“1” is 3.5 to 5 volts. COS/MOS noise immunity is 
30 per cent of the supply voltage for the range from +3 to 
+15 volts. 

The inherent 30-per-cent noise immunity of COS/MOS 
also permits a 1-volt noise margin when interfaced with T 2 L 
or DTL. For example, standard T 2 L and DTL interfacing 
with COS/MOS at a nominal Vdd = Vcc = 5 volts provides 
at least 1-volt noise margin; i.e., VoLmax(T 2 L) = 0.4 volt 
and VoL m i n (DTL) = 0.45 volt; 30% of 5 volts = 1 .5 volts. 

This example applies typically to the 5400/7400 series, 
the 9000 series, and the 8000 series. HI NIL (300 series) can 
interface with COS/MOS at a nominal Vdd = Vcc = 1 2 volts 
with a worst-case noise margin of 2.1 volts. 

Because COS/MOS voltage-transfer switching 
characteristics vary from 30 to 70 per cent of the supply 
voltage, system designers employing COS/MOS 
multivibrators, level detectors, and RC networks must 
consider this variation. Application Note IC AN-6267 
illustrates an accurate multivibrator design technique which 
minimizes the switching-point variation. 

Output Short Circuits 

Shorting of outputs to V$s or Vdd can cause the device 
power dissipation to exceed the safe value of 200 milliwatts 
for high-output-current types such as the CD4007A, 
CD4009A, CD4010A, CD4041A, CD4049A, and CD4050A. 
In general, outputs of these types can all be safely shorted 
when operated with Vdd " V$s ^ 5 volts, but may exceed 
the 200-milliwatt dissipation rating at higher power-supply 
voltages. For cases in which a short-circuited load, such as 
the base of a p-n-p or n-p-n bipolar transistor, is directly 
driven, the device output characteristics given in the 
published data should be consulted to determine the 
requirements for safe operation below 200 milliwatts. 

COS/MOS Characteristics 

Quiescent Device Leakage Current (II): 

Quiescent device leakage is measured for inputs tied high 
Odd) a »d also f° r all inputs tied low (Iss)> as illustrated 
below: 



92CS-228B6 

Quiescent Device Dissipation (Pd): 

Quiescent device dissipation is given by 

Pd=(V D d- V ss )Il 
where II = Idd or I S s 


450 



ICAN-6000 


Output Voltage Levels (COS/MOS driving COS/MOS): 

V 0L = Low-Level(“0”)Output = 10 mV* at 25°C 

Vqh = High-Level(“l”)Output = V DD - 10 mV* at +25°C 

Noise Immunity: 

V NL = the maximum noise voltage that can be applied to 
a logic “0” input (added to V$s) before the 
output changes state. 

Vnh = l he maximum noise voltage that can be applied to 
a logic “1” input (subtracted from Vdd) before 
the output changes state. 


Output Drive Current: 

Sink Current (IpN) = the output sink current provided by 
the n-channel transistor without exceeding a given 
output voltage (V Q ) as shown on each data sheet. 

Source Current (IpP) = the output source current 
provided by the p-channel transistor without 
dropping below a given output voltage (V Q ) as 
shown on each data sheet. 


Gate-Oxide Protection Circuits 

Most COS/MOS gate inputs have the protection shown in 
Fig. 2. An exception to this statement is the input network 
for the CD4049A and CD4050A shown in Fig. 3. Figs. 4 
and 5 illustrate the protection diodes inherently present at all 
transmission-gate input/output terminals and all inverter 
outputs. 1CAN-6218 gives further information on protection 
circuits. 

The protection networks can typically protect against 
1-2 kilovolts of energy discharge from a 250-pF source. 



Fig. 2 — Normal gate-input-protection circuit. 

O 1 — VW-f ► GATES 

i03 A03 D3 = 25 V 

92CS- 22868 

Fig. 3 — CD4049A/CD4050A gate-input-protection circuit. 


Input Current (Ij): 

Input current is typically 10 picoamperes (3 to 15 volts) 
at T a = 25°C. Maximum input currents for COS/MOS 
devices are normally below 10 nanoamperes at 15 volts, and 
below 50 nanoamperes at T A = +125°C. 

AC (Dynamic) Characteristics: 

Test parameters shown in the published data are 
measured at T A = 25°C with a 15-pF load and an 
input-signal rise or fall time of 20 nanoseconds. Actual 
system delays and transition times may be increased due to 
longer input rise and fall times. Graphs are included in the 
individual data sheets to illustrate typical variation of delays 
and transition times with capacitive loading. The designer 
should use a typical temperature coefficient of 0.3%/°C for 
estimating speeds at temperatures other than +25°C. 
Propagation delays and transition times increase with rising 
temperature; maximum clock input frequencies decrease 
with rising temperatures. 

Dynamic power dissipation for each device type is shown 
graphically in the published data as a function of device 
operating frequency. 


D2* 

-«-T 

v ss 


p-WELL 

— w- 


V DD 

a 


I W T ^ M Dl = 25 V 

_[p+ ^n-SUB p+ 02 = 50 V 


GaTE T 

92CS-22883 

Fig. 4- Transmission gate-input-output protection. 



92CS- 22684 


Dl = 25 V 
D2 = 50 V 


Fig. 5 — Active (inverter) output protection. 


* This voltage may be difficult to measure depending on accuracy, 
resolution, and offset voltage of test equipment used. Although 
device output “1” or “0” limits to which RCA tests in manufacture 
are 10 millivolts, a value of 50 millivolts may be used for customer 
measurements without compromise of device quality or system 
performance. 


* THESE DIODES ARE 
INHERENTLY PART OF 
THE MANUFACTURING 
PROCESS 


451 





I CAN-6000 


Table II — Partial List of Materials and Equipment Available 
for the Control of Static Charge 


Company 

Conductive 

Foam 

Conductive 

Envelopes 

Static 

Neutralizing 

Air Blowers 

Anti-Static 

Sprays 

Conductive 

Tape 

Custom Material Inc. 
Chelmsford, Mass. 

Velofoam 

#7672 

Velobags 

#1798M 

TEC Dynastat 
DS120 


P. C. 

Contab Shunt 

3M Company 

St. Paul, Minn. 



Ionized Air 
Blower #905 

See Technical 
Bulletins 

Scotch 

Shielding Tapes 

Scientific Enterprises, Inc. 
Bloomfield, Colo. 



Micro Stat 

575 Portable 

Ionizer 



Emerson & Cuming, Inc. 
Canton, Mass. 

ECCOSORB 

LD26 



See Technical 
Bulletins 



























Solid State 
Division 


Digital Integrated Circuits 

Application Note 
ICAN-6080 


Digital- to -Ana log Conversion 
Using the RCA- CD4007A 

COS/mC3 SC 


By O. H. Schade, Jr. 


RCA COS/MOS integrated circuits have demonstrated 
outstanding performance in a wide variety of DIGITAL 
applications. Simplified circuitry, design flexibility, low 
power consumption, moderate speed, and high noise im- 
munity of these devices can complement the high trans- 
conductance of bipolar IC’s in an extension to LINEAR signal 
processing applications. This Note demonstrates the use of 
The RCA-CD4007A* COS/MOS Dual Complementary Pair 
Plus Inverter as the Digital-to-Analog (D/A) switch; the 
op-amp output stage for a Digital-to-Analog Converter 
(DAC) uses COS/MOS and bipolar transistor-array IC’s. 

deneral Considerations 

In combination with a p-channel input pair (two 
p-channels of the CD4007A), a buffer-follower COS/MOS- 
bipolar op-amp has been designed with the capability to 
attain essentially the negative supply voltage at both the 
input and output terminals. Therefore, to consider inex- 
pensive single-supply operation becomes possible without the 
sacrifice of speed and bandwidth that results with many 
monolithic bipolar IC op-amps. An additional advantage is 
the use of an MOS input stage to provide exceptionally high 
input resistance and low input current. 

A 9-bit DAC is described in this Note to illustrate this 
design approach. This system combines the concepts of 
multiple-switch COS/MOS IC’s, a low-cost ladder network of 
discrete metal-oxide film resistors, a COS/MOS-bipolar 
op-amp follower, and an inexpensive monolithic regulator in 
a simple single-supply system. An additional feature which 
complements the ever-increasing use of COS/MOS IC’s for 
digital signal processing is the readily interfaced COS/MOS- 
DAC input logic. 

Although the accuracy of a DAC system depends on 
many factors, it is the ladder network which must initiate 
properly-proportioned current or voltage outputs. Recog- 
nition of various ladder types and an appreciation of the 
design flexibility and constraints are paramount to a well 
executed DAC development. 


Resistance Networks for DAC's 

Ladder networks for DAC’s can take many forms, 
although three types are most generally encountered. Among 
the best-known variations is the current ladder shown in 
Fig. 1. This network is frequently used in combination with 
bipolar current switches which utilize a reference potential at 
the transistor base terminals to establish emitter currents 
having binary proportions. Because current summing is 
accomplished at the collectors of these transistors, the extent 
of Vre- and beta-matching of these transistors depends on 
the degree of accuracy and temperature-range requirements. 
The use of a 10/20/40/80 — kf2 network in conjunction with 
a “quad” switch, a follower amplifier, and dual power supplies 
is common. 


*For data, see bulletin File No. 479. 



Fig. 1— Current ladder-network for bipolar DAC. 


453 



I CAN-6080 


Fig. 2 shows an R/2R current ladder commonly 
employed in monolithic DAC’s. Similar resistance values can 
simplify the problem of meeting ratio-match accuracy 
requirements. This ladder must be terminated in a single 
potential (or at least invariable values) to maintain proper 
current proportions. Although the absolute resistance values 
of the circuit in Fig. 1 must temperature track the summing 
resistor (or additional compensation must be employed), the 
R/2R current ladder must maintain only a resistance ratio; it 
is the current sink which must remain stable under external 
influences. 


Fig. 3 shows a less common voltage ladder suitable for 
DAC’s using COS/MOS switches. Output potentials are 
obtained directly by terminating the ladder arms at either the 
positive or the negative power supply. Each COS/MOS 
inverter output pair functions as a double-throw switch. If 
the switch (channel) resistance is kept small compared to the 
ladder-arm resistance value, accuracy becomes a function of 
ladder supply voltage and resistance ratios alone. Operation 
of this ladder is dynamic; the current in an arm reverses as 
the logic state changes. Therefore, stray capacitances (or the 
inductance of a wirewound resistor) can limit speed as a 
result of typical settling times of several microseconds. 


SCALE ADJUST 



However, the proper selection of parallel connection of 
switches for the most significant bit (MSB) to minimize 
channel resistance can result in COS/MOS-DAC speeds which 
approach those of the best bipolar systems, particularly when 
consideration is given to follower-amplifier speed limitations. 

In the illustrative 9-bit application, a modified voltage- 
ladder design is employed. The use of 1%-tolerance metal- 
oxide film resistors can result in inexpensive networks 
suitable to about the 10-bit level. Such networks are readily 
constructed for system evaluations and may also prove to be 
suitable for production. Practical tolerance considerations 
call for variations from the “pure” R/2R configuration, as 
discussed later. 


v+ 



Fig. 3- R/2R voltage ladder-network for COS/MOS DAC. 


454 



ICAN-6080 


The COS/MOS Switch 

A typical COS/MOS switch (CD4007A) is shown in 
Fig. 4. A change in input logic level causes the output to 
swing to either the positive or the negative supply voltage. 
Power consumption is low, typically a few microwatts to a 
few milliwatts, depending on the ladder resistance and 
voltage choice. Large DAC ladder resistance values can be 
used to minimize the effects of switch resistance. Fig. 5 
shows the minimum ladder resistance value for a given 
saturation resistance to produce an accuracy of 1/2 LSB 
(Least Significant Bit), with bit number as a parameter. For 
example, the CD4007A which has a channel resistance of 
approximately 250-ohms (VdD = 10 V), requires a minimum 
ladder resistance of 100 k£2 to maintain a 9-bit accuracy 
level. Reference to the dashed “settling time” line and the 
rightside ordinate shows that the approximate settling time 
of such a network having a 10-pF node capacitance is 6 /as. 
This settling time has been based on six time constants for 
settling to 1/2 LSB, an average value for the bit range 
illustrated. If a faster settling time is required, circuits 
employing the RCA-CD4041 A can be used. 

The CD4041A 0 can drive (in a theoretical example) a 
4— kf2, 6-bit ladder network which has a settling time of 
approximately 250 ns. This is as fast as the best presently 
available monolithic bipolar switches. High-slew-rate voltage- 
follower amplifiers are needed to maintain these speed levels; 
when a COS/MOS bipolar op-amp is used, the slew rate is ap- 
proximately 30 V//us and the settling time is several hundred 
nanoseconds for a 10-V full-scale signal. This performance ap- 
proaches the state-of-the-art for monolithic op-amps, especially 
in low-cost systems. In fact, high-speed op-amps capable of 
swinging to the negative supply have not generally been 
available. 

A Voltage-Follower Amplifier for Single-Supply Operation 

It is practical to utilize commercially available COS/MOS 
and bipolar transistor-array IC’s to provide a composite 
op-amp suitable for single-supply DAC systems. Fig. 6 shows 
a unity-gain follower amplifier having a COS/MOS p-channel 
input, an n-p-n second gain stage, and a COS/MOS inverter 
output. The IC building blocks are two CA3600 E’s a 
(COS/MOS Transistor Pairs) and a CA3046° n-p-n transistor 
array. A zener-regulated leg provides bias for a 400-/2 A 
p-channel current source feeding the input stage, which is ter- 
minated in an n-p-n current mirror. Amplifier voltage-offset is 
nulled with the 10-k£2 balance potentiometer. The second- 
stage current level is established by the 20-k£2 load, and is 
selected to approximate the first-stage current level, to assure 
similar positive and negative slew rates. The COS/MOS inverter 
portion forms the final output stage and is terminated in a 
2-k£2 load, a typical value used with monolithic op-amps. 
Voltage gain is affected by the choice of load resistance 
value. The output stage of this amplifier is easily driven to 
within 1 mV of the negative supply voltage. 



Torminal No. 14 = Vqq 
T orminal No. 7 = Vgs 

92CS-20433 


Fig. 4— CD 4007 A schematic diagram. 



MINIMUM MSB NETWORK RESISTANCE — SI 


•Fig. 5— COS/M OS- DAC voltage-network requirements. 


• COS/MOS Quad True/Complement Buffer 
A For data, see bulletin File No. 619. 

“For data, see bulletin File No. 341. 


455 



I CAN -6080 


♦ 15V 



Fig. 6— Voltage-follower amplifier for single-supply opera- 
tion. 


Compensation for the unity-gain non-inverting mode is 
provided by Miller feedback of 39 pF and a 300-pF by-pass 
capacitor shunting one-half the driving current (1-2 MHz). 
Unity-gain bandwidth is just under 10 MHz and the 
open-loop gain is 75 dB. Fig. 7 shows the gain-bandwidth 
characteristics for this circuit. A potential latch situation at 
the bipolar mirror is avoided by use of resistor-capacitor 
network (R=lk£2, C=150pF), which limits the dc 
feedback through the p-channel gate-protective diode. 

The amplifier response to 4-V input pulses is shown in 
Fig. 8. Although the slew rate is approximately 30 V//is, the 
settling time is significantly prolonged (approximately 2 ps) 
as a result of the method of second-stage biasing when the 
output swings near the negative supply. For many applica- 
tions, this speed loss is not significant. If a faster amplifier is 
desired, the load resistor can be replaced with a p-channel 
CA3600E current source similar to that used for the first 
stage. In fact, it may be desirable to change the current and 
resistance values to optimize the gain/speed trade-off for a 
particular application. For example, if higher gain is desired 
for less follower offset, the 20-k£2 resistance value can be 
increased. The choice of output load resistance also affects 
the gain/speed compromise. 



Fig. 7— Voltage-follower open-loop gain characteristics. 


456 



I CAN -6080 


A 9-Bit COS/MOS DAC 

An example of a 9-bit DAC is shown in Fig. 9. Three 
CD4007A IC packages perform the switch function using a 
10-V logic level. A single 15-V supply provides a positive bus 
for the follower amplifier and feeds the CA3085 a voltage 
regulator. The “scale-adjust” function is provided by the 
regulator output control which is set to a nominal 10 V in 
this system. The line-voltage regulation (approximately 0.2%) 
permits 9-bit accuracy to be maintained with a variation of 
several volts in the supply. System power consumption 
ranges between 70 and 200 mW; a major portion is dissipated 
in the load resistor and op-amp. The regulated supply 
provides a maximum current of 440 pA of which 370 pA 
flows through the scale-adjust leg. 

The resistor ladder is composed of 1 -per-cent tolerance 
metal-oxide film resistors available from several manu- 
facturers at modest cost. The five arms requiring the highest 
accuracy are built of series and parallel combinations of 
806-k£2 resistors from the same manufacturing lot. The ratio 
match between resistance values is in the order of 0.2%, 
usually without need for special selection. The construction 
of a “standard” with eight parallel resistors assures a high 
probability that ratio matching will be satisfactory. If the 
usual assumption that tolerances can be improved with the 
square-root of the sample number is adopted, the loss of 


tolerance is slower than the increase of resistance value 
toward the LSB. Once the most critical match has been 
attained, therefore, subsequent ratio matches should be more 
than adequate. An impedance-matching resistor is used 
between the fifth and sixth bits to permit ladder completion 
with individual resistors of the most desirable values where a 
1% tolerance is adequate. This resistor value is chosen as 
R5-1/2R6, to terminate the first five bits in a fifth-bit value 
(the impedance is 1/2R6 looking left into that node). 



0.5 m s/DIVISION 

92CS-20430 


Fig. 8- Amplifier response to 4- V input pulses. 



REQUIRED 

BIT RATIO-MATCH 

1 STANDARD 

2 ± 0.1 % 

3 ±0.2 % 

4 ±0.4 % 

5 ±0.8 % 

6-9 ± I % ABS. 


ALL RESISTANCES 
IN OHMS 


SEE FIG. 6 
FOR COMPLETE 
DIAGRAM OF 
VOLTAGE FOLLOWER 


92CM-2043I 


Fig. 9- 9-bit DAC using COS/MOS CD4007A. 


457 







I CAN -6080 


The follower amplifier has the offset adjustment nulled 
at approximately a 1-volt output level. System operating 
potentials are shown in Table I, where each bit is set “low” 
individually to observe the progression of output values. The 
positive ladder-supply voltage was adjusted to 10.010 V to 
provide a small compensation for the MSB switch resistance. 
A high-impedance 5-digit multimeter, such as the DANA 
5330 or equivalent, is needed for direct measurement of the 
ladder output, and is invaluable during system development 
and evaluation. Table I shows ideal potential values, system 
output, and ladder output and illustrates the sources of 
system inaccuracy. The system output maintains propor- 
tional accuracy within ±5.6 mV, or ± 1/4 LSB. 

Fig. 10 shows the system output response to a 4-V logic 
pulse. The ringing is caused by the voltage follower, and the 
more gradual transients are caused by voltage-follower and 
ladder time constants. Settling time to 1/2 LSB is 5 jus. 

This 9-bit COS/MOS-DAC demonstrates accuracy and 
simplicity with economical components and modest power- 
supply requirements. In addition, the design flexibility 
afforded by the COS/MOS building blocks simplifies the 
generation of DAC systems tailored to individual needs. 
COS/MOS switches used in conjunction with COS/MOS 
counters also find application in Analog-to-Digital Con- 
version Systems. The low-power and high noise-immunity 
features of these devices make them attractive A/D system 
components. 



2 /DIVISION 

92CS-20432 


Fig. 10- System response to most-significant-bit logic pulse. 


When incorporating RCA Solid State Devices in equipment, it is 
recommended that the designer refer to "Operating Considerations for 
RCA Solid State Devices", Form No. ICE-402, available on request 
from RCA Solid State Division, Box 3200, Somerville, N.J. 08876. 


Table I. Set Of Values For 10.010-V Regulated Supply Voltage 


BINARY 

WORD 

IDEAL 

POTENTIAL 

(V) 

SYSTEM 

OUTPUT 

(V) 

LADDER 

OUTPUT 

(V) 

SYSTEM 

ERROR 

(mV) 

VOLTAGE 

FOLLOWER 

OFFSET 

(mV) 

LADDER & 
SWITCH ERROR 
(mV) 

POSITIVE 
SWITCH DROP 
(mV) 

000000000 

9.9802 

9.9856 

9.9915 

+ 5.4 

- 5.9 

+ 11.3 

- 

011111111 

5.0000 

4.9959 

4.9997 

-4.1 

- 3.8 

- 0.3 

14.8 

101111111 

2.5000 

2.4996 

2.5023 

-0.4 

- 2.6 

+ 2.3 

11.0 

110111111 

1.2500 

1.2554 

1.2565 

+ 5.4 

- 1.0 

+ 6.5 

6.5 

111011111 

0.6250 

0.6233 

0.6226 

-2.7 

+ 0.7 

- 2.4 

3.2 

111101111 

0.3125 

0.3133 

0.3113 

+ 0.8 

+ 2.1 

- 1.2 

1.7 

111110111 

0.1568 

0.1603 

0.1571 

+ 3.5 

+ 3.2 

+ 0.3 

14.0 

111111011 

0.0784 

0.0826 

0.0786 

+ 4.2 

+ 4.0 

+ 0.2 

11.8 

111111101 

0.0397 

0.0439 

0.0393 

+ 4.2 

+ 4.6 

- 0.4 

6.8 

111111110 

0.0198 

0.0245 

0.0195 

+ 4.7 

+ 5.0 

- 0.3 

3.6 

111111111 

0.0000 

0.0056 

0.0000 

+ 5.6 

+ 5.6 

0.0 

_ 


458 



ICAN-6086 



Solid State 
Division 


Digital Integrated Circuits 

Application Note 
ICAN-6086 


Timekeeping Advances 
Through COS/MOS Technology 


by S.S. Eaton 


Most COS/MOS timing circuits consist of three basic 
parts: an oscillator, or main timing standard; some digital 
processing logic, usually in the form of frequency-dividing 
circuits; and logic-circuit drivers for mechanical or electrical 
output devices controlled by the digital processing logic. The 
oscillator is perhaps the most important because the accuracy 
of the total COS/MOS timing system is entirely dependent 
upon the accuracy of the oscillator. This Note discusses basic 
oscillator design considerations, practical COS/MOS oscil- 
lator circuits, and some typical COS/MOS timing-circuit 
applications. 

BASIC OSCILLATOR DESIGN CONSIDERATIONS 

A basic oscillator circuit consists of an amplifier and a 
feedback section, as shown in Fig. 1. For oscillation to occur, 
the gain of the amplifier times the attenuation of the 
feedback network must be greater than one. In addition, the 
total phase shift through the amplifier and feedback network 
must be equal to n times 360 degrees, where n is an integer. 
These conditions imply that oscillations occur in any system 
in which an amplified signal is returned in phase to the 
amplifier input after being attenuated less than it was 
originally amplified. In such a system, any noise present at 



Fig. 1— Basic oscillator circuit. 


the amplifier input causes oscillation to build up at a rate 
determined by the loop gain, or afi product, of the over-all 
circuit. 

The frequency stability of an oscillator is primarily 
dependent upon the phase-changing properties of the 
feedback network. For high stability, quartz crystals and 
tuning forks are commonly used as feedback network 
elements. The quartz crystal is the more popular because of 
its higher Q or greater inherent frequency stability. 

Selection of Crystal Operating Mode 

Fig. 2 shows the equivalent circuit of a quartz crystal, 
and Table I lists typical component values of the elements 
included in the equivalent circuit for different crystal cuts 
and operating frequencies. The basic circuit can be resolved 
into equivalent resistive (R e ) and reactive (X e ) components. 
Fig. 3 shows curves of these components as functions of 
frequency for a typical 32.768-kHz crystal. Fig. 3(b) shows 
two points at which the crystal appears purely resistive, (i.e., 
points at which Xe = 0). These points are defined as the 
resonant (f r ) and antiresonant (f a ) frequencies. Series- 
resonant oscillator circuits are designed to oscillate at or near 
f r . Parallel-resonant circuits oscillate between f r and f a , 
depending upon the value of a parallel loading capacitor, as 
discussed later. In contrast to series-resonant circuits, parallel 
resonant-circuits work best with amplifiers that have high 
input impedances. The parallel-resonant circuit, therefore, is 
most applicable to crystal oscillators that employ COS/MOS 
amplifiers.* 

Feedback-Circuit Configuration 

A feedback circuit suitable for use with a parallel- 
resonant oscillator circuit is shown in Fig. 4. This circuit, 
known as a crystal pi network, is intended for use after an 
amplifier that provides a 180-degree phase shift. The pi 
network is designed to provide the additional 180-degree 
phase shift required for oscillation. The phase angle for this 
type of feedback circuit is extremely sensitive to a change in 
frequency, a condition necessary for stable oscillation. If the 
equivalent resistance of the crystal were in fact zero (infinite 


10-72 


459 



ICAN-6086 



■— r K 1 

Co 

92 CS- 20506 

Fig. 2— Equivalent circuit for a quartz crystal. 


Table I — Typical Component Values for Common Cuts 
of Quartz Oscillator Crystals 


FREQUENCY 

32 kHz 

280 kHz 

525 kHz 

2MHz 

Cut 

XY Bar 

DT 

DT 

AT 

R s (ohms) 

40K 

1820 

1400 

82 

L (Hy) 

4800 

25.9 

12.7 

0.52 

Ci (pF) 

0.00491 

0.0125 

0.00724 

0.0122 

C 0 (pF) 

2.85 

5.62 

3.44 

4.27 

C 0 /Ci 

580 

450 

475 

350 

Q 

1 25000 

25000 

30000 

’ 80000* 


Q), a change in the phase angle of the feedback circuit would 
not cause any change in oscillator frequency; the frequency, 
therefore, would be insensitive to any phase change in the 
amplifier. Though practical crystals allow only a slight 
change in frequency for large variations in phase angle, the 
amplifier phase angle should, to the extent possible, be made 
independent of temperature and supply-voltage variations in 
order to minimize the phase compensation required of the 
feedback network. Any required phase compensation will, of 
course, dictate a corresponding change in the frequency of 
oscillation consistent with practical values of crystal Q. For 
this reason, the equivalent resistance of the crystal should be 
maintained as low as possible, and the amplifier should be 
designed to roll off at frequencies greater than the crystal 
frequency. 

Oscillator Amplifier 

Fig. 5 shows a COS/MOS amplifier circuit that may be 
used to provide the amplification function in a crystal- 
controlled oscillator. The amplifier is biased so that the 
output voltage VOUT is equal to the input voltage Vjn or 
typically is equal to one-half the supply voltage Vdd, 0- e -> 
VOUT = VlN = Vdd/ 2). Biasing is accomplished by means 
of a resistor that has a value high enough to prevent loading 
of the feedback network, yet that is low in comparison to 
the amplifier input resistance. Resistor values of 10 to 500 
megohms will satisfy these criteria; however, lower values in 
the order of 15 megohms are generally used to allow greater 
input leakage without, any severe change in bias point. The 
gain of the amplifier varies with supply voltage, the size of 
the n- and p-channel MOS transistors, and the sum of the 
threshold voltages of the n- and p-channel transistors. When 
an oscillator amplifier is designed to roll off at frequencies 
greater than the crystal frequency, care must be taken to 



Fig. 3— Impedance characteristics of a quartz oscillator 
crystal: (a) equivalent crystal resistance as a 
function of frequency; (b) equivalent crystal 
reactance as a function of frequency. 


R 

OAAAr- 

C T 


0 


o 


csrr 


92CS- 20503 

Fig. 4- Crystal pi-type feedback network. 



Fig. 5— COS/MOS amplifier. 


460 






ICAN-6086 


assure that the transistor sizes are large enough for the 
particular supply voltage used and range of threshold voltages 
expected. For any circuit, though, the sum of the threshold 
voltages of the n- and p-channel transistors must always be 
less than the supply voltage. 

The oscillator amplifier governs, to a certain extent, the 
selection of the components for the feedback network. The 
amplifier current consumption is strongly dependent upon 
the attenuation across the feedback network. As the 
attenuation becomes greater, the signal at the amplifier input 
becomes smaller, which, in turn, increases the amplifier 
current consumption. Large voltage swings at the amplifier 
input cause little current to flow because the resistance of 
either the n- or p-channel transistor is high during a large 
portion of the cycle. On the basis of power considerations, 
it is best to design the feedback network for a small attenu- 
ation. 

Equivalent Crystal Resistance 

The equivalent resistance R s of the crystal should be 
maintained as small as possible in order to obtain minimum 
attenuation across the feedback network. For any given 
circuit, the oscillator current always increases with a rise in 
crystal resistance. This factor and stability considerations 
provide strong arguments for the purchase of crystals that 
have low series resistance, although the usual cost tradeoffs 
prevail. 

Crystal Load Capacitance 

Another factor that influences the over-all power 
consumption is the size of the pi-network capacitor at the 
amplifier output. For minimum current consumption, this 
capacitor, obviously, should be kept small. This condition, 
however, does not always imply high frequency stability. The 
choice of the capacitor value first involves a determination of 
the over-all crystal load capacitance. The phase angle of the 
feedback network approaches 180 degrees when the crystal 
equivalent reactive component Xg is equal to the reactance 
(XCL) of a capacitor placed in parallel with the crystal. 
Fig. 4 shows that the effective capacitance across the crystal 
consists of the two pi-network capacitors in series. If the 
value of the equivalent reactance Xe at the crystal frequency, 
as may be determined from Fig. 3(b), is equal to the value of 
the crystal load capacitance Cl , then the equivalent value 
of the two series-connected pi-network capacitors can be 
calculated from the following relationship: 

Cf = 1 /wXg (1) 

The value of the load capacitance Cl, in general, is chosen 
first, and the crystal manufacturer is required to cut the 
crystal to oscillate at the desired frequency for the specified 
value of load capacitance. 

The choice of a load capacitance is important in terms of 
over-all power consumption and frequency stability. Higher 
values of Cl generally improve frequency stability, but also 
increase power dissipation. The timing industry presently 
seems to have standardized on values of Cl between 10 and 
20 picofarads. 


The choice of the total equivalent load capacitance Cl 
only fixes the series sum of the two pi-network capacitors. 
The individual capacitors themselves can be found from the 
following equations: 


C T = 4CL/(l-5fReC L ) 

(2) 

Cs = 4CL/(3 + 5fReC L ) 

(3) 


The actual value of Cs used in the feedback circuit 
should be about 3 picofarads less than the calculated value to 
allow for the amplifier input capacitance. The value of the 
amplifier output capacitor Ct should not normally be fixed. 
A trimmer capacitor should be placed in parallel with, or 
used in place of, a fixed output capacitor to allow for 
variations in stray capacitance and circuit components. The 
mid-range value of the output capacitor combination should 
be equal to the calculated value of Ct- 

Frequency-Trimming Capability 

The required capacitance range for the oscillator trimmer 
capacitor is determined by the variation in oscillation 
frequency with a change in load capacitance. 2 The total 
frequency-trimming range of a crystal-controlled oscillator 
circuit is mainly a function of the crystal characteristics, or 
more explicity, is inversely proportional to the slope of the 
crystal reactance curve, shown in Fig. 3(b). The slope of this 
curve is a function of the difference between the resonant 
frequency f r and the antiresonant frequency f a . This 
frequency difference, in turn, is a function of the crystal 
capacitance ratio C 0 /C i , where C 0 and C i are the inherent 
shunt and series capacitances, respectively, of the crystal 
structure, as shown in Fig. 2. The slope of the reactance 
curve is also a function of the total external crystal load 
capacitance Cl- As shown in Fig. 3(b), this slope decreases as 
the equivalent reactance increases, (i.e., for smaller values of 
the capacitance Cl). Fig. 6 and Table II show trimming-range 
data for a typical 32.768-kHz crystal that has a capacitance 
ratio C 0 /Ci of 580. These data show that smaller values of 
load capacitance result in greater trimming-range capability. 

Temperature Stability 

Another important oscillator consideration is tempera- 
ture stability. Most crystals have a negative parabolic 
temperature coefficient. ^ Fig. 7 shows a typical curve of the 
variation in crystal frequency as a function of temperature. 
The frequency of the total oscillator circuit also exhibits a 
similar temperature dependence. Temperature compensation 
of the over-all oscillator circuit can be achieved by use of a 
capacitor that has a positive parabolic temperature coef- 
ficient in the pi feedback network. 3 For comparison, Fig. 7 
also shows a typical resultant curve for the over-all circuit. 

The temperature characteristics of a crystal are deter- 
mined to a large extent by the crystal cut. Popular 
low-frequency cuts include the NT and XY Bar. The XY Bar 
is the more popular of the two types because it can be made 
smaller for a given Q and is easier to trim. The disadvantage 
of a slightly lower shock resistance of XY Bar crystals is 
compensated by the superior aging chacteristics of this type. 


461 



I CAN-6086 



92CS- 20499 

Fig. 6— Frequency as a function of toad capacitance for a 
typical 32-kHz crystal. 

AT-cut crystals, when used at frequencies greater than 1 MHz, 
are characterized by excellent temperature stability and 
ruggedness. Temperature characteristics for this type of 
crystal cut as well as for the XY Bar and NT types are shown 
in Fig. 8. 

Crystal Dimensions 

Size is also an important consideration in the design of 
oscillator crystals. The length of quartz required for any 
given cut is inversely proportional to the square root of 
frequency. Dimensions for a typical packaged 32-kHz, XY 
Bar crystal are 0.6 inch by 0.2 inch by 0.11 inch. The 
smallest XY Bar crystals currently available have dimensions 
in the order of 0.53 inch by 0.2 inch by 0.1 1 inch. A 1-MHz 
AT-cut crystal is significantly larger; however, dimensions 
again decrease with frequency. Crystal manufacturers are 
currently working to develop wristwatch-size AT-cut crystals 
with the anticipation of circuit improvements that will allow 
low-current operation at high frequencies. 

Crystal Shock Resistance and Aging Rate 

A prime concern of the timing industry today is that of 
crystal shock resistance and aging. The aging of a crystal 
results primarily from aging of the mounting material rather 


Table II - Trimming Data for a Typical 32-kHz 
Quartz Oscillator Crystal 



LOAD CAPACITANCE, CL 

TRIM 

5 pF 

11.5 pF 

20 pF 

32 pF 

±20 PPM 

-0.45 

Pf 

+0.51 

-1.6 

pf 

+2.0 

-3.7 

Pf 

+5.5 

-8.0 

Pf 

+ 14.7 

± 25 PPM 

-.55 
■ pf 
+.65 

-1.9 

Pf 

+2.6 

-4.5 

Pf 

+7.3 

-9.4 

pf 

+20.5 

±30 PPM . 

-0.66 

pf 

+0.79 

-2.3 

pf 

+3.3 

-5.2 

Pf 

+9.3 

-10.7 

Pf 

+27.9 



92 CS- 20508 

Fig. 7— Effect of temperature on crystal frequency. 




Fig. 8— Frequency-temperature characteristics for various 
crystal cuts: (a) XY-Bar and NT cuts; (b) A T cut. 


than from aging of the quartz itself. The mounting material 
enters into the crystal equivalent circuit, and the slowest 
aging rate results when the mount consists of the least 
amount of supporting material. This condition of course, 
results in lower shock resistance, and an optimum trade-off 
must be achieved. At present, 32-kHz crystals can be made 
that can withstand a mechanical shock of about 1500 G’s 
applied for 0.5 millisecond and that have aging rates that 
result in a frequency change of 2 to 5 parts per million for 


462 






I CAN-6086 


the first year and essentially no aging thereafter. Any 
mechanical or thermal shock, however, will interrupt the 
normal aging process. The aging rate of 2 to 5 parts per 
million presently appears acceptable to the timing industry, 
although shock resistances of 3,000 to 5,000 G’s are desired. 
This shock level corresponds approximately to the shock 
experienced by dropping the crystal from a height of one 
meter onto a hardwood floor. 

PRACTICAL OSCILLATOR CIRCUITS 

The basic amplifier, feedback-network, and crystal 
considerations discussed in the preceding paragraphs can be 
combined in the design of COS/MOS oscillator circuits. In 
the circuits, the crystal selected has an equivalent resistance 
R e of 50 kilohms and is cut to operate at a frequency of 
32.768 kHz with a load capacitance Cl of 10 picofarads. The 
values of pi feedback-network capacitors Cj and Cs can be 
calculated by use of Eqs. (2) and (3) as Op = 43 picofarads 
and Cs = 13 picofarads. The value of the feedback-network 
resistance R can be calculated as follows: 

_(3Xe + 0.27 R e ) (X e - 0.8 R e ) 

R 16 Re 

~ 1 M£2 

This value is the maximum value of resistance allowd for a 
minimum feedback-network attenuation of 0.75, a value 
chosen on the basis of power and stability considerations.* 
The calculated value of R includes any fixed resistance plus 
the amplifier output resistance. Because the output resistance 
is often appreciable and varies with supply voltage, transistor 
size, and threshold voltages, it is generally best to add 
resistance experimentally until the desired power consump- 
tion and frequency stability are reached. The effect of this 
resistance on operating current and frequency stability can 
be predicted from data given in Table III for the three 
different COS/MOS crystal oscillator circuits shown in Fig. 9. 
In each circuit, the pi-network capacitors Cx and Cs are 39 
picofarads and 10 picofarads, respectively. These capaci- 
tances are slightly less than the calculated values because of 
stray and amplifier capacitances. 

The circuit shown in Fig. 9(a) combines the amplifier and 
feedback circuits shown in Fig. 4 and 5. Although theory 
predicts that an increase in the values of the feedback- 
network resistor R will result in increased frequency 
stability, the circuit performance data given in Table III show 
no significant improvement in this characteristic. This result 
indicates that the circuit instability can be attributed almost 
entirely to phase instabilities of the amplifier. This assump- 
tion is verified by data taken from the circuits shown in 
Figs. 9(b) and 9(c) in which the required feedback-network 
resistance is incorporated into the amplifier as a fixed value. 
The resistors essentially fix the amplifier phase shift so that 
greater stability results. As the data show, use of these 
resistors also results in a decrease in the total current 
consumption. Because of the two fixed resistors, the circuit 
of Fig. 9(b) shows the least current consumption and also the 
greatest stability. 


Table III — Typical Oscillator Data 


Circuit 

Value of 

R (£2) 

v D d 

(Volts) 

Current 
(H A) 

Frequency 
Stability 
Vqd = 1.45V 
to 1.6V 

9(a) 

0 

1.60 

4.0 

2.8 

" 

0 

1.45 

3.1 

" 

100K 

1.60 

3.1 

2.6 

" 

" 

1.45 

2.4 

" 

200K 

1.60 

2.9 

2.6 

" 

" 

1.45 

2.1 

9(b) 

100K 

1.60 

2.3 

.3 

" 

" 

1.45 

2.0 

" 

" 

1.1 

1.5 

" 

150K 

1.60 

1.8 

.2 

" 

" 

1.45 

1.6 

" 

" 

1.1 

.95 

9(c) 

200K 

1.60 

5.0 

.6 

" 

" 

1.45 

4.4 

" 

300K 

1.60 

3.5 

.5 

" 

• „ 

1.45 

3.0 


As mentioned previously, the amplifier feedback resistor 
should not significantly load the crystal feedback network. 
The resistor value at which loading begins to occur can be 
determined from a curve of circuit operating frequency as a 
function of feedback resistance. Fig. 10 shows such a curve 
for the circuit shown in Fig. 9(b). This curve indicates that 
15 megohms is a suitable value for the feedback resistor. 

FREQUENCY DIVIDERS 

Because of restrictions on crystal size and cost, oscillator 
frequencies of 8192 Hz, or higher, are generally used for 
electronic timing circuits. The use of such high crystal 
frequencies usually requires division of the oscillator fre- 
quency to a more convenient value. Synchronous motors, for 
example, are often driven by frequencies between 0.5 Hz and 
64 Hz. Numeric readouts for digital clocks or wristwatches 
require pulses at least every second, minute, and hour. The 
necessity for frequency division becomes clear if one 
considers the wide variety of timing intervals that may be 
required for certain applications. 

The basic frequency-dividing circuit, shown in Fig. 11, 
consists of a master-slave D-type flip-flop connected as a 
binary counter stage. N stages may be cascaded with the final 
output frequency equal to 2 — N times the input frequency. 
Division by integers other than powers of 2 can also be 
accomplished by use of gating techniques. For example, a 
divide-by-60 counter implemented as shown in Fig. 12, can 
be used to obtain minutes from seconds. 


463 




I CAN-6086 





Fig. 9— Typical COS/MOS crystal-oscillator circuits. 

A basic block diagram of a typical digital clock that 
employs divide-by-60 counters is shown in Fig. 13. The 
display for the clock is designed to be multiplexed in that 
new information is provided to only one of the six readout 
characters, while the eye itself holds the previous state of the 
other five. The multiplexing unit consists of COS/MOS 
transmission gates controlled by a six-stage ring counter that 
also addresses each character sequentially. This type of 



AMPLIFIER FEEDBACK RESISTANCE ( R f )— MEGOHMS 

92CS- 20494 

Fig. 10— Oscillator frequency as a function of amplifier 
feedback resistance. 


MASTER | SLAVE 



(b) AN OPEN CIRCUIT WHEN CONTROL INPUT I IS"HIGH" 
AND CONTROL INPUT 2 IS "LOW* 


92CS- 20511 

Fig. 11 — Basic frequency-dividing stage. 
circuit is particularly applicable for driving light-emitting 
diode displays. 

Light-emitting diodes, as well as other readout devices, 
require some form of driving circuitry which is often unique 
to the driven device. Other typical readout devices include 
stepping motors, balance-wheel motors, tuning-fork motors, 
and liquid-crystal displays. 

Motors are frequently driven by low-impedance MOS 
transistor drivers. The waveforms required depend upon the 
particular type of motor. Rotary stepping motors require a 
pulsed waveform such as that shown in Fig. 14(a). The motor 
advances one position (for example 180 degrees) on each 
pulse. Fig. 14(b) shows a COS/MOS circuit that may be used 
to generate this type of waveform. The crystal frequency and 
the number of countdown stages for this circuit determine 
the pulse frequency. The duty factor is controlled by two 
resettable flip-flops that are clocked inversely by the last 
counting stage and reset by an intermediate stage. The 
output waveform from this circuit will have a duty factor 
that is exactly given by 2 * ~ * — N where I is the number of 
the intermediate stage used to reset the shaping flip-flops and 
N is the total number of frequency-divider stages. 

A tuning-fork motor consists of two coils wired in series 
and wound on either side of the fork. A subdivision of the 
crystal frequency drives the coils which electromagnetically 
vibrate the fork. The fork can be linked to an index wheel 
that, in turn, can drive the hands of a watch. 

A balance-wheel motor consists of a coil fixed near the 
periphery of a pivoted balance wheel. Permanent magnets are 
attached to one side of the wheel and counterweights to the 
other. The coil can be energized by pulses supplied to the 
gate of an n-channel MOS transistor with the coil connected 
between the drain and the supply voltage of the transistor. 
When the coil is energized, the balance wheel swings toward 
the coil. The momentum of the wheel moves it beyond the 
coil, and spring action then forces it back. Repeated cycles 
generate a back-and-forth type motion which can be linked 
to a wheel for driving the hands of a watch or clock. 

Seven-segment liquid-crystal numerals can be driven as 
shown in Fig. 15. An ac voltage is required across each 


464 




ICAN-6086 


4 10 



92CS- 20496 

Fig. 12— C0S/M0S divide-by-60 counter. 



TO SEVEN SEGMENTS OF 
All DISPLAY NUMERALS 


92 CS - 204 9 7 


Fig. 13— Typical COS/MOS digital dock. 


segment of the display to assure long life. For this purpose, a 
60-Hz square wave is applied to one input of each of seven 
exclusive-OR gates. The logic state present at the other input 
determines whether the segment will transmit or scatter light. 

Liquid-crystal displays can be made for operation in 
either transmissive or reflective modes. The transmissive- 
mode type requires a light source behind the display. The 
light will either be transmitted or not depending upon the 
voltage across the segment. In the reflective-mode type, 
ambient light can be scattered by the liquid crystal material, 
or reflected from a mirrored surface placed behind the 
numeral. If displayed correctly, excellent contrast between 
“on” and “off’ segments can be obtained when reflecting or 
scattering only ambient light. 

The light scattering property of liquid-crystal displays 
offers two major advantages. First, the problem of washout in 
high intensity light is prevented. Washout has always been a 
problem with light generating displays. Second, because the 
displays do not generate light, they require negligible power. 


In fact, liquid crystals require the least amount of power of 
any currently available type of display 

Light-emitting diodes are somewhat simpler to drive than 
liquid crystals because signals to individual segment and/or 
numeials can be easily multiplexed. Fig. 16 shows a typical 
multiplexed driving circuit. The n-p-n transistor, which is 
common to the cathode of all segments in each numeral, can 
be turned on to address only one particular numeral. The eye 
will hold the reading from all off segments long enough for at 
least six numerals to be multiplexed. 

COS/MOS TIMING-CIRCUIT APPLICATIONS 

The choice of a readout device depends, of course, upon 
the application involved and to a certain extent upon the 
individual characteristics of the device itself. Special 
considerations for readout devices are perhaps best treated in 
a discussion of special requirements for three important 
timing-circuit applications, namely, wristwatches, wall 
clocks, and automobile clocks. 


465 












I CAN-6086 




b n n — 

T|'T| N *2 I_I T2=T|n*2 N 

1 ... * 92CS-20495 

lb; 

Fig. 14— Generation of required stepping-motor waveforms: (a) required driving 
waveform across stepping motor; (b) COS/MOS driving circuit and output 
waveforms applied to motor control winding. 


Wristwatches 

In any wristwatch application, size and total operating 
current are perhaps the two most important considerations. 
The total timing circuitry, together with the battery and 
readout device, must fit into a relatively fixed size and have a 
current consumption small enough to allow at least one year 
of life. Size and power considerations also become important 
in crystal selection. The size and cost of a crystal decreases 
with increases in frequency up to about 1 MHz. The power 
consumption of the oscillator and counter increases with 
frequency. On the basis of these considerations, the most 


popular crystal frequency for wristwatches at present is 
32.768 kHz. Typical packaged sizes for this crystal and 
various available crystal oscillator circuits were discussed in 
an earlier section of this Note. 

The choice of a readout device also involves considera- 
tions of size and power as well as, of course, marketing 
considerations. If conventional-hand movements are chosen, 
a motor type of drive must be selected. No great size 
advantage exists over any of the various motor types used in 
this type of application. In addition, all types can be 
designed to operate from 1.1 to 1.6 volts with average 



AVERAGE VOLTAGE 
ACROSS ANY SEGMENT 
= 0 VOLTS 


Fig. 15— COS/MOS liquid-crystal driving circuit. 


466 









I CAN-6086 


N CHARACTERS 


V 


y 



FROM 4- N PLUS N DECODED OUTPUT 
COUNTER 


92CM-20493 

Fig. 16— Multiplexing driving circuit for light-emitting diodes. 


current consumptions of about 10 microamperes. Sensitivity 
to vibration, however, is one separating characteristic. 
Although balance-wheel motors can be designed to compen- 
sate to a certain extent for speed variations produced by 
vibrations, the stepping motor, which is insensitive to 
vibration, remains superior in this respect. At present, 
however, the stepping motor is the more expensive of the 
two types. 

Light-emitting diodes require a minimum of two battery 
cells for proper operation. The required current can be kept 
to about 2 milliamperes per segment when the diodes are 
pulsed from a six-stage ring counter, as shown in Fig. 13. A 
duty factor of 16 per cent is achieved with this arrangement. 
Because of the high current, however, a continuously 
operating battery-powered display is not possible, and a 
“readout on demand” watch is then necessary. 

Continuously operating liquid-crystal displays are 
possible and practical. RCA wristwatch displays employ 
liquid-crystal material having resistivities of about 5 x 10^ 
ohms per centimeter, which at a 0.5-mil spacing results in a 
resistance of 6.3 megohms per square centimer. With all 
segments energized, the display consumes only about 1 
microampere of current at 15 volts. Liquid crystals, however, 
require a minimum supply of 12 volts to assure good contrast 
between on and off segments. For single-cell operation, a 
dc-to-dc converter must be used to step the voltage up to the 
required 12-to- 15-volt level. Transformer and capacitor 
voltage-doubling circuits with conversion efficiencies of 
about 75 per cent are typically used for this purpose. 

Because current consumption is such an important 
consideration for wristwatch circuits, the careful considera- 
tion given to the choice of a battery is easily understood. 
Small silver-oxide and mercury cells are presently popular for 
wristwatch use. Pertinent information on these types of 


Mallory cells is shown in Table IV. Most of the cells listed 
will last at least one year with a motor current of 10 
microamperes and a total oscillator and divider current less 
than 5 microamperes at an oscillator frequency of 32.768 
kHz. The voltage for both types of cells is relatively constant 
during the active life listed and falls off rapidly thereafter. 
Typical end-of-life voltages at 1.1 volts for mercury cells and 
1.45 volts for silver-oxide cells. Either type of cell works 
equally well with RCA silicon-gate COS/MOS circuits which 
operate from supply voltages as low as 1.1 volts. 

Wall Clocks 

Size and power limitations for clocks are not as 
restrictive as those for wristwatches. For this reason, 
lower-cost, higher-frequency crystals may be used. The 
optimum range of crystal frequencies presently appears to be 
from 131 kHz to 524 kHz. All the oscillator considerations 
given previously for operation at 32 kHz apply equally well 
to this higher frequency range. The oscillator circuit 
configuration shown in Fig. 9(b) is still the optimum type; 
however, the value of the source resistors must be decreased 
to assure adequate gain at the higher frequencies. Source 
resistors are often best chosen experimentally by gradually 
increasing the resistance until an output voltage swing of 30 
to 70 per cent of the supply voltage Vdd is reached. Data 
taken from a typical 262-kHz oscillator circuit that employs 
two 10-kilohm source resistors and a DT-cut, 262-kHz crystal 
are shown in Table V. The table also shows typical counter 
current. 

The most popular readout devices for clocks are 
conventional-hand movements and liquid-crystal displays. 
Continuously operating light-emitting-diode numerals con- 
sume too much current even for long life of C- and D-size 
batteries. In contrast, a typical RCA four-digit liquid-crystal 


467 






I CAN-6086 


Table IV — Typical Data for Mallory Watch Cells 


Type 

Voltage 

Capacity 
juA yrs. 

Height 

(in.) 

Diameter 

(in.) 

WH3 

1.35 

25 

0.208 

0.455 

WS 14 

Type A 

1.55 

19 

0.210 

0.455 

W4 

1.35 

11 

0.139 

0.455 

WS11 

1.55 

11 

0.164 

0.455 

10 R 101 
(EXP) 

1.35 

36 

0.190 

0.610 

10 L 19 
(EXP) 

1.55 

27 

0.190 

0.610 

WD4 

1.36 

14 

0.149 

0.594 

WD5 

1.36 

23 

0.110 

1.003 


display having a 0.4-inch-by-0.6-inch numeral consumes only 
100 microamperes of current with all segments energized. 

Motors for driving the clock hands are typically of the 
balance-wheel or continuously rotating synchronous types. 
Sensitivity to vibration is usually not a restriction; hence, the 
balance wheel motor can be successfully used in place of the 
more expensive stepping motor. Clock motors typically 
require about 300 to 450 microwatts of power, or average 
currents of 200 to 300 microamperes at 1.5 volts. 

These currents, together with the oscillator and counter 
currents given in Table V, can now be compared with 
typical battery capacities. Battery information extrapolated 
from published Eveready data on popular AA-, C-, and D-size 
cells is listed in Table VI. ^ Most of the battery current is 
consumed by the motor, and if a total current of 250 
microamperes is assumed, the data show a carbon-zinc C cell 
as the minimum size battery required for one year of life. 

Auto Clocks 

Auto clock circuits are somewhat unique in that power 
considerations are not nearly as restrictive as in other 
portable applications. Although the low-power feature of 
COS/MOS circuits is helpful, the main advantages obtained 


Table V — Typical Data for 262-kHz Oscillator 
and Counter Circuits 


Product 

VDD 

(Volts) 

Oscillator 

Current 

(MA) 

Counter 

Current 

(mA) 

Freq. 

Stability 

(ppm) 

Silicon-Gate 

1.1V 

7 

7 

2.0 ppm 

1.4 

1.2 

" 

1.3V 

9.5 

9 

" 

1.5V 

11.5 

10 

" 

1.6V 

12.5 

11 

Low-Voltage 

2.2V 

21 

10 

1.8 

" 

3.0V 

35 

13 


Table VI — Life Data for Typical Batteries 


Eveready 
Type # 

Mallory 

Type# 

Size 

Type 

Life 

(Days) 

915 

M15F 

AA 

Carbon- 

Zinc 

150 

E91 

MN1500 

AA 

Alkaline 

200 

935 

M14F 

C 

Carbon- 

Zinc 

385 

E93 

MN1400 

c 

Alkaline 

575 

950 

M13F 

D 

Carbon- 

Zinc 

800 

E95 

MN1300 

D 

Alkaline 

1100 


All life data assumes a continuous drain of 250 juA and an 
end-of-life voltage of 1.1V. 


from the use of COS/MOS in automobile clocks, or in any 
automotive application, are those of wide operating voltage 
and temperature range and high noise immunity. 

With little restriction on power, the choice of a crystal 
depends mainly on cost. Crystals typically used for auto- 
mobile timing applications are AT-cut types that operate at 
frequencies between 1 MHz and 4.2 MHz. The oscillator 
considerations discussed earlier also apply to these frequen- 
cies; however, as the frequency increases, it becomes 
increasingly difficult to maintain a low starting voltage at a 
low current. At high frequencies, the starting voltage and 
current are inversely proportional and are controlled mainly 
by the values of the capacitors on the pi-type feedback 
network and the size of the COS/MOS amplifier transistors. 
For minimum starting voltage, relatively small capacitors 
should be used in the pi-feedback network, and no source 
resistors should be added to the amplifier. As indicated by 
data taken on the circuit shown in Fig. 9(b) and shown in 
Table VII, low power can still be maintained even when the 
source resistors are not used. 

The upper limit of the crystal frequency depends not so 
much on power consumption as on the minimum supply 
voltage allowed for circuit operation. The minimum auto- 
mobile battery voltage is generally considered to be 5 volts; 
however, the supply voltage for the timing circuit can be 
considerably less than this value depending upon the design 
of the transient protection circuit, as discussed later. Table 
VIII lists minimum COS/MOS supply voltages for typical 
oscillator circuits. The values shown permit design at two 
temperatures. The lower temperature is often considered 
adequate by auto companies with the opinion that the 
minimum battery voltage of 5 volts rarely, if ever, occurs at 
high temperatures. 

The oscillator in a typical auto clock circuit is followed 
by a number of frequency-dividing stages, the last stage of 
which is frequently used to drive a motor. Long counter 
chains are required because of the high oscillator frequency; 
however, the power dissipation of COS/MOS circuits is so 
low that the number of stages is only restricted by chip size 


468 






ICAN-6086 


Table VII — Typical High-Frequency Data for 
COS/MOS Oscillator and Counter 
Circuits (Low-Voltage Product) 


VdD 

(Volts) 

Freq. 

(MHz) 

Oscillator 

Current 

(mA) 

Counter 

Current 

(mA) 

Motor 

Current 

(mA) 

5 

1 

0.28 

0.125 

5V 

12 

1 

1.3 

0.275 

2-5 mA 

5 

2 

0.37 

0.250 

12V 

12 

2 

1.5 | 

0.550 

5-10 mA 

5 

3 

0.40 

0.375 

5V 

12 

3 

1.9 

0.825 

3-8 mA 

5 

4 

0.43 

0.500 

12V 

12 

4 

2.3 

1.1 

8-20 mA 


limitations. Because COS/MOS circuits consume current only 
during switching transitions, each counter stage averages 
one-half the current of the previous stage. The first counter 
stage, therefore, consumes as much current as all of the 
following stages combined for a counter of infinite length. 
Little difference, then, exists between the power consump- 
tion of a ten-stage or thirty-stage COS/MOS counter. Table 
VII lists, in addition to the oscillator current, typical values 
of counter current, as well as some typical ranges of peak and 
average motor currents. 

Current data, such as that shown in Table VII, are 
necessary for a proper design of the transient protection 
circuit, an essential part of any automobile digital logic 
system. Automobile manufacturers disagree on the maximum 
amplitude and decay of transient voltage; however, values 
often used are maximum transients of +120 volts and —90 
volts, each decaying exponentially with a maximum time 
constant of 45 milliseconds. Because standard COS/MOS 
circuits are rated for a maximum supply of 15 volts, a 
protection circuit must be included between the battery and 
the COS/MOS logic. 

Fig. 17 shows a transient-voltage protection circuit that is 
frequently used. The zener diode regulates the voltage supply 


Table VIII — Minimum Operating Voltages for 
COS/MOS Integrated Circuits 



Low-Voltage Product 

Silicon-Gate Product 

Freq. 

(MHz) 

1 

2 

3 

4 

1 

2 

3 

4 

Min. 
Voltage 
at 25°C 

2.9 

3.1 

3.5 

4.0 

1.6 

2.0 

2.6 

3.0 

Min. 
Voltage 
at 82°C 
180°F 

3.0 

3.3 

4.0 

j 

5.0 

1.8 

2.6 

3.4 

4.0 


BATTERY R 

0“ — wv 


-H 


TIMING 

CIRCUIT 

SUPPLY 


^LlO fjLF TO 
100 /iF TYR 


92CS- 20512 


Fig. 17— Automobile transient-protection circuit. 

for the clock circuits, and the capacitor and series diode 
prevent timing losses during negative transients. For mini- 
mum zener current during transients, the maximum value of 
R should be based on the minimum circuit operating voltage 
and the peak current drawn by the logic circuit and motor at 
the minimum battery voltage. The minimum zener break- 
down voltage is then determined by subtraction of the 
product of the minimum current drain at the normal battery 
voltage and the value of R just chosen from the battery 
voltage. A zener breakdown greater than this voltage assures 
that no unnecessary current will be drawn by the zener 
during normal automobile operation. 

Another important zener characteristic is dynamic 
impedance. During a current surge, the voltage across the 
zener must not rise to a damaging level. A value of 22 volts 
for the 45-millisecond time constant appears safe for 
standard COS/MOS circuits. 

In the design of a typical transient-voltage protection 
circuit, it is assumed that the minimum battery voltage is 5 
volts, that the minimum circuit operating voltage is 3.5 volts 
at a crystal frequency of 3.145728 MHz, and that a peak 
current of 3 milliamperes is obtained at 5 volts. The value of 
the resistance R is then found as (5 — 3.5 + 0.7)/3^250 
ohms. With a minimum current of 5 milliamperes at 1 2 volts, 
the minimum zener voltage becomes 12 — 5(0.250) = 11.75 
volts. For a + 120-volt transient, the zener could then 
consume a peak current of (120 — 11.8)/250 = 0.4 ampere. 
For a maximum zener voltage of 13 volts, the dynamic 
impedance of the zener must be less than (22V — 13V)/.4A = 
22 ohms. Components chosen in this manner will provide 
adequate protection for anticipated transients. 

Both protection-circuit diodes can be integrated onto the 
COS/MOS chip. When located as shown in Fig. 17, the series 
diode need only have a breakdown rating of about 12 volts. 
Zener diodes that have breakdown ratings of 4.5 to 6.0 volts 
or any multiple thereof can also be integrated onto the 
COS/MOS chip. The breakdown rating can also be increased 
in 0.7-volt steps by addition of forward-biased diodes in 
series. Characteristics of two typical zener diodes integrated 
in series are shown in Fig. 18. Fig. 18(a) shows the area 
around the “knee” of the breakdown region, and Fig. 18(b) 
shows the higher-current region useful for determining the 
dynamic resistance. From the slope of the line, the typical 
dynamic resistance for two diodes is found to be 17.6 ohms 
total, or 8.8 ohms per diode. The diodes are rated to 
withstand a 0.5-ampere surge current that decays with an 
80-millisecond time constant. The zener diode, then, is 
compatible with present automobile protection requirements. 


469 





ICAN-6086 




incubator timers, and other similar systems can be designed 
from information provided on the oscillator and counter 
with only the output device unique to the particular 
application. Automobile applications for COS/MOS circuits 
are almost endless. One can think of speed controllers, digital 
speedometers, miles per gallon indicators, and perhaps even 
estimated-time-of-arrival indicators that, on the basis Of the 
given total mileage, would update the time on a dynamic 
basis from information provided by the speedometer, 
odometer, and clock. 


CONCLUSIONS 

The primary advantage of electronic timing circuits over 
conventional mechanical methods of timekeeping lies in the 
greatly increased accuracy permitted by the highly stable 
crystal-controlled oscillator circuit. Although crystal oscil- 
lator circuits have existed for some time, their usefulness in 
portable applications has been somewhat limited because of 
the high current consumption required by the following 
digital logic. The advent of COS/MOS integrated circuits now 
permits the design of complete low-power timing systems. 
The impact of COS/MOS on timing applications is perhaps 
equalled by the recent development of liquid-crystal displays 
and dc-to-dc converters that allow low-power continuously 
operating digital displays. Certainly, no great technological 
barriers now exist for the use of electronic timing circuits in 
a wide variety of applications. The search, no doubt, will 
always continue for the ideal timekeeping device; however, it 
should be apparent from the information presented that the 
ideal timekeeping unit can now be more closely approached 
than ever before. 


Fig. 18— Oscillograph tracings showing characteristics of an 
integrated zener diode: (a) low-current region; (b) 
high-current region. 

and integration of this component should represent a 
considerable cost saving, especially when integrated with the 
series diode. 

Other Applications 

Although wristwatches and clocks of various types are 
important applications of COS/MOS timing circuits, they are 
certainly not the only timing applications which can benefit 
from the unique features of COS/MOS logic. Applications 
such as fuze timers, feeding systems, automatic sprinklers, 


REFERENCES 

1. Eaton, S.S., “Micropower Crystal-Controlled Oscillator 
Design Using RCA COS/MOS Inverters,” RCA Applica- 
tion Note ICAN 6539, 1971. 

2. “Frequency Control Devices,” Catalog No. 670, North- 
ern Enginnering Laboratories, Burlington, Wisconsin. 

3. Yoda, H., “Low Power Crystal Oscillator for Electronic 
Wrist Watch,” Mihon Dempa Kogyo Co., Ltd., Japan, 
1971. 

4. Schindler, H.C., “Liquid Crystal Dynamic Scattering for 
Display Devices,” RCA Publication PE-533, 1972. 

5. Eveready Battery Applications Engineering Data, Union 
Carbide Corp., 1971. 


470 




Solid State 
Division 


Digital Integrated Circuits 

Application Note 
SCAN -6101 


TBue C©S/@$©S Phase" Locked »L©©p 

A Versatile Building Block for Micro" Power 
Digital and Analog Applications 

by David K. Morgan 


INTRODUCTION 

Phase-locked-loops (PLL’s), especially in monolithic 
Drm, are finding significantly increased usage in signal- 
rocessing and digital systems. FM demodulation, FSK 
emodulation, tone decoding, frequency multiplication, 
ignal conditioning, clock synchronization, and frequency 
ynthesis are some of the many applications of a PLL. The 
'LL described in this Note is the COS/MOS CD4046A, 
/hich consumes only 600 microwatts of power at 10 kHz, a 
eduction in power consumption of 160 times when 
ompared to the 100 milliwatts required by similar mono- 
ithic bipolar PLL’s. This power reduction has particular 
ignificance for portable battery-operated equipment. This 
4ote discusses the basic fundamentals of phase-locked-loops, 
ind presents a detailed technical description of the COS/ 
40S PLL as well as some of its applications. 

REVIEW OF PLL FUNDAMENTALS 

The basic phase-locked-loop system is shown in Fig. 1 ; it 
consists of three parts: phase comparator, low-pass filter, and 
voltage-controlled oscillator (VCO); all are connected to 
form a closed-loop frequency-feedback system. 

With no signal input applied to the PLL system, the error 
voltage at the output of the phase comparator is zero. The 
voltage, Vd(t), from the low-pass filter is also zero, which 
causes the VCO to operate at a set frequency, fo, called the 
center frequency. When an input signal is applied to the PLL, 
the phase comparator compares the phase and frequency of 
the signal input with the VCO frequency and generates an 
error voltage proportional to the phase and frequency 



Fig. 1— Block diagram of PLL. 


difference of the input signal and the VCO. The error 
voltage, Ve(t), is filtered and applied to the control input of 
the VCO; Vd(t) varies in a direction that reduces the 
frequency difference between the VCO and signal-input 
frequency. When the input frequency is sufficiently close to 
the VCO frequency, the closed-loop nature of the PLL forces 
the VCO to lock in frequency with the signal input; i.e., 
when the PLL is in lock, the VCO frequency is identical to 
the signal input except for a finite phase difference. The 
range of frequencies over which the PLL can maintain this 
locked condition is defined as the lock range of the system. 
The lock range is always larger than the band of frequencies 
over which the PLL can acquire a locked condition with the 
signal input. This latter band of frequencies is defined as the 
capture range of the PLL system. 

TECHNICAL DESCRIPTION OF COS/MOS PLL 

Fig. 2 shows a block diagram of the COS/MOS 
CD4046A, which has been implemented on a single 



11-73 


471 







ICAN-6101 


monolithic integrated circuit. The PLL structure consists of a 
low-power, linear, voltage-controlled oscillator (VCO), and 
two different phase comparators having a common signal- 
input amplifier and a common comparator input. A 5.2-volt 
zener is provided for supply regulation if necessary. The VCO 
can be connected either directly or through frequency 
dividers to the comparator input of the phase comparators. 
The low-pass filter is implemented through external parts 
because of the radical configuration changes from application 
to application and because some of the components are 
non-integrable. The CD4046A is supplied in a 16-lead, 
dual-in-line, ceramic package (CD4046AD); a 16-lead, dual- 
in-line, plastic package (CD4046AE); or a 16-lead flat-pack 
(CD4046AK). It is also available in chip form (CD4046AH). 

Phase Comparators 

Most PLL systems utilize a balanced mixer composed of 
well-controlled analog amplifiers for the phase-comparator 
section. Analog amplifiers with well-controlled gain charac- 
teristics cannot easily be realized using COS/MOS tech- 
nology. Hence, the COS/MOS design shown in Fig. 3 
employs digital-type phase comparators. Both phase com- 
parators are driven by a common-input amplifier configura- 
tion composed of a bias stage and four inverting-amplifier 
stages. The phase-comparator signal input (terminal 14) can 
be direct-coupled provided the signal swing is within 
COS/MOS logic levels [logic 0<30% (VDD-VSS), logic 
1>70% (VDD-VSS)]. For smaller input signal swings, 
the signal must be capacitively coupled to the self-biasing 
amplifier at the signal input to insure an over-driven digital 
signal into the phase comparators. 

Phase-comparator I is an exclusive-OR network; it 
operates analagously to an over-driven balanced mixer. To 
maximize the lock range, the signal and comparator input fre- 
quencies must have 50-percent duty cycle. With no signal 
or noise on the signal input, this phase comparator has 



COMPARATOR PHASE COMPARATOR I 


INPUT 

Fig. 3— Schematic of COS/MOS PLL phase-comparator 
section. 


an average output voltage equal to VDD/2. The low-pass 
filter connected to the output of phase-comparator I supplies 
the averaged voltage to the VCO input, and causes the VCO 
to oscillate at the center frequency (f 0 ). With phase-com- 
parator I, the range of frequencies over which the PLL can 
acquire lock (capture range) is dependent on the low-pass-filter 
characteristics, and can be made as large as the lock range. 
Phase-comparator I enables a PLL system to remain in lock in 
spite of high amounts of noise in the input signal. 

One characteristic of this type of phase comparator is 
that it may lock onto input frequencies that are close to 
harmonics of the VCO center-frequency. A second charac- 
teristic is that the phase angle between the signal and the 
comparator input varies between 0° and 180°, and is 90° at 
the center frequency. Fig. 4 shows the typical, triangular, 
phase-to-output, response characteristic of phase-comparator 
I. Typical waveforms for a COS/MOS phase-locked-loop 
employing phase-comparator I in locked condition of f 0 is 
shown in Fig. 5. 

Phase-comparator II is an edge-controlled digital memory 
network. It consists of four flip-flop stages, control gating, 
and a three-state output circuit comprising p and n drivers 
having a common output node as snown in Fig. 3. When the 
p-MOS or n-MOS drivers are ON, they pull the output up to 
Vdd or down to Vgg, respectively. This type of phase 
comparator acts only on the positive edges of the signal- 
and comparator-input signals. The duty cycles of the signal 
and comparator inputs are not important since positive 
transitions control the PLL system utilizing this type of 
comparator. If the signal-input frequency is higher than the 
comparator-input frequency, the p-MOS output driver is 
maintained ON continuously. If the signal-input frequency is 
lower than the comparator-input frequency, the n-MOS 
output driver is maintained ON continuously. If the signal- 
and comparator-input frequencies are the same, but the 
signal input lags the comparator input in phase, the n-MOS 
output driver is maintained ON for a time corresponding to the 
phase difference. If the signal- and comparator-input fre- 
quencies are the same, but the signal input leads the com- 
parator input in phase, the p-MOS output driver is maintained 
ON for time corresponding to the phase difference. Sub- 
sequently, the capacitor voltage of the low-pass filter con- 
nected to this type of phase comparator is adjusted until the 
signal and comparator input are equal in both phase and fre- 
quency. At this stable operating point, both p- and n-MOS 
output drivers remain OFF, and thus the phase-comparator 



Fig. 4— Phase-comparator / characteristics at 
low-pass filter output. 


472 







ICAN-6101 


SIGNAL INPUT (TERM. 14) 


VCO OUTPUT (TERM 4)* 
COMPARATOR INPUT 
(TERM 3) 


jinnr 


VCO INPUT (TERM. 9) = 
* LOW- PASS FILTER 
OUTPUT 


— V SS 


92CS-200I0RI 


Fig. 5— Typical waveforms for COS/MOS phase- 

locked loop employing phase-comparator l 
in locked condition of f Q . 

output becomes an open circuit and holds the voltage on the 
capacitor of the low-pass filter constant. Moreover, the signal 
at the “phase pulses” output is at a high level, and can be used 
for indicating a locked condition. Thus, for phase-comparator 
II, no phase difference exists between signal and comparator 
input over the full VCO frequency range. Moreover, the power 
dissipation due to the low-pass filter is reduced when this 
type of phase comparator is used because both the p- and n- 
MOS output drivers are OFF for most of the signal-input 
cycle. It should be noted that the PLL lock range for this 
type of phase comparator is equal to the capture range, 
independent of the low-pass filter. With no signal present at 
the signal input, the VCO is adjusted to its lowest frequency 
for phase-comparator II. Fig. 6 shows typical waveforms for 
a COS/MOS PLL employing phase-comparator II in a locked 
condition. 

Fig. 7 shows the state diagram for phase-comparator II; 
each circle represents a state of the comparator. The number 
at the top inside each circle represents the state of the 
comparator, while the logic state of the signal and 
comparator inputs, represented by a 0 or a 1, are given by 
the left and right numbers, respectively, at the bottom of 
each circle. The transitions from one state to another result 
from either a logic change on the signal input (I) or the 
comparator input (C). A positive transition and a negative 
transition are shown by an arrow pointing up or down, 
respectively. The state diagram assumes that only one 
transition on either the signal input or the comparator input 
occurs at any instant. States 3, 5, 9, and 1 1 represent the 
condition at the output of phase-comparator II when the 
p-MOS driver is ON, while states 2, 4, 10, and 12 determine 
the condition when the n-MOS driver is ON. States 1, 6, 7, 
and 8 represent the condition when the output of phase- 
comparator II is in its high impedance state; i.e., both p- and 
n-devices are OFF, and the phase-pulses output (terminal 1) 
is high. The condition at the phase-pulses output for all other 
states is low. 

As an example of how one may use the state diagram 
shown in Fig. 7, consider the operation of phase-comparator 
II in the locked condition shown in Fig. 6. The waveforms 
shown in Fig. 6 are broken up into three sections: section I 
corresponds to the condition in which the signal input leads 
the comparator input in phase, while section II corresponds 
to a finite phase difference. Section III depicts the condition 
when the comparator input leads the signal input in phase. 
These three sections all correspond to a locked condition for 
the COS/MOS PLL; i.e., both signal- and comparator-input 


SIGNAL INPUT (TERM. 14) 

VCO OUTPUT (TERM 4)* 
COMPARATOR INPUT 
(TERM 3) 

PHASE COMPARATOR II 
OUTPUT (TERM. 13) 


VCO INPUT (TERM. 9)* 
•LOW-PASS FILTER 
OUTPUT 

PHASE PULSE (TERM. I 



NOTE: DASHED LINE IS AN OPEN-CIRCUIT CONDITION 92CS-200IIRI 

Fig. 6 — Typical waveforms for COS/MOS phase-locked loop 
employing phase-comparator II in locked condition. 


signals are of the same frequency but differ slightly in phase. 
Assume that both the signal inputs begin in the 0 state, and 
that phase-comparator II is initially in its high-impedance 
output condition (state 1), as shown in Figs. 7 and 6, 
respectively. The signal input makes a positive transition 



PHASE-PULSES OUTPUT (PINI) HIGH IN STATES 1,6,7, 0 AND LOW 
IN STATES 2,3,4, 5,9,10,11,12 


LOGIC STATE' 

OF SIGNAL INPUT 
(PIN 14) 


(S' 


STATE NUMBER 


lt*0-l TRANSITION 
ON SIGNAL INPUT 
Ct*0-l TRANSITION 
ON COMPARATOR 
INPUT 


Fig. 7— State diagram of phase-comparator //. 


first, which brings phase-comparator II to state 3. State 3 
corresponds to the condition of the comparator in which the 
signal input is a 1, the comparator input is a 0, and the 
output p-device is ON. The comparator input goes high next, 
while the signal input is high, thus bringing the comparator 
to state 6, a high-impedance output condition. The signal 
input goes to zero next, while the comparator input is high, 
which corresponds to state 7. The comparator input goes low 
next, bringing phase-comparator II back to state 1. As shown 
for section I, the p-device stays on for a time corresponding to 
the phase difference between the signal input and the 
comparator input. Starting m state 1 at the beginning of 
section III, the comparator input goes high first, while the 
signal input is low, bringing the comparator to state 2. 
Following the example given for section I, the comparator 
proceeds from state 2 to states 6 and 8 and then back to 1. 
The output of phase-comparator II for section III corres- 
ponds to the n-device being on for a time corresponding to the 
phase difference between the signal and comparator inputs. 

The state diagram of phase-comparator II completely 
describes all modes of operation of the comparator for any 
input condition in a phase-locked-loop. 


473 



ICAN-6101 


Voltage-Controlled Oscillator 

Fig. 8 shows the schematic diagram of the voltage- 
controlled oscillator (VCO). To assure low system-power 
dissipation, it is desirable that the low-pass filter consume 
little power. For example, in an RC filter, this requirement 
dictates that a high-value R and a low-value C be utilized. 
The VCO input must not, however, load down or modify the 
characteristics of the low-pass filter. Since the VCO design 
shown utilizes an n-MOS input configuration having prac- 
tically infinite input resistance, a great degree of freedom is 
allowed in selection of the low-pass filter components. 

The VCO circuit shown in Fig. 8 operates as follows: 
when the inhibit input is low, P 3 is turned full ON, 
effectively connecting the sources of Pj and P 2 to Vdd; and 
gates 1 and 2 are permitted to function as NOR-gate 
flip-flops. N 1 together with external-resistor R1 form a 
source-follower configuration. As long as the resistance of R 1 
is at least an order of magnitude greater than ON resistance 
of Ni (greater than 10 kilohms), the current through R1 is 
linearly dependent on the VCO input voltage. This current 
flows through Pj, which, together with P2, forms a 
current-mirror network. External resistor R2 adds an 
additional constant current through PI; this current offsets 
the VCO operating frequency for VCO input signals of 0 
volts. In the current-mirror network, the current of P2 is 
effectively equal to the current through PI independent of 
the drain voltage at P2. (This condition is true provided P2 is 
maintained in saturation; in the circuit shown, P 2 is saturated 
under all possible operating conditions and modes). The 
set/reset flip-flop composed of gates 1 and 2 turns ON either 
P4 and N3, or P5 and N2. One side of the external capacitor 
Cl is, therefore, held at ground, while the other side is 
charged by the constant current supplied by P2. As soon as 
Cl charges to the point at which the transfer point of 
inverters 1 or 5 is reached, the flip-flop changes state. The 



charged side of the capacitor is now pulled to ground. The 
other side of the capacitor goes negative, and discharges 
rapidly through the drain diode of the OFF n-device. 
Subsequently, a new half-cycle starts. Since inverters 1 and 5 
have the same transfer points, the VCO has a 50-percent 
duty-cycle. Inverters 1 through 4 and 5 through 8 serve 
several purposes: ( 1 ) they shape the slow-input ramp from 
capacitor Cl to a fast waveform at the flip-flop input stage, 
( 2 ) they maintain low power dissipation through the use of 
high-impedance devices at inverters 1 and 5 (slow-input 
wave-forms), and (3) they provide four inverter delays before 
removal of the set/reset flip-flop triggering pulse to assure 
proper toggling action. 

In order not to load the low-pass filter, a source-follower 
ouput of the VCO input voltage is provided (demodulated 
output). If this output is used, a load resistor (Rs) of 10 
kilohms or more should be connected from this terminal to 
ground. If unused, this terminal should be left open. A logic 
0 on the inhibit input enables the VCO and the source 
follower, while a logic 1 turns off both to minimize stand-by 
power consumption. 

Performance Summary of COS/MOS PLL 

The maximum ratings for the CD4046A COS/MOS PLL, 
as well as its general operating-performance characteristics 
are outlined in Table 1. The VCO and comparator 
characteristics are shown in Tables II and III, respectively. 
Table IV summarizes some useful formulas as a guide for 
approximating the values of external components for the 
CD4046A in a phase-locked-loop system. When using Table IV, 
one should keep in mind that frequency values are in 
kilohertz, resistance values are in kilohms, and capacitance 
values are in microfarads. The selected external components 
must be within the following r ange s: 

10Kf2<R l 5 R 2 ,R s <l Mf2 
q > 100 pF at V DD >5 V 
Cj >50pF at V DD > 10 V 

In addition to the given design information, refer to Fig. 9 
for Rj , R 2 , and C j component selections. The use of Table IV 
in designing a COS/MOS PLL system for some familiar appli- 
cations is discussed below. 

APPLICATIONS OF THE COS/MOS PLL 

The COS/MOS phase-locked-loop is a versatile building 
block suitable for a wide variety of applications, such as FM 
demodulators, frequency synthesizers, split-phase data 
synchronization and decoding, and phase-locked-loop lock 
detection. 

FM Demodulation 

When a phase-locked-loop is locked on an FM signal, the 
voltage-controlled oscillator (VCO) tracks the instantaneous 
frequency of that signal. The VCO input voltage, which is the 
filtered error voltage from the phase detector, corresponds to 
the demodulated output. Fig. 1 1 shows the connections for 
the COS/MOS CD4046A PLL as an FM demodulator. For 
this example, an FM signal consisting of a 10-kilohertz carrier 
frequency was modulated by a 400-Hz audio signal. The total 


474 



ICAN-6101 


Table 1— Maximum ratings and general operating character- 
istics 

MAXIMUM RATINGS, Absolute-Maximum Values: 


Storage Temperature Range — 65°C to +150 °C 

Operating Temperature Range: 

Ceramic Package Types -55°Cto+125 °C 

Plastic Package Types — 40°C to +85 °C 

DC Supply Voltage Range 

(V DD - V ss > -0.5 V to +15 V 

Device Dissipation (Per Pkg.) 200 mW 

All Inputs ^SS^^I^^DD 

Recommended 

DC Supply Voltage (V DD - V ss ). . 5 to 15 V 

Recommended 

Input Voltage Swing Vqq to ^SS 


General Characteristics (Typical Values at Vqq - V SS 
= 10 V and T A = 25°C) 

Operating Supply Voltage (Vqq - V 55 ) 5 to 15 V 

Operating Supply Current: 

Inhibit = "0" <0= 10kH,.V DD = 5V 70 M W 

@ Ci =0.0001 uF 

Ri . 1MR f 0 = 10kHz.V DD -10V...600 M W 
Inhibit = ”1 '* 25 /nA 


Table II— VCO electrical characteristics 

VCO Characteristics (Typical Values at Vqq - V 55 
= 10 V and T A = 25°C) 


Maximum Frequency 

Temperature Stability 

Linearity <V VC q jn = 5 V t 2.5 V) 
Center Frequency 

Frequency Range 

Input Resistance 

Output Voltage 

Duty Cycle 

Rise & Fall Times 

Output Current Capability 


1.2 MHz 
600 ppm/°C 
1% 

Programmable with 
R-j and C-j 
Programmable with 
R 1 , R 2 , and C-j 
10 12 n 

10 Vp 

50% 

50 ns 


"1 " Drive @ V Q = 9.5 V -1.8 mA 

”0" Sink @ V Q = 0.5 V 2.6 mA 

Demodulated Output: 

Offset Voltage 


(V VCO in “ V DEMOD out* @ 1 mA . 1 .5 V 


Table III — Comparator electrical characteristics 
Comparator Characteristics (Typical Values at Vqq - V 55 
= 10 V and T A = 25° C) 


Signal Input: 

Input Impedance 400 

Input Sensitivity 

ac coupled 400 mV 


dc coupled I "0“ < 30% (Vq d - V s$ l 

| "1" S 70% (V 0D - V ss ) 

Comparator Input Levels (term. 3). "0” < 30% (Vqq — V 55 ) 
"1" > 70% (Vqq - V ss ) 

Output Current Capability 

Comparator I (term. 2) and Comparator II (term. 13): 


”1" Drive @ Vq =9.5 V -1.8 mA 

”0'' Sink @ v 0 = 0.5 V 2.6 mA 


Comparator II Phase Pulses (term. 1 ): 


"I" Drive @ V 0 = 9.5 V -0.5 mA 

"0" Sink @ V 0 = 0.5 V 1.4 mA 


FM signal amplitude is 500 millivolts, therefore the signal 
must be ac coupled to the signal input (terminal 14). 
Phase-comparator I is used for this application because a PLL 
system with a center frequency equal to the FM carrier 
frequency is needed. Phase comparator I lends itself to this 
application also because of its high signal-input-noise- 
rejection characteristics. 

The formulas shown in Table IV for phase-comparator I 
with R 2 = 00 are used in the following considerations. The 
center frequency of the VCO is designed to be equal to the 
carrier frequency, 10 kHz. The value of capacitor Cj , 500 pF, 
was found by assuming an Rj = 100 K£2 for a supply voltage 
Vqd = 5 volts. 

These values determined the center frequency: 
f 0 = 10 kHz 

The PLL was set for a capture-range of 

f r ~±-J- -MI = ±0.4 kHz 
c 2 t r R 3 C 2 



Fig. 9(a)— Typical center frequency vs. Cj for 
Rf = 10 KQ., 100 KSl, and 1 MSI. 


475 



[ifft] 




VCO TIMING CAPACITOR (Cl) — /iF 


Fig. 9(b)— Typical frequency offset vs. Cj for 
R 2 = 10 KS1, 100 KSl, and 1 MSI. 


Fig. 9(c)- Typical f max /f min v 


USING PHASE COMPARATOR II 




v DD /z v 00 

VCO INPUT VOLTAGE 




For No Signal Input 
Frequency Lock Range,2fi_ 


Frequency Capture 
Range, 21q 


VCO in PLL system will adjust to center frequency, f 0 I 


O-AMri O 

T1 -R3C2 


VCO in PLL system will adjust 
to lowest operating frequency, f m { n 


2 f l = full VCO frequency range 
2 f L = ♦max _f min 


90° at center frequency (f 0 ), approximating 0° ai 
180° at ends of lock range (2f(_) 



- Given: f D 

- Given: f Q and 

- Given: f max 

- Given: f m j n St f m 


- Use f 0 with Fig ,9a to 

— Calculate f m ; n from 

- Calculate f 0 from 



determine R1 and Cl 

the equation 

the equation 

to determine R2andC1 



♦min = f o — ♦l 

f maX 

f mgx 



- Use f m in with Fig.9b 

♦o= 2 

- Calculate j—r~ 



to determine R2 andCI 

- Use f 0 with Fig,9a to 

. f 

VCO 


♦max 

— Calculate — ; — 

determine R1 and Cl 

— Use — with Fig.9c 

Component 


from the equation 


to determine 



♦max _ ^o + f L 


ratio R2/R1 to 
obtain R1 



♦min ♦o ~ f L 




- Use f WaX with 





Fig.5c to determine 





ratio R2/R1 to obtain 





R1 



For further information, see 





1) F. Gardner,"Phase-Lock Techniques”, John Wiley and Sons, New York, 1966 



!2) G. S. Moschytz, "Miniaturized RC Filters Using Phase-Locked Loop”, BSTJ, May, 1965. 









ICAN-6101 



V 0 D=+ 5V 
f 0 » 10 KHz 

total current drain 


Fig. 10— FM demodulator. 

to allow for the deviation of the carrier frequency due to the 
audio signal. The components shown in Fig. 10 for the 
low-pass filter (R 3 = 100 kf 2 ,C 2 = 0.1 M F) determine the 
above capture frequency. 

The total current drain at a supply voltage of 5 volts for 
this FM-demodulator application is 132 microamperes for a 4 
dB S/N-ratio on the signal input, and 90 microamperes for a 
lOdB S/N ratio. The power consumption decreases because 
the signal-input amplifier goes into saturation at higher input 
levels. 

Fig. 11 shows the performance of the FM/demodulator 
circuit of Fig. 10 at a 4 dB S/N-ratio. The demodulated 
output is taken off the VCO-input source follower using a 
resistor Rs (R s = 100 kS2).The demodulation gain for this 
circuit is 250 mV/kHz. 


Frequency Synthesizer 

The PLL system can function as a frequency-selective 
frequency multiplier by inserting a frequency divider into the 
feedback loop between the VCO output and the comparator 
input. Fig. 12 shows a COS/MOS low-frequency synthesizer 
with a programmable divider consisting of three decades. N, 
the frequency-divider modulus, can vary from 3 to 999 in 
steps of 1 . When the PLL system is in lock, the signal and 
comparator inputs are at the same frequency and 

f= NX 1 kHz 

Therefore, the frequency range of this synthesizer is 3 to 999 
kHz in 1-kHz increments, which is programmable by the 
switch position of the Divide-by-N counter. 


O.l V/cm 

0.5 V/cm 

10 V/cm 

O.l V/cm 


400 Hz AUDIO 
TRANSMITTED 

FM4- 

NOISE 


VCO OUTPUT 


DEMODULATED 

OUTPUT 


Phase-comparator II is used for this application because it 
will not lock on harmonics of the signal-input reference 
frequency (phase-comparator I does lock on harmonics). 
Since the duty cycle of the output of the Divide-by-N 
frequency divider is not 50 percent, phase-comparator II 
lends itself directly to this application. 

Using the formulas for phase-comparator II shown in 
Table IV, the VCO is set up to cover a range of 0 to 1.1 MHz. 
The low-pass filter for this application is a two-pole, lag-lead 
filter which enables faster locking for step changes in 
frequency. Fig. 13 shows the waveforms during switching 
between output frequencies of 3 and 903 kHz. The figure 
shows that the transient going towards 3 kHz on the VCO 
control voltage is overdamped, while the transient to 903 
kHz is underdamped. This condition could be improved by 
changing the value of R 3 in the low-pass filter by means of 
adjustment of the switch-position hundreds in the Divide- 
by-N counter. 

Split-Phase Data Synchronization and Decoding 

Fig. 14 shows another application of COS/MOS PLL, 
split-phase data synchronization and decoding. A split- 
phase data signal consists of a series of binary digits that 
occur at a periodic rate, as shown in waveform A in Fig. 14, 
The weight of each bit, 0 or 1 , is random, but the duration of 
each bit, and therefore the periodic bit-rate, is essentially 
constant. To detect and process the incoming signal, it is 
necessary to have a clock that is synchronous with the 
data-bit rate. This clock signal must be derived from the 
incoming data signal. Phase-lock techniques can be utilized to 
recover the clock and the data. Timing information is 
contained in the data transitions, which can be positive or 
negative in direction, but both polarities have the same 
meaning for timing recovery. The phase of the signal 
determines the binary bit weight. A binary 0 or 1 is a positive 
or negative transition, respectively, during a bit interval in 
split-phase data signals. 



Fig. 11— Voltage waveforms of FM demodulator. 


Fig. 12— Low-frequency synthesizer with three- 
decade programmable divider. 


477 







ICAN-6101 



Fig. 13— Frequency-synthesizer waveforms. 



® /yn^TLTlTL. 

<d o 1 o r 


Fig 14— Split-phase data synchronization and decoding. 


As shown in Fig. 14, the split-phase data-input (A) is First 
differentiated to mark the locations of the data transitions. 
The differentiated signal, (B), which is twice the bit rate, is 
gated into the COS/MOS PLL. Phase-comparator II in the 
PLL is used because of its insensitivity to duty cycle on both 
the signal and comparator inputs. The VCO output is fed 
into the clock input of FF1 which divides the VCO 
frequency by two. During the ON intervals, the PLL tracks 
the differentiated signal (B); during the OFF intervals the 
PLL remembers the last frequency present and still provides 
a clock output. The VCO output is inverted and fed into the 
clock input of FF2 whose data input is the inverted output 
of FF1. FF2 provides the necessary phase shift in signal (C) 
to obtain signal (D), the recovered clock signal from the 
split-phase data transmission. The output of FF3, (E), is the 
recovered binary information from the phase information 
contained in the split-phase data. Initial synchronization of 
this PLL system is accomplished by a string of alternating 0’s 
and Fs that precede the data transmission. 


a binary signal. For example, a 1 or a 0 output from a 
lock-detection circuit would correspond to a locked or 
unlocked condition, respectively. This signal could, in turn, 
activate circuitry utilizing a locked PLL signal. This detection 
could also be used in frequency-shift-keyed (FSK) data 
transmissions in which digital information is transmitted by 
switching the input frequency between either of two discrete 
input frequencies, one corresponding to a digital 1 and the 
other to a digital 0. 

Fig. 15 shows a lock-detection scheme for the COS/MOS 
PLL. The signal input is switched between two discrete 
frequencies of 20 kHz and 10 kHz. The PLL system uses 
phase-comparator II; the VCO bandwidth is set up for an 
fmin 9.5 kHz and an f max of 10.5 kHz. Therefore, the 
PLL locks and unlocks on the 10-kHz and 20-kHz signals, 
respectively. When the PLL is in lock, the output of 
phase-comparator I is low except for some very short pulses 
that result from the inherent phase difference between the 
signal and comparator inputs; the phase-pulses output 
(terminal 1) is high except for some very small pulses 
resulting from the same phase difference. This low condition 
of phase comparator I is detected by the lock-detection - 
circuit shown in Fig. 15. Fig. 16 shows the performance of 
this circuit when the input signal is switched between 20 and 
10 kHz. It can be seen that after about five input cycles the 
lock detection signal goes high. 



Fig. 15— Lock-detection circuit. 



Phase-Locked-Loop Lock Detection Fi 9- 16- Lock-detection-circuit waveforms. 

In some applications that utilize a PLL, it is sometimes 
necessary to have an output indication of when the PLL is in 
lock. One of the simplest forms of lock-condition indicator is 


478 





Solid State 
Division 


Digital Integrated Circuits 

Application Note 
ICAN-6166 


COS/MOS MSI Counter and 
Register Design 
and Applications 


by R. Heuner, J. Litus, Jr., A. Havasy 


COS/MOS (Complementary-Symmetry Metal-Oxide- 
Semiconductor) technology offers economical MSI 
(Medium-Scale Integration) arrays on a single monolithic 
silicon chip. Added performance benefits are- derived from 
micropower quiescent power dissipation; moderately fast 
operation; excellent dc and dynamic noise immunity; high dc 
fanout; stable performance over wide ranges of supply 
voltage, temperature, and device parameter variation; simple 
circuit and subsystem design; and compatible logic and 
memory circuitry from simple gates and flip-flops to 
complex MSI circuits. 

In the COS/MOS MSI area, RCA has several counter and 
register types presently available commercially. These devices 
are available in both plastic and ceramic packages intended 
for military, commercial and industrial uses. Devices with the 
suffix “E” are plastic package types; suffix “D” are ceramic 
package types. 

CD4006A — Eighteen-Stage Static Shift Register 
CD4014A - Eight-Stage Synchronous Parallel-Input/Serial- 
Output Static Shift Register 

CD4015A-Dual Four-Stage Serial-Input/Parallel-Output 
Static Shift Register 

CD4017A — Decade Counter/Divider Plus 10 Decoded 
Decimal Outputs 

CD4018A — Presettable Divide-by-“N” Counter 
CD4020A — Fourteen-Stage Ripple-Carry Binary Counter 
CD4021A — Eight Stage Asynchronous Parallel-Input/Serial- 
Output Static Shift Register 

CD4022A— Divide-by-8 Counter Plus 8 Decoded Outputs 
CD4024A - Seven-Stage Ripple-Carry Binary Counter 

This Note shows logic and schematic diagrams for each of 
the counter and register types listed above, outlines circuit 
designs, and discusses device-design tradeoffs. Performance 
criteria are summarized, and applications by type are 
outlined by logic or subsystems diagrams and waveform 
photographs. Possible extensions of design into other areas of 
application are given. 

The applications shown also utilize other RCA COS/MOS 
family types such as the CD4000A-CD4002A “NOR” gate 
types; CD4013A Dual-D Flip-Flop type; CD4007A Dual 


Complementary Pair Plus Inverter; CD4009A and CD4010A 
Hex-Buffer/Logic-Level Converter types; and the CD4011A 
and CD4012A Quad-2 and Dual-4 “NAND” gate types. 

General COS/MOS Design 

The COS/MOS counter and register types described 
consist of between 100 and 300 MOS devices, supporting 
interconnect tunnels and metal rims, and bond pads, all on a 
single monolithic pellet. 

Table I summarizes the major operating characteristics of 
the counter and register types. A complete description of the 
advantages and operating characteristics of the RCA COS/ 
MOS line is given in Refs. 1, 2, 3 and 4. The applications 
shown in this Note for each type are not intended to be 
all-inclusive, but rather to highlight sample uses. 

Fig. 1 illustrates the basic static master-slave flip-flop 



b) An open circuit 
when control input 1 
is "High” and 
control input 2 is "Low” 


Fig. 1 - Basic COS/MOS master-slave flip-flop stage. 


6-72 

479 







ICAN-6166 


circuit configuration utilized in all the designs described. The 
logic level present at the “D” (Data) input is transferred to 
the “Q” output during the positive-going transition of the 
clock pulse. DC “Reset” or “Set” is accomplished by a high 
level at the respective input. 


loosely specified input waveshape requirement. As shown in 
Table I, the basic flip-flop configuration operates from a 
non-critical single-phase clock input signal. Both “1” and “0” 
dock-pulse durations can go to infinity, and rise and fall 
times of 5 microseconds or less are permissible. 


Table 1 - Typical Features and Characteristics of COS/MOS Counters 
and Registers - All Types. 


FEATURES: 

Operating Temperature Range -55 to + 1 25°C (Ceramic) 

-40 to + 85 °C (Plastic) 

Operating Voltage Range 3.5 to 15V 

Full MOS Gate Oxide Protection at all Terminals 
Output Buffers Provided 
Full Static Operation 


TYPICAL CHARACTERISTICS (T A = 25°C) 


V DD =10V 


Clock Pulse Frequency 


5MHz 


Clock Rise & Fall Times 


< 5 ps 


V DD =5V 

2.5MHz 
< 5 /is 


Quiescent Power Dissipation/Package 


5 juW 


1.5 pW 


Noise Immunity — All Inputs 


45% of V DD 


Drive Capability 
Sink Capability 


Ip = 0.5 to 3mA @ 
Vj=7V 

Ip = 0.5 to 3mA @ 
V 0 = 3V 


Id = 0.1 to 1mA @ 
Vj=4V 

10 = 0.1 to 1mA @ 
V 0 =1V 


Both “Reset” and/or “Set” functions are easily omitted, 
as shown for some of the designs. Output lead isolation at 
the “Q” and/or <: Q” outputs is realized by use of inverters. 
These inverters eliminate all possibility of MOS gate oxide 
damage at the output leads, and also improve circuit speed, 
noise immunity, and drive capability. The sizes of the 
p-channel and n-channel MOS devices in the output inverters 
are tailored to meet the desired drive and sink current 
requirements. The internal clock shaping shown permits a 


CD4024A Seven-Stage Ripple-Carry Binary Counter 

Fig. 2 shows the logic diagram of the CD4024A, a 
7-stage ripple-carry binary counter. Fig. 3 illustrates in 
more detail the schematic and logic diagrams for one of the 
seven counter stages. Operation is similar to that of the basic 
master-slave flip-flop, with the following exceptions: the 
“D” line connection is derived from the Q output of that 
stage so that it complements the stage at the negative 
clock-pulse transition. The clocking of a stage is derived from 



TERMINAL No. 2 V DD 
TERMINAL No.12 6ND. 


Fig. 2 - Logic diagram of CD4024A binary counter. 


480 




ICAN-6166 


the previous counter stage (ripple-carry). The dc “Reset” 
function is realized by raising the ground return path of the 
Q outputs of all seven stages (both master and slave sections). 
This mode of resetting saves four devices and associated 
interconnections per counter stage. 


Fig. 4 illustrates the use of the CD4024A as a binary 
frequency-divider. Multiple CD4024A units can be stacked 
for added frequency division. The clock input of a 
subsequent CD4024A is derived directly from the last output 
stage of the previous CD4024A. 


V DD 



NOTE : SUBSTRATES FOR ALL V UNITS 
ARE CONNECTED TO Vqd SUB- 
STRATES FOR ALL "N" UNITS, 
UNLESS OTHERWISE SHOWN, ARE 
CONNECTED TO GROUND. 

RESET INPUT HAS SAME PRO- 
TECTION CIRCUITRY AS THAT 
SHOWN FOR THE * INPUT. 


EQUATIONS FOR STAGES 2 TO 7 
Q20UT - (02^1^®)^ 

°30UT s (Q 3 KOl)(Q2>(®)(R> 

Q 40 UT = (0 4 HQ 1 ) (02>t03>t«>> <« > 

°50UT 1 <Q5)(Ql )(Q2)(Q3> (0 4 )(O )(R) 

QfcOUT ■ <Q6)(Ql)(Q2)(Q3)(Q4«QsK®«R) 
070UT 1 (Q7)(0lKQ2)(03)(04)(Q5)(°6)(®W) 



Fig. 3 - Schematic and logic diagrams for one of the seven 
counter stages in the CD4024A. 



Fig. 4 - CD4024A "Binary frequency-divider" application. 


481 






I CAN-61 66 


Fig. 5 shows how the CD4024A is used to derive a 
desired pulse-output delay time. Varied delay times can be 
realized by detecting different CD4024A outputs. A finer 
control of delay time is possible if more than one CD4024A 
output is detected. Extremely long and accurate delay times 
can be realized by use of an accurate oscillator* and multiple 
CD4024A units. 

Fig. 6 illustrates the use of the CD4024A to derive 
various divide-by-N counter configurations. Fig. 6a & 6b 
illustrate 2 reliable reset methods for counting to the number 
N, (N=60). Reset mode 1 is shown in Fig. 6a. The type 
D-Flip-Flop is set at the coincidence of count 59 and the 
positive clock transition. At the next negative clock 
transition, a reset pulse is generated, whose duration is 


one-half the clock cycle time. This resets the CD4024A to 
zero. Note that only count 59 needs to be detected for the 
reset operation, and no N+l count occurs. 

Reset mode 2 is shown in Fig. 6b. The N+l count (60) is 
detected, sets the R-S Flip-Flop, which in turn resets the 
CD4024A to the zero state. The reset pulse width is one-half 
the clock cycle time, and is removed by gating count zero 
with the positive clock transition to reset the R-S Flip-Flop. 

Fig. 6c illustrates a divide-by-60, divide-by-60 and 
divide-by-24 timer system using the reset scheme (mode 1) of 
Fig. 6a. Similar use of one CD4024A unit permits any 
divide-by-N from 2 to 128. In applications where decimal 
display outputs are required, the RCA type CD4017A can be 
used to advantage, as described later in this Note. 





Fig. 5- CD4024A "Pulse-delay-control" application. 


«IN> 



I-CD400IA 
I-CD40I2A 
I-CD40I3A 
I - CD4024A 

Fig. 6a - Counter of 60 using reset mode 1. 




Fig. 6 - CD4024A used to derive various divide-by-N counter 
* See Ref. 5 configurations. 


482 











ICAN-6166 


Fig. 7a shows how the CD4024A is used with a weighted 
resistor network to realize analog to digital conversion (A to 
D). The CD4010A (Hex-Buffer, Non-Inverting) is used to 
reduce the more significant counter output “1” level 
impedances (which have poor tolerances) to well below the 
precision resistor network values. 

Varied ranges of analog signals can be handled by control 
of the resistor network and comparator. 

As the CD4024A counter advances, the voltage input to 
the comparator rises until it equals the analog input. The 
comparator then switches and inhibits further counter 
advancement, thus holding the digital representation of the 
analog signal in the counter. Because the CD4024A can 


count to 2^, or 128, division of an analog voltage range into 
100 parts is easily realized. (The example shows a 1-volt 
range broken into 10-millivolt steps.) 

Fig. 7b shows the CD4024A used with an R-2R ladder 
network for A to D conversion. The R-2R network, while 
requiring added resistors, utilizes only 2 resistor values, 
permits ready expansion to greater than 7 stages, and 
provides better resistor temperature tracking and allows 
elimination of the CD4010A’s. The photographs, for the 
R-2R network, show a stepping input from zero to 12.8 
volts, divided into 100-millivolt steps. The CD4010A Buffers 
may be used to permit lower R-2R values, if desired. 






INTENSIFIED ZONE OF PHOTO <o) 


Fig. 7b - Analog-to-digital conversion-resistor ladder network. 


Fig. 7 - CD4024A "Analog : to-digital conversion" application. 


484 








I CAN-61 66 


Fig. 8 shows the Logic Diagram of the CD4020A, a 
14-Stage Binary Counter. Applications are similar to the 
CD4024A. 


RESET i 



reset signal clears t$ie decade counter to its zero count. Use 
of the “Johnson” ; decade counter configuration permits 
high-speed operation, two-input decimal decode gating, and 
spike-free decoded output. Anti-lock gating is provided to 
permit only the proper counting sequence. The ten decimal 
outputs are normally low and go high only at their respective, 
decoded decimal time slot. Each decimal output remains high 
for one full clock cycle. The carry-out signal completes one 
cycle for every ten clock input cycles, and is used to clock 
the following decade directly in any multi- decade applica- 
tion. 

Fig. 10 shows the use of the CD4017A in a “Multi- 
Decade Counter/Decimal Display” application. Two typical 
lamp-driver interface circuits are shown. When one-sixth of a 
CD4009A is used as the lamp driver, current ranges up to 
20-milliamperes and 7.5-milliamperes can be realized for 
COS/MOS supply voltages of 10 volts and 5.0 volts, 
respectively. 


Fig. 8 - Logic diagram of CD4020A 14-stage binary counter. 


RCA CD4017A Decade Counter/Divider 
Plus 10 Decoded Decimal Outputs 

Fig. 9 shows the logic diagram of the CD4017A a decade 
counter plus 10 decoded decimal outputs. A five-stage 
“Johnson Counter” configuration is used to implement the 
decade counter. The basic flip-flop stages are similar to that 
described in Fig. 1. “Clock”, “Reset”, “Inhibit”, and “Carry 
Out” signals are provided. The decade counter advances one 
count at the positive clock-signal transition provided the 
inhibit signal is low. Counter advancement by way of the 
clock line is inhibited when the inhibit signal is high. A high 



2 TYPICAL LAMP DRIVER CIRCUITS 



TERMINAL No. I6«V DD 
TERMINAL No 8 * GND 


Fig. 9 - Logic diagram of CD40 17 A-decade counter. 



Fig. 10 - CD4017A " Multi-decade counter/decimal display" 
application. 

Fig. 11 illustrates the use of the CD4017A in a 
“Multi-Decade Frequency Division” application; decimal 
display is optional. Fig. 12 shows the use of the CD4017A to 
obtain various divide-by-N counter configurations. Figs. 12a 
& 12b illustrate two reset methods in counting to the 
number 60. Fig. 12c shows an example of divide-by-60, 
divide-by-60 and divide-by-24. The CD4017A permits easy 
decimal display of each divide-by-N section. The CD4017A 
can also be used in applications requiring multiplexing, de- 
multiplexing and commutation of signals. 


485 






I CAN -6 166 


RCA CD4022A Divide-by-8 Counter Plus 8 Decoded Outputs 

Fig. 13 shows the logic diagram of the CD4022A, a 
divide-by-8 counter and 8 decoded outputs. A four-stage 
“Johnson Counter” is used to implement the divide-by-8 
counter. The basic flip-flop stages are similar to that 
described in Fig. 1. “Clock”, “Clock-Enable”, “Reset” and 
“Carry-Out” signals are provided on the divide-by-8 counter. 

The divide-by-8 counter is advanced one count at the 
positive clock-signal transistion. A high reset signal returns 
the divide-by-8 counter to its zero count. Use of the 
“Johnson” divide-by-8 counter configuration permits high- 
speed operation, two-input decode gating, and spike-free 
decoded output. Anti-lock gating is provided to permit only 
the proper counting sequence. The eight decoded outputs are 
normally low and go high only at their respective decoded 
time slot. Each decoded output remains high for one full 
clock cycle. The carry-out signal completes one cycle for 
every eight clock input cycles, and is used to clock the 
following counter stage directly, in multi-stage applications. 

Fig. 14 shows the CD4022A used in a “Divide-by-8 
Counter/Decoder” application. One CD4022A unit provides 
the counting as well as the decoding function. 



TRACE 

f * FREQ. INPUT- (a) 
f/IO-(b) 
f/IOO*(c) 
f/IOOO » (d) 


Fig. 11 - CD4017A " Multi-decade frequency division" 

application. 




PACKAGE COUNT : 
I-CD400IA I-CD40I2A 
I-CD40I3A 2-CD40I7A 


Fig. 12a - Counter of 60-using reset mode 1. 




PACKAGE COUNT : 
I -CD400IA 

1 - CD 4012 A 

2- CD40I7A 



CD400IA 


CLOCK (a) 
SET (b) 
RESET (c) 
f 0 (d) 


CLOCK (o) 
SET (b) 
RESET (c) 

f 0 « d > 


Fig. 12b - Counter of 60-using reset mode 2. 




Fig. 12 - CD4017A "Divide-by-N counter" configurations. 


486 











ICAN-6166 


“DIVIDE BY N COUNTER WITH DECIMAL DISPLAY" 
( EXAMPLE SHOWN -r-60; -r-60; -r24) 


DISPLAY 60 





PACKAGE COUNT 
6-CD40I7A 
2-CD40IIA 
2-CD400IA 
2-CD40I3A 
2-CD4009A 


Fig. 12c - Divide-by-60, divide-by-60 and divide-by-24 configuration. 




CLOCK 

CLOCK ENABLE CD4022A 
RESET “o“ Y 


Ittl Cc)| (d)| (e)| (f)| 


>| (g)| < 


2 I 3 7 II 4 5 10 



Fig. 14 - CD4022A "Divide-by-8 counter/decoder" 
Fig. 13 - Logic diagram of the CD4022A-divide-by-8 counter, application. 


487 








ICAN-6166 


Fig. 1 5 shows a “Divide-by-64 Counter/Decoder” appli- 
cation. The partial decode function performed by the 
CD4022A significantly simplifies the external gating to 
complete the 1 -in-64 decode function. Other binary 
counter/decoder applications can also be realized. 


CLOCK INPUT (a) 


1 

C 0 

CD4022A 

CL. 

CD4022A 

r -5 : 

-i-e 

r 

r-64 

r 

0 12 3 4 5 6 7 

£ 

0 12 3 4 5 6 7 


Fig. 15a - Block diagram. 



TRACE 

CLOCK IN * (a) 

"0"* (b) 

'7“- (C) 

"15". (d) 

"31"* (e) 

"63"* (f) 

Fig. 15c - Waveforms. 

Fig. 15-CD4022A "Divide-by-64 counter/decoder" 
application. 

RCA CD4018A Presettable Divide-by-N Counter 

Fig. 16 shows the logic diagram of the CD4018A, a 
presettable divide-by-N counter. The CD4018A consists of 
five flip-flops which can be configured as a 5-, 4-, 3-, or 
2-stage Johnson counter with buffered Q outputs from each 
stage, and counter preset control gating. “Clock”, “Reset”, 
“Data”, “Preset”, and 5 “Jam” inputs are provided. Q 
outputs are provided from each of the five counter stages. 
The basic flip-flop stages are similar to that shown in Fig. 1 . 

Divide-by-10, 8 , 6 , 4, or 2 counter configurations can be 
implemented by feeding the § 5 , § 4 , $ 3 , § 2 > or Qi, signals, 
respectively, back to the data input. Divide-by-9, 7, 5, or 3 
counter configurations can be implemented by use of the 
CD4011A gate package to gate the proper feedback 
connection to the data input. Divide-by-functions greater 
than 10 can be achieved by use of multiple CD4018A 
packages. The counter configuration is advanced one count 
at the positive clock-signal transition. A high reset signal 
clears the counter to an all-zero condition. A high preset 



signal allows information on the Jam inputs to preset the 
counter configuration. Anti-lock gating is provided to assure 
the proper counting sequence. 

Fig. 17 shows the CD4018A utilized in constructing 
fixed counters of divide-by-9, 7, 5 or 3. Operation in a 
divide-by-7 configuration is shown in detail in Fig. 18. 



Fig. 16- Logic diagram of the CD4018A-presettable divide- 
by-N counter. 


EXTERNAL CONNECTIONS FOR DIVIDE 
BY 10,9,8,7,6,5,4,3 OPERATION 


DIVIDE BY 10 
DIVIDE BY 8 
DIVIDE BY 6 
DIVIDE BY 4 


Qsl 

54 

5 3 

5 2 J 


CONNECTED 
BACK TO 
"DATA" 


NO EXTERNAL 
COMPONENTS 
REQUIRED 


DIVIDE BY 9 

1/2 CD40IIA 



CONNECTED BACK TO "DATA" 
(SKIPS "ALL-l's" STATE) 
OF CD40I8A 


DIVIDE BY 7 

1/2 CD40IIA 


FROM 

CD40I8A 



CONNECTED BACK TO "DATA" 
(SKIPS "ALL-l's" STATE) 
OF CD40I8A 


DIVIDE BY 5 

1/2 CD40IIA 


FROM 

CD40I8A 



CONNECTED BACK TO "DATA" 
(SKIPS "ALL-l's" STATE) 
OF CD40I8A 


DIVIDE BY 3 

1/2 CD40IIA 



CONNECTED BACK TO "DATA" 
(SKIPS "ALL-l's" STATE) 

OF CD40I8A 


Fig. 17 - External connections for divide-by-10, 9, 8, 7, 6, 5, 
4, 3 operation. 


488 







ICAN-6166 



Fig. 18 - CD4018A "Fixed divide-by-7" configuration. 




Fig. 19 - Three-decade , programmable, divide-by-N counter with frequency division from 2 to 999: (a) logic diagram; (b) 
counting sequence; (c) timing waveforms at various points in the circuit; (d) divide-by-N output for various values of N; 


489 









I CAN -6 166 



3. SINGLE WAFER (NON-STANDARD) PER 
DECADE •, TO ENABLE THE ELIMINATION 
OF RESISTORS, WHICH REDUCES COMPONENT 
COUNT AND POWER DISSIPATION. 

Fig. 19 (e) alternative decade switch configuration. 


Fig. 19 illustrates the use of the CD4018A in a 
programmable divide-by-N counter, where N is any number 
from 2 to 999 for the example shown. Extension to higher N 
ranges is realized by use of additional CD4018A units. The 
Johnson-counter configuration of the CD4018A permits 
simpler switch arrangements at the Jam inputs controlling 
the programmable preset state. The programmable divide- 
by-N configuration can be utilized in frequency-synthesis 
applications. 

The CD4018A can also be utilized as a five stage parallel 
input/output holding register. “Holding Register” parallel 
entry can be controlled by means of the “Preset Enable 
Line”, resulting in a five stage latch operation. 

CD4006A 18-Stage Static Shift Register 

Fig. 20 shows the logic diagram of the CD4006A, an 
1 8-stage static shift register. The register stages are similar to 
those shown in Fig. 1. The CD4006A consists of four 
separate shift-register sections, two four-stage sections and 
two five-stage sections with output taps at the fourth stage. 
Each register section has independent “Data” inputs to the 
first stage. The clock input is common to all 18 register 
stages. Through appropriate connection of inputs and 
outputs, multiple register sections of 4, 5, 8, and 9 stages or 
single register sections of 10, 12, 13, 14, 16, 17, and 18 
stages can be implemented using one CD4006A. Longer 
shift-register sections can be assembled by use of more than 
one CD4006A. 



TERMINAL No.l^Voo 
TERMINAL No. 7 =GN0. 

Fig. 20 - Logic diagram of die CD4006A - 18-stage static 
shift register. 


490 



















ICAN-6166 


Fig. 21 shows in more detail the schematic and logic 
diagrams for one of the 18 register stages. Register shifting 
occurs on the negative clock-pulse transition. 



note: all "p"-unit substrates 

ARE CONNECTED TO V D D 
ALL "N"-UNIT SUBSTRATES 
ARE CONNECTED TO V S S 



Fig. 21 - Schematic and logic diagrams for one of the 18 
register sections of the CD4006A. 


RCA CD4015A Dual 4-Stage Serial-1 nput/Parallel-Output 
Static Shift Register 

Fig. 22 shows the logic diagram of the CD4015A. The 
CD4015A consists of two identical, independent, four-stage 
serial-input/parallel-outpu.t registers. Each register has 
independent “Clock” and “Reset” inputs, as well as a serial 
“Data” input. “Q” outputs are available from each of the 
four stages on both registers. All register stages are similar to 
that shown in Fig. 1. The logic level present at the data input 
is transferred into the first register stage and shifted over one 
stage at each positive clock transition. Reset of a four-stage 
section is accomplished by a- high level on the reset line. 
Register expansion to 8 stages with one CD4015A or to more 
than 8 stages with multiple CD4015A packages, is possible. 


Fig. 23 shows the use of the CD4015A in an 8-stage 
serial-input/parallel-output register application. This circuit 
operates as follows: The CD4015A connected as an 8-stage 
register is reset and “l”s are shifted through the register. The 
scope trace shows the “1” pattern loading into the register 
until a “1” reaches the eighth stage and initiates reset. After 
two clock pulses, the reset is removed and “l”s again shift 
into the register. Low-speed-to-high-speed data queueing and 
serial/parallel data conversion are typical applications. 


°2A 



Fig. 22 -Logic diagram of the CD4015A — dual 4-stage 
serial-input/parallel-output register. 


RCA CD4014A 8-Stage Synchronous 
Parallel-Input/Serial-Output Static Shift Register 

Fig. 24 shows the logic diagram of the CD4014A, an 
8-stage synchronous parallel-input/serial-output register. A 
“Clock” input and a single serial “Data” input along with 
individual parallel “Jam” inputs to each register stage and a 
common “Parallel/Serial” control signal are provided. “Q” 
outputs from the 6th, 7th, and 8th stages are available. All 
register stages are similar to that shown in Fig. 1 , except that 
extra transmission gates permit parallel or serial entry. 
Parallel or serial entry is made into the register synchronous 
with the positive clock transition and under control of the 
parallel/serial input. When the parallel/serial input is low, 
data is serially shifted into the 8-stage register synchronous 
with the positive clock transition. When the parallel/serial 
input is high, data is jammed into the 8-stage register by way 
of the parallel input lines and synchronous with the positive 
clock transition. Register expansion with multiple CD4014A 
packages is possible. 


491 
















ICAN-6166 





Fig. 25 shows the use of the CD4014A in an 8-stage 
synchronous parallel-input/serial-output register application. 
In this configuration, the CD4013A allows a parallel transfer 
to be made into the CD4014A register once every 8 clock 
pulses. Use of the divide-by-2 outputs of the CD4013A as 
parallel inputs to alternate CD4014A stages permits change- 
over from a 10101010 to a 01010101 parallel input pattern 
every 8 pulses. The scope trace shows the parallel transfer of 
the 01010101 pattern into the register followed by eight 
shift pulses and subsequently another parallel transfer of 
10101010 and eight shift pulses. High-speed-to-low-speed 
data queueing and parallel/serial data conversion are typical 
applications. 



CLOCK 

Fig. 25 - CD4014A 8-stage synchronous parallel-input/serial- 
output register application. 


Fig. 23 - CD4015A 8-stage serial-input/parallel-output regis- 
ter application. 


The CD4014A can be utilized in pseudo-randon-code 
generation applications via combined control of the parallel 
input conditions and gating of the 6th, 7th, and 8th stage 
register feedback to the serial input. Fig. 26 shows the 
photomicrograph of the CD4014A pellet. 



Fig. 24 - Logic diagram of the CD4014A 8-stage synchronous 
parallel-input/serial-output register. 



Fig. 26 - Photomicrograph of the CD4014A pellet. 


492 








ICAN-6166 


RCA CD4021 A 8-Stage Asynchronous 
Parallel-1 nput/Serial-Output Static Shift Register 

Fig. 27 shows the logic diagram of theCD4021A 8-stage 
asynchronous parallel-input/serial-output register. Operation 
is basically the same as that of the CD4014A except that 
parallel transfers are made as soon as the parallel/serial 
control input goes high. Parallel transfers are thus made 
asynchronous with the clock input. Serial shifting is still 
performed synchronously with the clock input. The 
CD4014A thus permits the parallel transfer to be synchro- 
nized with a different clocking signal than that of the serial 
transfer. Thus, in high-speed-to-low-speed data queueing, for 
example, an externally gated high-speed clock may control 
the parallel transfer while the low-speed clock may control 
the serial shifting. 


PARALLEL 

INPUT-1 PI-2 PI-3 PI-4 



0-6 0-7 0-6 


Fig. 27 - Logic diagram of the CD4021A 8 -stage asynchro- 
nous parallei-input/seriai-output register. 


Fig. 28 shows the use of the CD4021A in an 8-stage 
asynchronous high-speed parallel-input/low-speed serial- 
output application. For the example shown, the high-speed 
portion of the system is simulated by simplified control 
logic. A 10kHz slow-speed clock and 1MHz high-speed clock 
are assumed. Signal lines “a” and “b”, as well as the eight 
data lines, are representative of the information transfer 
requirements, between the high-and-low-speed systems. At 
the slow-speed output sections, the CD4021A shifts out 
stored information at a 10kHz clock rate. The CD4022A 


counts to eight at the 10kHz rate and at count zero, sends a 
high “Flag” signal to the high-speed system over line “a”, 
indicating that the low-speed section is ready to accept eight 
bits on the data lines. 

In the simulated high-speed section, a high on line “a”, 
allows Flip-Flop “A” to set on the positive transition of the 
1MHz clock. The Q output of Flip-Flop “A” is gated with 
the 1MHz clock to form a gated 1MHz clock signal on line 
“b”. This clock signal along with count zero at the slow 
speed section puts a single 1MHz gated clock pulse at the 
Parallel/Serial Control of the CD4021A to permit an eight bit 
parallel transfer of data from the high-speed system to the 
low-speed system. 

R-S Flip-Flops 1 & 2 remove the “Flag” signal “a” after a 
1MHz gated clock pulse on line “b” has generated the 
parallel transfer signal. These flip-flops also prevent any 
further activation of line “a” (and line “b”) and subsequent 
parallel transfers until the CD4022A counts back to zero. 
Thus, the eight bits transferred into the CD4021 A are shifted 
out at the 10kHz clock rate before a new set of data is 
transferred into the CD4021A. Note that the extra pulse 
edge generated at line “b” (one clock pulse after the gated 
1MHz clock pulse) is ignored. (See the Logic of the 
slow-speed section.) For Scope Display purposes, Flip-Flop 
B, in the high-speed system is used to change the pattern 
transferred every eight 10kHz clock pulses from a 10101010 
to a 01010101 pattern. 

In an actual system the high signal at line “a” would 
represent a “Flag” bit, enabling the high-speed system to 
transfer eight bits of new data, any time during the count 
zero. (10kHz clock cycle duration.) This allows the 
high-speed system time to service its many other input and 
output lines and to satisfy internal process requirements at 
the 1MHz rate. At the same time, the high-speed system is 
still conditioning the eight transfer lines (just prior to 
activation of line “b”) with a pulse to enable the parallel 
transfer of data. The re-sync Flip-Flop in the slow-speed 
section helps avoid any gap in the output data due to the 
variable delay possible in line servicing between the eighth 
shifted bit out of the CD4021A and the next parallel transfer 
of the eight valid bits of information. 

Conclusions 

This note has shown the use of several COS/MOS MSI 
counters and static shift registers in systems designs. The 
designs described are useful in a variety of applications. 

The availability of an increasing number of standard 
low-cost COS/MOS devices now permits the systems designer 
greater freedom and versatility as well as increased reliability 
in his designs. 


493 




ICAN-6166 


PACKAGE COUNT 
I-CD402IA 
I-CD4022A 
1 1/2 - CD40I3A 
1 1/4 - CD40IIA 
I -CD400IA 


DATA OUT (10 kHz RATE) 




N-GROUPS 
OF 8 BIT 
DATA LINES 
IN. , 


HIGH SPEED 
SYSTEM 

(I MHz CLOCK) 


JJU 


(b) 


GATED I MHz CLOCK 


FLAG BIT a b 


TOOTHER 
SYSTEMS. 
N-GROUPS 
OF 8 BIT 
DATA LINES 
OUT. 


1 

2 SLOW SPEED 


3 SYSTEM 


5 


® (10 kHz CLOCK) 


8 


SLOW SPEED 

DATA OUT 

OUTPUT 

(10 kHz 


RATE) 



(d) 


10 kHz CLOCK 
°8 

RE-SYNC FLIP-FLOP OUTPUT 
COUNT ZERO 
FLAG BIT (LINE “a") 

I MHz GATED CLOCK(LINEV) 




Fig. 28 - CD4021A "8 bit asynchronous high-speed parallel-input/low-speed serial-output" application; (a) logic diagram , 
(b) block diagram; (c) slow-speed system waveforms; (d) s/ow-speed system waveforms; (e) high-speed system (expanded 
scale ) waveforms 


References: 

1. RCA COS/MOS Commercial Data Sheets, CD4000A 
series and Developmental Data Sheets by “TA” Number 

2. “Power Supply Considerations For RCA COS/MOS IC’s” 
by H. Pujol, ICAN-6576 

3. “Design of Fixed and Programmable Counters Using the 
RCA CD4018A COS/MOS Presettable Divide-by-N 
Counter" by J. Utus, Jr., ICAN-6498 


4. “Complementary MOS Transistor Logic Integrated 
Circuits”, ICAN-5593 

5. “Micropower Crystal-Controlled Oscillator Design using 
RCA-COS/MOS Inverters”, by S.S. Eaton, ICAN-6539 

6. “Astable and Monostable Oscillators Using RCA COS/ 
MOS Digital IC’s”, by J.A. Dean and J.P. Rupley, 
ICAN-6267 


494 










ICAN-6176 



Solid State 
Division 


Digital Integrated Circuits 
Application Note 

ICAN-6176 


Noise Immunity of 
COS/MOS Integrated -Circuit 
Logic Gates 

by S.S. Eaton 


The immunity of a COS/MOS integrated-circuit logic gate to 
noise signals is a function of many variables, such as 
individual chip differences, fan-in and fan-out, stray 
inductance and capacitance, supply voltage, location of the 
noise, shape of the noise signal, and temperature. Moreover, 
the immunity of a system of gates usually differs from that 
of any individual gate. Because of the many variables 
involved, a generalized analysis of the noise immunity of a 
logic circuit is a complex process. In general, it is more 
practical to analyze immunity of a system for a specific set 
of conditions and then to generalize or extrapolate the 
results to make them applicable to other sets of conditions. 

This Note describes the types of noise usually encountered in 
a logic system and evaluates the noise immunity of a 
COS/MOS integrated-circuit logic-gate test setup in relation 
to system variables. The evaluation is performed on a setup 
that includes a CD4000A dual 3-input gate plus inverter and a 
CD4001A quad 2-input gate connected in cascade to drive a 
CD4013A flip-flop. Measurement of the voltage required at 
various gate leads to switch the flip-flop defines the 
noise-immunity threshold of the gate circuits. 

TYPES OF NOISE 

The following listing indicates and briefly explains the types 
of noise usually encountered in logic systems: 

1 . External noise - noise that is generated externally 
by electric motors, arcing relay contacts, circuit 
breakers, and other similar types of devices. Such 
noise is usually inductively coupled into the logic 
system. 


2. Crosstalk - noise that results from coupling (usu- 
ally capacitive) between adjacent signal lines. 

3. Transmission-line reflections - noise introduced 
into the logic system when an impedance mismatch 
exists at the receiving end of the line. The energy 
reflected back along the line causes ringing, and 
voltage levels produced may exceed -the noise- 
immunity threshold of the receiving gate. This 
type of noise is most prevalent when the switching 
time of the gate is short in comparison to the time 
delay of the line. 

4. Power-line noise - noise that results from tran- 
sient currents produced in the supply line by cou- 
pling from external sources or by stray or junction 
capacitances at the gate outputs. 

5. Ground-line noise - noise that is produced on the 
ground line because of improper ground returns. 

This Note evaluates the noise immunity of the CD4000A and 
CD4001 A COS/MOS integrated-circuit logic gates with respect 
to each type of noise listed above with the exception of that 
produced by transmission-line reflections. Because this type 
of noise is specifically a function of the transmission line, a 
generalized analysis is not as effective as in the case of the 
other types of noise. However, transmission-line reflections 
are not significant in COS/MOS circuit systems because the 
switching speed of a COS/MOS circuit is generally slow in 
comparison to the time delay of a line. The schematic and 
logic diagrams of the CD4000A and CD4001A gates are 
shown in Figs. 1 and 2, respectively. 


11-73 


495 




ICAN-6176 




Fig. 1 - Schematic and logic diagrams of the CD4000A dual 
3-input gate plus inverter. 




Fig. 2 - Schematic and logic diagrams of the CD4001A quad 
2-input gate. 


SIGNAL-LINE EXTERNAL NOISE IMMUNITY 

The following analysis was used to determine the immunity 
of a COS/MOS gate to noise on the input line at both the“0” 
(low-level) and “1” (high-level) states. 

“0”-State Analysis 

The signal-line noise immunity of COS/MOS gates was 
evaluated by use of the test circuit shown in Fig. 3(a). The 
COS/MOS gate under test was the inverter section of a 
CD4000A. Fig. 3(b) shows the results obtained. The test setup 


is designed to measure the voltage required at the input of 
the inverter to trigger a CD4013A flip-flop. The logic diagram 
of the CD4013A is shown in Fig. 4. 

During test, a noise pulse is introduced on the signal line of 
the CD4000A inverter. At some voltage level, depending on 
the width of the pulse and the gate thresholds, this pulse 
causes the flip-flop to be “set” because of the rising voltage 
on the set input that results from the decreasing voltage at 
the output of the inverter. This level defines the permissible 
input range for a logical “0.” The measured value for a 
supply voltage of 10 volts was 4.4 volts. For a supply voltage 


496 





ICAN-6176 




Fig. 3 - (a) Test circuit and (b) measured results for "O "-state 
signal-line noise-immunity test. 


to trigger the CD4013A flip-flop at a supply voltage Vj)D of 
10 volts. Fig. 5(b) shows that a signal of 5.45 volts is 
required at the injput to the CD4001A gate to produce an 
output of 5.5 volts. 

Similarly, Fig. 5(c) shows that the CD4000A inverter requires 
an input of 4.45 volts to provide 5.45 volts to the input of the 
CD4001A gate. An input of 4.45 volts to the CD4000A in- 
verter, therefore, should trigger the CD4013A flip-flop. The 
actual measured value of the voltage required to trigger the 
flip-flop, as shown in the curve for Vdd = 10 V in Fig. 3(b), 
is 4.4 volts. (All measured values shown on all graphs are 
typical, obtained from measurements on gates that have 
typical threshold switching characteristics.) 

“1 ’’-State Analysis 

Fig. 6 shows the test setup used and the results obtained 
from noise-immunity measurements on the COS/MOS logic 
gates when the input to the CD4000A inverter gate is high and 
a negative-going pulse is superimposed on the signal line. As 
in the case of the “0”-state evaluation, a dc analysis of the 
component transfer characteristics may be made to verify the 
measured noise immunity. Fig. 5(c) shows that the input to 
the CD4000A must decrease from 10 volts to 4.5 volts (a 
margin of 5.5 volts) to provide the 5. 5 -volt output required 
to trigger the flip-flop. The measured value of the required 
decrease in voltage, as shown in Fig. 6(b), is 5.3 volts. 


of 14 volts, the measured value of the voltage required to 
trigger the flip-flop was approximately 6.2 volts. 

A dc analysis of the transfer characteristics of the 
components included in the test setup, shown in Fig. 5, can 
also be used to determine the noise level required to set the 
flip-flop. Fig. 5(a) shows that an input of 5.5 volts is required 


POWER-SUPPLY NOISE IMMUNITY 

The test configuration shown in Fig. 7(a) measures the 
ability of the CD4000A inverter to withstand a negative-going 
noise pulse on the supply line without a change in state. A 
pulse of sufficient amplitude causes the output of the gate to 
decrease so that, at some point, the CD4013A flip-flop will be 



TERMINAL 14 » V DD 
TERMINAL 7 > GND 

Fig. 4 - Logic diagram and truth table for the CD4013A 
COS/MOS integrated circuit flip-flop. 


**TG « TRANSMISSION GATE 


INPUT TO OUTPUT IS: j 

o) A BIDIRECTIONAL LOW IMPEDANCE Z 
WHEN CONTROL INPUT 1 IS "LOW" T . 

AND CONTROL INPUT 2 IS "HIGH" 

b) AN OPEN CIRCUIT WHEN CONTROL 

INPUT 1 IS "HIGH" AND CONTROL INPUT 2 IS "LOW" 

*** . FF1/FF2 TERMINAL ASSIGNMENTS 


TRUTH TABLE 



* • LEVEL CHANGE 


x - DON'T CARE CASE 


497 









ICAN-6176 










V DD 

= 14 V 









1 

1 








^DD = l 

) V 








1“ 

1 










T 

i 










T 










T 










T 






A I I I I U - J I A I I 

0 2 4 6 8 10 

INPUT (SET)— V 


(a) 



INPUT -V 

(b) 



(c) 

Fig. 5 - Transfer characteristics for (a) the CD4013A flip-flop, 
(b) the CD4001A quad 2-input NOR gates, and (c) the 
CD4000A inverter gate. 




(b) 


Fig. 6 - (a) Test circuit and (b) measured results for the 
"1 "-state signal-line noise immunity test. 


triggered from the rising voltage at the output of the driving 
inverter stage. The curves in Fig. 7(b) show the noise 
immunity level for noise pulses on the power supply to be 
4.2 volts at 10 volts and 5.7 volts at 14 volts. 



(a) 


7 












1 












\ 









V DD 

14V 



V 








v DD = 10V 



























0 200 400 600 800 1000 1200 

PULSE WIDTH - ns 


(b) 


Fig. 7 - (a) Test circuit and (b) measured results for the 
power-line noise-immunity test. 


498 









ICAN-6176 


GROUND-LINE NOISE IMMUNITY 

Noise on the power line may be effectively reduced or 
eliminated by use of decoupling capacitors; ground-line 
noise, however, cannot be reduced so easily and, therefore, is 
more objectionable. Fig. 8(a) shows the test circuit used to 
measure the ground-line noise immunity of the COS/MOS 
gate, and Fig. 8(b) shows curves of the measured results 


,-TL 


(a) 


CD40I3A 



fl> 


(a) 


GATE UNDER 
TEST 




(b) 

Fig. 8 - (a) Test circuit and (b) measured results for the 
ground immunity test. 



(b) 

Fig. 9 - Switching curves for the CD4013A COS/MOS flip-flop. 



Fig. 10 - Circuit used for test of noise voltage as a function 
coupling capacitance. 


obtained. The noise pulse introduced on the ground line of 
the CD4000A inverter raises the potential of the output of the 
gate until the flip-flop is triggered. The close similarity of the 
COS/MOS flip-flop switching curves shown in Fig. 9(b) and 
the noise-immunity curves shown in Fig. 8(b) confirms a 
volt-for-volt change at the gate output with a change in 
ground potential for the COS/MOS circuit. 

CROSSTALK NOISE IMMUNITY 

A test circuit that may be used to evaluate crosstalk is shown 
in Fig. 10. A noise pulse from a pulse generator is coupled to 
the signal line of the CD4000A gate through a capacitor. The 
noise voltage necessary to trigger the flip-flop is then 
measured for different values of capacitance under “high” 
and “low” input conditions. Fig. 11 shows the results of 
these tests. As expected, the noise amplitudes required to 
trigger the flip-flop are higher for lower capacitance values. A 
more meaningful evaluation of the circuit is provided by the 
curves in Fig. 12, which show the noise amplitude as a 
percentage of the supply voltage. Because crosstalk is caused 



Fig. 11 - Noise immunity as a function of coupling 
capacitance. 


499 










ICAN-6176 



Fig. 12 - Noise immunity in terms of percentage of supply 
voltage. 

by varying signals coupled from adjacent lines and the logic 
swing of these signals is limited and approaches the supply 
voltage, the percentage of the supply voltage coupled at the 
time when the flip-flop is set is a more meaningful value than 
the actual value of the voltage at this instant. For example, if 
the amplitude of crosstalk noise required to trigger the 
CD4013A flip-flop at a supply voltage of 10 volts is less than 
that required at a supply voltage of 14 volts, this condition 
does not imply that a COS/MOS logic circuit operated at 14 
volts is more immune to crosstalk than a similar circuit 
operated at 10 volts because of the different logic swings 
involved. 

The results shown in Figs. 11 and 12 also provide a 
meaningful comparison between low- and high-state 
operation of the COS/MOS gates. In general, a greater noise 
immunity is achieved in the low state. 

Although the test circuit shown in Fig. 10 yields reliable 
data, the measured values are not entirely representative of 
actual operating conditions. The circuit shown in Fig. 13 




FROM PULSE 
GENERATOR 


0 V 


Fig. 13 - Test circuit used to determine crosstalk noise 
susceptibility. 


more closely approximates crosstalk caused by adjacent 
signal lines. In this circuit, CD4001A gates are used as the 
driving inverters for the CD4013A flip-flop. The output of 
inverter No. 1 can be made either high or low for crosstalk 
tests in both logic states. The response of this test circuit to a 
noise pulse may be explained by analysis of the response of a 
high-pass RC circuit to a ramp input of Vj = at. The output 
voltage V G may be expressed by the following equation: 

V o = a RC (1 - e' ,/RC ) (1) 

The equivalent circuit for the part of the test configuration 
used in this analysis is shown in Fig. 14. On the basis of this 
equivalent circuit, Eq. (1) may be rewritten as follows: 

V o =a(Z //Z. n )C [l -e- f/ ( Z o //Z in) C] (2) 
max 

If Vj is assumed to be at (where t is the rise time) during the 
period in which the output voltage switches from 10 to 90 
per cent of its total value, this change in output voltage can 
be expressed as follows: 


A v 


v i <z 0 // Z in ) C 


[l-e-*/ (Zo//Zm) C] (3) 



Fig. 14 - Equivalent circuit for noise analysis of the test 
configuration shown in Fig. 13. 


The results of this analysis may be applied to the various 
crosstalk waveforms obtained. Fig. 15 shows photographs of 
V 0 with the output of inverter No. 1 in the high state. Fig. 
15(a) shows the crosstalk pulses obtained for the CD4001A 
COS/MOS gate for a capacitance C of 100 picofarads. Noise 
pulse’s are obtained only at certain time intervals which 
correspond to the rising and falling edges of the voltage Vj. 
Only the falling pulses are considered in the following 
analysis^ because they are responsible for triggering the 
flip-flop. 

Eq. (3) may be used to calculate the amplitude of the pulses. 
The noise pulse introduced to the test circuit switches from 
90 to 10 per cent of its final value in 17 nanoseconds (fall 
time). Because of the 100-picofarad capacitance C at the 
output of inverter No. 3, the fall time at this point should be 
somewhat greater than 17 nanoseconds. The actual measured 
value is 130 nanoseconds. In Eq. (3), therefore, t = 130 
nanoseconds, AVj = (0.090) (10) - (0.10) (10) = 8 volts, 
Zin«10l2 o hms, Z 0 ^ 550 ohms (for the COS/MOS 


500 





ICAN-6176 


integrated-circuit gate used), and C = 100 picofarads. The 
output voltage swing AV 0max is then calculated as follows: 

(8 V) (550 £2) (IQ' 10 F) 


A V, 


°max " 


130 x 10' 9 s 


In the low state, the output impedances of the COS/MOS 
logic circuit are low enough (550 ohms) and the rise times 
sufficiently slow that the flip-flop could not be triggered at 
any value of capacitance used (up to 10 microfarads). 


130 x 10' 9 
[1-e 

=3.1 V 

Fig. 15(a) shows that the measured value of the fall voltage 
(about 2.9 volts) is in close agreement with the calculated 
value. Fig. 15(b) shows the crosstalk pulse for the same 
COS/MOS circuit with a noise pulse rate of 500 kHz rather 
than 54 kHz. As Eq. (3) implies, the pulse rate does not seem 
to change the noise amplitudes. 


'(550 12) (10* 10 F) ] 




Fig. 15 - "1 "-state crosstalk waveforms: (a) frequency = 54 
kHz, pulse width = 5 ps/cm, and pulse amplitude = 5 V /cm; 
(b) frequency = 500 kHz, pulse width = 1 ps/cm and pulse 
amplitude = 5 V /cm. 


Crosstalk measurements that simulate actual operation are 
made by use of the test circuit shown in Fig. 16. In this 




Fig. 16 - Crosstalk test circuit which uses tightly coupled 
cable to simulate actual operating conditions. 

circuit, a sense line is placed tightly within five surrounding 
wires (No. 22 gauge) to form a 7-foot-long cable which has a 
capacitance of 30 picofarads per foot (determined by 
measurement). The cable is used to simulate a worst-case 
cable with 5 gates switching on lines adjacent to one wire. 
The results of this test are shown by the photographs in Figs. 
17 and 18. Fig. 17 shows the effect of the capacitive loading 



Fig. 17 - Crosstalk waveform showing effect of load 
capacitance (output of CD4001A inverter No. 3; frequency = 
500 kHz, pulse width = 1 ps/cm, and pulse amplitude = 2 
V/cm). 


501 







ICAN-6176 



10 V 

(AC COUPLED) 



(b) 


Fig. 18 - Crosstalk waveforms for (a) "O" state and ( b ) "1" 
state (frequency = 500 kHz, pulse width = Ips/cm, and pulse 
amplitude =1 V/cm for "O" state waveforms or 0.2 V/cm for 
"1 "-state waveforms). 


on the fall time of the inverted output waveform. Fig. 18 
shows the “0”-and “1 ’’-state crosstalk coupled to the sense 
line. In both cases, the forward crosstalk, or noise, at the 
receiver end of the cable (the input to inverter No. 2 in Fig. 
16) matched back crosstalk, or noise at the driver end of the 
cable (the output of inverter No. 1). The crosstalk does not 
trigger the flip-flop in either the “O” or “1” state. Even with 
a tightly coupled 7-foot cable, the COS/MOS gate does not 
change state falsely. 

CONCLUSIONS 

The results of all tests show exceptionally high noise 
immunity for COS/MOS integrated-circuit gates. Typical 
noise-immunity values range from 4.5 to 5.5 volts for a 
supply voltage Vj)D of 10 volts, and 5.5 to 8.5 volts for a 


Vdd of 14 volts. These high values are achieved with gate 
power consumptions in the microwatt range, as compared 
with much higher (milliwatt) consumptions and much lower 
noise immunities (about 1 volt) for saturated bipolar logic. 
Factors contributing to the high noise immunity of 
COS/MOS gates are the relatively slow speeds and relatively 
low (500 ohms) output impedances. 


Because it is impossible to study all cases of noise immunity, 
the cases chosen are meant only to be representative. Noise 
pulses are certainly not all rectangular in shape, and the same 
type of integrated circuit may have widely differing 
characteristics. It is hoped, however, that enough 
information is presented to permit generalization to other 
cases not specifically studied. 


502 





Solid State 
Division 


Digital Integrated Circuits 

Application Note 
ICAN-6210 


A Typical Data-Gathering & 
Processing System Using 
CD4000A-Series COS/MOS Parts 


by D. Block 


INTRODUCTION 

The broad line of COS/MOS standard parts in the 
CD4000A series,^ including many MSI functions not available 
in other logic families, provides the design engineer with the 
tools to implement a large number of digital functions. 
The well-known characteristics of COS/MOS circuits, ^ such 
as low power dissipation, wide supply-voltage range, high 
noise immunity, and excellent temperature stability, can make 
possible cost-effective' systems for a variety of applications, 
and have opened up new areas where electronic controls 
were not previously suitable for a variety of reasons. 

This Note considers the area of data gathering and pro- 
cessing, and is developed in terms of a typical system for 
process controls. Emphasis is placed on applications of the 
newer parts in the CD4000A line. Also stressed are the flexi- 
bility of system design and common data-bus architecture 
made possible by the three-state outputs and bidirectional 
input/outputs incorporated in many COS/MOS circuits and 
the ease of system design for data handling in increments of 
4 bits made possible by the careful planning of the CD4000A 
family. 


The implementation of the system described is shown in 
terms of the COS/MOS standard parts which can be used to 
perform the desired system functions. Specific details, such as 
pin numbers, are not provided; rather attention is focused on 
the multiplicity of applications which can be handled by a 
single product and the scope of information processing which 
can be covered by standard parts. 

The fine points of circuit design, which would have to be 
dealt with in any real-world design, are not treated here. The 
approach adopted is one of “filling in the blocks” to show 
which COS/MOS standard parts can be used to implement a 
particular function, and how these blocks tie together to 
create a system. 

SYSTEM DESCRIPTION 

The over-all system described is one which accepts 
asynchronous inputs of analog or digital data and operates on 
that data; the output is display and control information. Fig. 1 
shows a block diagram of the entire system. It is assumed that 
the input signals from remote sensors are digitally encoded 
and transmitted to the central Processor Unit for data manipu- 


ANALOG 

SIGNALS 



92CS-2I494RI 


Fig. 1 — Block diagram of the Data-Gathering and Processing System. 


503 




ICAN-6210 


lation. It is also assumed that the controlled functions are at a 
distance from the Processor and that data is transmitted from 
the Processor to the Controller by frequency-modulation 
techniques. At the Controller, data is reconstructed to an NRZ 
data-word format which can then be used for direct digital 
control or converted to an analog voltage for proportional 
control of servos, etc. 

The display output at the Processor is a 4-digit, liquid- 
crystal display located in reasonable proximity to the rest of 
the logic. Thus, the areas to be considered for COS/MOS 
implementation include A/D and D/A conversion, data trans- 
mission and reception, and data processing. Serial-to-parallel 
and parallel-to-serial conversion are included since a common 
data bus architecture is assumed in the Processor Unit. 

Two power supplies, + 10 volts and —5 volts, are used in 
the system. All COS/MOS parts require only a single power 
supply and single-phase clock, and logic levels in the system 
will be from Vgg = 0 volts to Vj)j) = 10 volts. However, the 
negative supply can be used to advantage, as examples in this 
Note will show, to permit transmission of signal levels above 
and below ground, and to develop 1 5 volts across the liquid- 
crystal display for good readability. 

INPUT SIGNAL CONDITIONING AND TRANSMISSION 

Fig. 2 shows the conversion of analog input voltages to a 
serial-data stream. The CD4051A’s are used as multiplexers to 
connect, one at a time, each of the 16 analog input voltages to 
the A/D converter. When the conversion is completed, a signal 
from the converter gates an oscillator ON which causes the 
8-bit result of the A/D conversion to be multiplexed into a 
serial-data stream. This data, along with a clock, is transmitted 
to the Processor Unit. A CD4047A used in the negative-trigger, 
astable mode provides a reset pulse to the A/D converter on 
the negative transition of Q3 . The pulse indicates that the 8-bit 
data stream has been transmitted and that the input multi- 


plexer has been stepped to the next address. By taking ad- 
vantage of the capability of the CD4051A’s to operate from 
two power supplies, analog voltages above and below ground 
can be switched by control-signal inputs of 0 to 10 volts. 
Note that the CD4051 A is suitable for both analog and digital 
multiplexing applications and that, because of the Inhibit 
input, which entirely disconnects the common outputs, two 
or more units can be wire-OR’ed. 

The A/D converter can also be assembled with COS/MOS 
standard parts, as shown, in Fig. 3(a). The CD4040A binary 
counter, used in conjunction with an R/2R resistor ladder 
network, generates a staircase ramp at the negative input to 
the comparator as shown in Fig. 3(b). When the ladder voltage 
matches the analog input., the comparator output goes low. 
This signal is inverted by the CD4007A and becomes a logic 1 
latched into the flip-flop. This action inhibits additional clocks 
to the counter and indicates that the conversion is complete. 
The output of the counter, which is buffered by high-current 
CD4041A’s to minimize switch impedance effects on the re- 
sistor ladder, is the digital equivalent of the analog input 
voltage. A reset clears the flip-flop and resets the counter so 
that the next conversion can begin. 

To generate a staircase from —5 volts to 10 volts, one end 
of the resistor ladder is connected to —5 volts, and the counter 
is connected with a Vj)j) of 10 volts and a V$s of -5 volts. 
Since the clock and reset signals to the counter must then 
swing from —5 volts to 10 volts, a CD4054A is used as a level 
translator. 

A micropower op-amp, the CA3080A, is used as a voltage 
comparator for the D/A converter. The op-amp is gated off 
after the conversion is completed by turning off a p-device of 
the CD4007A supplying bias current to the unit. In this way, 
power dissipation is reduced to a few microwatts in the standby 
state during those times in which a conversion is not actually 
being performed. With the active bias current (I a b c ) set at 
15 microamperes, typical power dissipation for the CA3080 is 


SENSOR 

INPUTS 




Fig. 2 — The conversion of analog input voltages to a serial-data stream. 


504 






ICAN-6210 


about 500 microwatts with a V+ of 10 volts and a V— of —5 
volts. Dissipation during a conversion would be approximately 
20 milliwatts at a clock rate of 100kHz for the circuit shown in 
Fig. 3. Standby dissipation, however, would typically be less 
than 50 microwatts. Care must be taken not to exceed the 
common-mode input voltage of the op-amp. 


DIGITAL PROCESSOR UNIT 

A block diagram of the Processor Unit is shown in Fig. 4. 
Four internal bus systems are used. The Control Bus carries 
discrete control and timing signals from the Control Unit to 
the various sub-units; the other three bus systems are 8-bit, 
parallel transfer buses. The Memory Bus (M) carries memory 


+ IOV 

I 


+IOV -5 V 

L 5 


ANALOG 

VOLTAGE 

INPUT 


c 

R 

Ql 

Q2 Q3 

CD4040A 

04 Q5 

06 07 

08 

pz 

.1 1 

_E 



1 1 . 

: x 


CD404IA 




CD404IA 



2R> 2R> 2R> 2R> 2R> 2R> 2R> 2R 

O-^VWWwiAAA^AA/V^AAA^A/VV^VwiwV 


+ ioO- 



DF 

CD4054A 

IN 


INI 

STl’ ST 2 IN 2 


RESET 

92CM-2232I 



(b) 

Fig. 3 — (a) The A/D converter assembled with COS/MOS standard parts, (b) staircase ramp generated by the 
CD4040A binary counter. 


505 







ICAIM-6210 



Fig. 4 - Block diagram of the Processor Unit 


address information from the Control Unit to the Memory and 
Output Buffer, while the Data Bus (D) is used for common 
data transfers between all subsystems. The third parallel bus is 
internal to the Arithmetic Unit and is used for high-speed 
transfer of data between registers in that unit. It is assumed 
that, because of bandwidth limitations, data input and output 
rates are asynchronous with respect to the system internal 
clocking and, therefore, that the I/O’s are interfaced with the 
D bus under command of the Control Unit. 


RECEIVER 

Fig. 5 shows the Receiver portion of the Processor. A 
CD4034A is used in the serial-in/parallel-out mode for data 
serial-to-parallel conversion, and also functions as a holding 
register for input data until the Control Unit calls for it to be 
strobed onto the D bus. A CD4017A associated with each 
register counts input clocks and, when output number “8” 
goes high, indicates that its associated register is full. A 
scanner, consisting of a CD4052A dual-4-channel multiplexer, 



DATA BUS 92CS-2I493RI 

Fig. 5 — Receiver portion of the Processor. 


506 










ICAN-6210 


sequentially examines each counter and reports to the Control 
Unit when any register is ready to be read out. A pulse from the 
Control Unitback through the CD4052A resets the counter and 
strobes the appropriate register onto the D bus. 

MEMORY 

The Memory portion of the Processor is shown in 
Fig. 6(a). Eight CD4061A’s are paralleled to form the 8-bit 


structure required for the D bus. A chip enable feature 
allows the Data Input and Data Output terminals of these 
units to be tied together since both are disconnected when 
the Chip Enable input is high. (The Chip Enable input must be 
high prior to any change of address.) The Read/Write control 
determines whether parallel data will be written from or read 
onto the Data Bus when the memory is enabled. With reason- 
able capacitive loading, read access times of about 400 nano- 



Fig. 6— (a) Memory portion of the Processor, (b) an exp mded memory organization to 4096 words. 


507 






I CAN -62 10 


seconds are achievable. The CD4042A’s, which are quad- 
clocked latches, are used as a memory address register. 

An expanded memory organization to 4096 words is 
shown in Fig. 6(b). Here the eight-package organization of 
Fig. 6(a) is taken as a basic building block and repeated 16 
times. Four more address bits on the M Bus can be decoded 
into 16 discrete block-enabling signals by using a CD4028A. 
The decoded outputs must be inverted to provide the “low” 
enabling signal required by the CD4061A memories. The en- 
tire memory can be disabled, i.e., effectively disconnected 
from the D Bus, by maintaining the Memory Disable signal low. 

The memory could be used in this system to store pro- 
gramming instructions for the Control Unit, parameter limits 
against which new inputs are to be compared, instruction 
words which are to be sent to the remote controller, etc. 

ARITHMETIC UNIT 

An extremely flexible Arithmetic Unit can be configured 
by using two CD4057A 4-bit arithmetic arrays and three 
CD4034A shift registers, as shown in Fig. 7. The CD4057A’s 
have a 16-instruction repertoire, as shown in Table I. The ad- 
dition of four operational modes which control transfer of 
information, either serial data or arithmetic carries, and the 
I/Ocontrol, makes the CD4057A a powerful tool for arithmetic 
operations. The results of these operations are fed back to the 
Control Unit of the D bus and overflow indicator, and are used 
to determine the next sequence of operations. 


The bidirectional data input/output capability of the 
CD4Q57A’s and CD4034A’s enables units to be arrayed on 
their own Arithmetic Bus A and to communicate directly with 
all other subsystems. 

Register A contains two CD4057A’s for arithmetic 
operations and a CD4034A to allow left shifting of results as 

Table I — The 16-Instruction Repertoire of the CD4057A 

NO-OP (Operational Inhibit) 

AND 

Count down 
Count up 

Subtract from zero (SMZ) (Stored number) 

Subtract from memory (SM) (Stored number from memory) 
Add (AD) 

Subtract (SUB) (Memory from stored number) 

Set to one 
Clear to zero 
Exclusive-OR 
OR 

Input Data (From parallel data lines) 

Left shift 
Right shift 
Rotate (cycle) right 


MODES 


INSTRUCTIONS 


TRUE /COMPLEMENT 
CONTROL 



92CM-22 323 

Fig. 7 — The Arithmetic Unit. 


508 








ICAN-6210 


would be required in a multiplication algorithm. Parallel data 
entry or access to the A bus is possible for the shift register 
from the A side of the CD4034A. When all inputs on the B side 
are grounded, the shift register can be reset by performing a 
parallel-input operation on the B side. 

Register B is a general-purpose register which could be 
used to hold intermediate results, a multiplicand, or for shift- 
right expansion of register A. With the configuration shown, 
i.e., with the output of Q8 connected to the input of Q7 and 
so forth, register B can be made to shift left as well as right, 
its normal mode of shifting. Left shifting is accomplished by 
enabling synchronous data entry on the B side and clocking 
the register. The addition of a CD4030A exclusive-OR gate 
causes .the register to be complemented when the True/ 
Complement Control signal is high and data is right shifted 
around once. With the control signal low, data is recirculated 
without modification. Here again, the three-state outputs on 
the A side of the B register allow parallel or serial data transfer 
to and from the A bus. 

The C register is used as an interface buffer between 
the A and D buses and for data storage or right-hand expansion 
of the A register. Table II shows the modes of operation for 
buffering and the required control-signal levels. The one mode 
which is not realizable directly from Table II could be ac- 
complished by putting two CD4016A transmission-gate pack- 
ages between the B side of the CD4034A and the A bus. 
Register C can be cleared by setting the Recirculate-Zeros 
control-line low and shifting data around once. Of course, a 
parallel entry of zeros from either the A or D bus would also 
serve as a reset for this register. 

DISPLAY OUTPUT 

The display unit for numerical outputs is shown in Fig. 8. 
The CD4056A is used as interface with a 4-digit liquid-crystal 
display, the TA8054R. Each CD4056A contains a 4-bit latch, 
a BCD-to-7 -segment decoder, level shifters, and display drivers. 
When a square wave is applied to the Display-Frequency input 
of the CD4056A and as a common to one side of the display, 
the selected segment outputs consist of a square wave 180° 


Table II — Modes of Operation for Buffering and the 
Required Control-Signal Levels for the C 
Register 



1. Input from D, disconnect from A* 

2. Input from D, connect to A 

3. Disconnect from D, connect to A 

4. Disconnect from D, disconnect from A 

5. Input from A, disconnect from D 

6. Input from A, connect to D 

7. Disconnect from A. connect to D 

8. Disconnect from A, disconnect from D 



•Note: 

These “AY' refer to the A (Arithmetic) Bus, not to the "A side" of the CD4034A. 

92CS-22324 


out of phase with the common. The signal causes the ap- 
propriate segment to become visible. Unselected outputs are 
in phase with the common, and the appropriate segment is then 
not visible. The two voltage-supply terminals of the CD4056A 
permit a higher voltage to be used across the display than 
appears on the control inputs to the device and allows for 
maximum contrast ratio on the display. At 15 volts and a 
frequency of 60 Hz, typical operating current for the display 
is only 1 25 microamperes. 

Assuming that the normal data-bus information is in 
standard binary notation, conversion to BCD for the display 
can be handled in the Arithmetic Unit by using the Couleur^ 
technique or hard-wired, IC-implemented schemes.^ Since 
the D bus is 8 bits, two transfers are necessary to display all 
4 digits. 


DISPLAY INTERFACE 



TA8054R 

4 -DIGIT LIQUID CRYSTAL 


Fig. 8 — Display unit for numerical outputs. 


509 





I CAN-6210 


OUTPUT BUFFER 

The Output-Buffer circuitry, shown in Fig. 9, is realized 
by using a memory in a parallel-write/serial-read mode. The 
CD4051A is used as a multiplexer to enable one CD4061A 
memory circuit at a time when the Read/Write control line is 
low (for Read) and the Inhibit input of the CD4051A is also 
low. If the Inhibit input were high in the read mode, then all 
multiplexer outputs would be off since, with both inputs 
low to each gate, all NOR outputs will be high, and the 
memory will be disabled. Note that pull-down resistors are 
used to define a logic 0 level to the NOR gate since the 
tri-state outputs of the CD4051 A would otherwise leave those 
inputs floating. Whenever the Read/Write control line goes 
high, all NOR gate outputs will be forced low and a 
parallel Write operation will be enabled. 

For the greatest flexibility in this buffer application, 
CD4029A up/down presettable counters have been used for the 
address register. A starting address is strobed into the register 
by using the Preset Enable inputs of the CD4029A’s. The clock 
is then enabled to provide a serial-memory readout where the 
address is automatically advanced or decremented at a rate 
suitable for the transmission medium. A faster clock can be 
used to fill the memory initially from the D Bus in the 
Write Mode. A CD4019A AND/OR select gate is used to 
switch between the two clocks. By disabling the clock 
entirely, the CD4029A can be made to perform as a simple, 
4-bit latch to randomly access any particular memory location. 

As an example of the use and operation of the entire 
Control Unit, consider the case where one of the system 


analog inputs represents water pressure being monitored in a 
pipe. The digitized pressure reading would be entered into the 
Arithmetic Unit and then subtracted from a maximum or 
minimum limit number brought from memory. In addition, 
the present reading could be compared against the last reading 
stored in memory and the result compared with yet another 
stored parameter to determine whether the difference in two 
readings lay within expected bounds. A rapid pressure drop, 
for instance, could indicate a leak in the line and would 
require a warning message to be generated and special action 
to be taken by the controls. 


OUTPUT TRANSMITTER 

The Transmitter portion of the system, shown in 
Fig. 10(a), consists of an NRZ-to-biphase data converter 
(CD4037A) and a VCO (CD4046A), so that output data will 
be in the form of biphase FSK. This type of modulation is 
preferred in many applications since one zero-crossing is 
generated during each bit period; this arrangement simplifies 
clock recovery. However, this technique is relatively wasteful 
of bandwidth. The CD4037A generates biphase data, as 
shown in Fig. 10(b), when supplied with a clock and clock at 
twice the bit rate. The output of the circuit is used to control 
a transmission gate (CD4016A) which switches R3 in parallel 
with R2, thus changing the input voltage to the VCO. The 
VCO output, then, is two discrete frequencies determined by 
the ratios of R1 and R2 for a logic 1 and R1 to R2/R3 for a 
logic 0. 



92CM- 2I500R I 


Fig. 9 — Output-Buffer circuit. 


510 





ICAN-6210 



(a) 



(b) 


Fig. 10 — (a) Transmitter, (b) biphase data generated by the 
CD4037A. 


RECEIVER 

The block diagram of the Receiver is shown in Fig. 1 1(a). 
After amplification, the FSK signal is detected in a phase- 
locked loop using the CD4046A and a threshold detector 
(Fig. 11(b)). Clock and data reconstruction is accomplished 
by the circuit shown in Fig. 1 1(c). 

The flexibility of COS/MOS devices is demonstrated in 
Fig. 12 in which an op-amp circuit that can be used to 
amplify the incoming signal to the Receiver is configured. The 
op-amp consists of two CA3600E packages, which are 
CD4007A units specially tested for linear applications, and 
one CA3046 bipolar-transistor array. This circuit is unusual in 
that it is responsive to small-signal, ground-referenced inputs, 
and the output stage can easily be driven to within 10 milli- 
volts of Vdd or V§s when R-l is very high. 

In Fig. 11(b), the phase-locked loop locks onto the 
incoming frequency. The voltage controlling the VCO then 
assumes two discrete values corresponding to whether the 
loop is locked onto fj, representing a binary 1, or ^ repre- 
senting a binary 0. A Schmitt trigger, constructed of a 
CD4007A and used here for threshold detection, discriminates 
between the two voltages and produces a clean 1 or 0 output. 
This action completes the demodulation of FSK into a biphase 
data stream. 

The next step is to reconvert the data in the biphase 
data stream to the original NRZ and recover the clock signal; 
Fig. 1 1(c) shows how this can be done. The biphase data (A) is 


differentiated to mark the locations of data transitions. This 
differentiation provides a reference frequency at twice the bit 
rate of the phase-locked loop. However, some of the pulses will 
be missing where transitions occurred in the original data 
stream (B). To provide a reliable clock, the VCO is forced to 



92CS-223I6 


(a) 



THRESHOLD DETECTOR 
WITH HYSTERESIS 
( R 2 >R| ) 


92CS-223I8 

(b) 

PHASE LOCKED LOOP 
LOW-PASS FILTER 



Fig. 11 — (a) Receiver, (b) phase-locked loop consisting of a 
CD4046A and a threshold detector, ( c } circuit for 
dock and data reconstruction. 


511 











ICAN-6210 


run at twice the bit rate by FF1, which divides the VCO out- 
put by two before returning it to the phase comparator (D). 
The differentiated signal is gated such that only every other 
pulse is permitted through to the phase comparator (C). In 
this way, the PPL does not see the missing pulses, and the VCO 
output remains constant at twice the bit rate. FF2 provides the 
necessary 90° phase shift to geherate a clock signal for 
incoming data (E). The output of FF3 is the recovered binary 
information (F). Initial synchronization of the system is ac- 
complished ' by preceding actual data transmission with a 
string of alternating 0’s and l’s.^ 

Typical data rates up to 600 kHz can be realized within 
the frequency range of the VCO incorporated in the CD4046A 
with the VCO operating at 10 volts. 

CONTROL UNIT 

Binary information recovered at the Control Unit can be 
used directly to control on/off functions by a particular bit in 
the data word, or a complete word can be converted to an 
equivalent analog voltage for proportional control of servos, 
for example. An A/D converter realizable with COS/MOS 
standard parts is shown in Fig. 13. In a configuration analogous 
to the Receiver portion of the Control Unit, a data word is 
clocked into a CD4034A register and, after all 8 bits have 



92CS-22320 OR AMP. 

(FIG. 13) 


Fig. 13 - A D/A converter that can be made up of COS/MOS 
standard parts. 

been received, the output of a CD4017A (connected in a 
divide-by-8 mode) strobes the word into a CD4042A holding 
register. Register outputs are buffered by CD4041A’s to an 
R/2R resistor ladder and a voltage follower. The COS/MOS 
op-amp shown in Fig. 12 can be used as the follower. 



Fig. 12 — Op-amp circuit that can be used to amplify the incoming signal to the Receiver or as a voltage 
follower in the Control Unit. 


512 






I CAN-62 10 


SUMMARY 

The wide range of logic functions available as standard 
parts in the ever-expanding CD4000A line provides the design 
engineer with the building blocks for a wide variety of digital 
functions. Complex logic functions realized on a single IC 
permit the designer to think in large-scale system terms. The 
flexibility of design made possible by such features as bi- 
directional inputs and outputs and three-stage logic results in 
a minimum package count, even for complex systems. These 
features, coupled with the well-known advantages of COS/MOS 
circuits in the areas of noise immunity, low power, high 
fanout, power-supply tolerance, temperature stability, and off- 
the-shelf availability of parts for both bread-boarding and 
production, make a very attractive combination for the de- 
signer. 


REFERENCES 

1 . COS/MOS Digital Integrated Circuits Databook, RCA Solid 
State Databook Series, SSD-203A, 1973. 

2. RCA COS/MOS Integrated Circuits Manual, Technical Series 
CMS-271 , 1972 

3. J.F. Couleur, “BIDEC - A Binary to Decimal or Decimal to 
Binary Converter,” IRE Transactions on Electronic Com- 
puters, Dec. 1958. Also see ref. 1 , pp. 176-178. 

4. Z.M. Benedek and B. Moskowitz, “Converter Binary to BCD 
Without Flip-Flops, ’’Electronic Design, Oct. 10, 1968. 

5. John R. Linford, “Binary to BCD Conversion with Complex 
IC Functions,” Computer Design, Sept. 1970. 

6. See ref. 1 , pp 325—326. 


513 



OUCBZO 

Solid State 
Division 


Digital Integrated Circuits 

Application Note 
ICAN-6218 


Gate - Oxide Protection Circuit 

in RCA COS/MOS 

Digital Integrated Circuits 


by R.R. Painter 

One of the most frequently encountered handling and testing 
problems with early MOS devices was failure of the gate 
oxide. Although this problem existed during handling and 
testing of devices prior to their installation in a circuit 
(because normal circuit impedances and voltages make 
damage of this nature less likely), a solution to the problem 
was necessary to reduce failure of MOS devices and inte- 
grated circuits during manufacture, reliability testing, 
shipping, incoming inspection, and assembly by equipment 
designers. 

The breakdown voltage of an MOS gate oxide is generally in 
the order of 70 to 100 volts, and the dc resistance is in the 
order of 10 ^ ohms. In contrast to other semiconductor 
diodes, in which the breakdown can be tested any number of 
times without damage, the MOS gate oxide will be shorted as a 
result of only one voltage excursion to the breakdown limit. 
Because of the extremely high resistance of the gate oxide, 
even a very-low-energy source (such as a static charge) is 
capable of developing this voltage. 

Fig. 1 shows a protection circuit developed by RCA which is 
incorporated in COS/MOS integrated circuits to minimize 
this problem. The results to date have shown that this 
approach is effective in minimizing occurrences of gate-oxide 


failure; when the handling guidance contained in ICAN-6000* 
is followed, the problem is eliminated. 

A value of 200 to 2000 ohms (depending on design and pro- 
cess variations) is used for the input resistor R in Fig. 1. This 
value is chosen, in conjunction with the capacitance of the 
gate and the associated protective diodes, to integrate and 
clamp the device voltages at a safe level. The diagrams 
shown in Fig. 2 demonstrate that the input circuit limits 
extraneous voltages to safe levels for all operating conditions. 
Because of its low RC time constant, this network has no 
noticeable effect on circuit speed. 

Because of the presence of this integral protection circuit, 
the Vj)D power supply should not be turned off while a 
signal from a low-impedance generator is applied at an input 
of a COS/MOS integrated circuit. If the Vj)j) supply is 
turned off while a low-impedance pulse generator is connec- 
ted to an input, the Vqj) line is essentially grounded and a 
positive voltage from the pulse generator is impressed across 
diode D 2 - This voltage of up to 15 volts can cause 
permanent damage to the diode or can burn out the Vqd 
metallization. If any input excursion exceeds +Vj)j) or goes 
below — Vgs, the current through the input diodes should be 
limited to 10 milliamperes for safe operation. 

* “Handling Considerations for MOS Integrated Circuits” 



0| * n + TO p WELL 25V MAX 
D 2 AN0 D 3 = p* TOn SUB 50V 
R = NORMAL p+ DIFFUSION IN n SUB ISOLATION 


Fig. 1 - Gate-oxide protection circuit used in COS/MOS integrated circuits. 


514 


10-73 





ICAN-6218 


V DD PIN V 0D PIN 




INPUT 

PIN 


INPUT 

PIN 


V OXIDE * v OXIDE = VD, ♦ VDj = 25 V ♦ 1 V 
MAX MAX BREAK- OH 

DOWN = 26 V 
n-TYPE UNIT p-TYPE UNIT 


V OXIDE = v OXIDE = VD 1 ♦ VD 1 
MAX MAX ON BREAKDOWN- 
DOWN 

■ 1 V ♦ 25 V * 26 V 
(c) n-TYPE UNIT p-TYPE UNIT 




Fig. 2 - Circuits used to provide: (a) protection between input pin and Vpp pin; 
(b) protection between input pin and ground pin; (c) protection between input 
pin and output pin. 


515 



MM] 

Solid State 
Division 


Digital Integrated Circuits 

Application Note 
ICAN-6224 


Radiation Resistance of the 
COS/MOS CD4000A Series 


by M. N. Vincoff 


Complementary MOS (COS/MOS) integrated circuits 
possess many advantages which recommend their use in 
radiation-susceptible space and military environments. 
Several of the most significant of these advantages are: 
ultra-low standby-power consumption, high noise im- 
munity, 1 extremely high packaging density, and inherently 
high reliability.-^ These advantages, along with the improved 
radiation resistance of the RCA CD4000A series over the 
CD4000 series described in earlier radiation studies, ^ exhibit 
the maturity reached by the MOS technology since 1971 . 

A number of studies of the radiation resistance of 
complementary MOS devices by NASA, the Navy and various 
companies in the space industry have revealed two areas of 
prime concern/**! 5 The first, permanent radiation exposure, 
as experienced in a space environment, causes a shift in 
threshold or switching voltage and a possible increase in 
leakage current, II- The second, transient radiation exposure, 
as experienced in an atomic environment, causes the output- 
voltage levels to respond to a pulse of ionizing radiation; this 
effect could change the state of the logic circuitry and 
require resetting of that circuitry for proper equipment or 
system operation. 

Permanent-Radiation Resistance 

The CD4000 series was resistant to permanent radiation 
levels of 2x 10^ rads (approximately 10^ e/cm^). Now, 
however, RCA CD4000A-series devices without special 
shielding have been found to be resistant to radiation levels 
up to 2 x 10^ rads (approximately 10^ e/cm^), as shown in 
Fig. 1 ? In this figure the change in switching voltage A Vg is 
plotted as a function of dose. The value of av$ was 
calculated from the average value of a Vtn and a Vtp for the 
devices mentioned. The new radiation level of the CD4000A 
series represents a significant improvement over the CD4000 
series. In addition, with minimal shielding (for example, 
1/1 6-inch of aluminum) the CD4000A series can be used in 
application with levels of radiation up to 3 x 10^ rads 
(approximately lO^e/cm^).^ 


V DD = 10 VOLTS, DOSAGE * Co bl 

1 CD4007A* 

2 CD40IIA * 

3 CD40I6A 

4 CD40I3A * 

5 CD400IA* 

6 CD4004A** 

7 CD4007 ** 

8 CD400I ** 


GAMMA SOURCE 


I 


I 


/ 




4000 / CD4000A / 
RIES/ SERIES / 

“ 2 \ 

2. 4 _ * 


/■ 


2XI0 4 2x10 s 

(RADS) 


I I I I 

10'° 10" I0 ,z I0' 5 

(e/cm z ) 

* BIAS APPLIED 100% OF THE TIME 
** BIAS APPLIED 50% OF THE TIME 


I0 14 


92CS-22496 


Fig. 1 — Permanent radiation resistance of CD4000A- and CD4000- 
series devices. 


Transient-Radiation Resistance 

The resistance of the CD4000A series to transient 
radiation is expected to be ten times better than that of the 
CD4000 series, which can withstand pulses of radiation of 
approximately 10*0 rads/s. ^ 

Design Considerations 

The resistance of the CD4000A-series devices to either 
permanent- or transient-radiation exposure can be increased 
by providing either minimal shielding through the design of 
the equipment enclosure containing the devices or by 
locating the devices deep within the equipment in which they 
are used. In any case, the action taken will depend on the 
constraints dictated by the radiation environment imposed 
by the system or program. Each application must be tested 
and the results analyzed with the data in this Note as criteria. 
Test items to be considered are radiation environment, which 


516 




I CAN-6224 


will vary greatly depending on dosage rate; time of exposure; 
amount of normal shielding; distance of the device from the 
radiation source; shielding afforded by the atmosphere; 
power-supply voltage selection; and switching cycles used 
during exposure. For example, consider the effects of 
permanent radiation on two spacecraft in 90-degree orbits at 
600 and 1500 nautical miles from the earth, respectively. 
The dose-depth is determined as shown in the curves of 
Fig. 2. In these curves the dose in rads(Al)/day is plotted as 
a function of the thickness of spacecraft aluminum required 
to shield the devices from trapped electrons and protons.^ 



A I THICKNESS -MILS A t THICKNESS-MILS 

(a) 600-MILE, 90° ORBIT (b) 1500-MILE, 90° ORBIT 


Fig. 2 — Dose-depth curves for trapped electrons and protons in space- 
craft in orbit. 


Conclusion 

The RCA COS/MOS CD4000A series exhibits improved 
radiation resistance over the CD4000 series, and is well suited 
for use in many applications in which permanent and 
transient radiation effects are factors. When stringent 
radiation requirements are imposed, additional shielding can 
be employed to increase the radiation life of COS/MOS 
CD4000A-series devices to any desired level, i.e., to make 
their radiation resistance equivalent to that of bipolar 
devices. 

Custom COS/MOS devices that can resist a radiation level 
of 10^ rads are now being developed by means of an 
aluminum implantation process which requires one 
additional masking step in the production line. 1 1-14 


References 

1. Eaton, S. S., “Noise Immunity of RCA COS/MOS 
Integrated Circuit Logic Gates”, RCA Application Note 
ICAN-6176. 


2. Vincoff, M. N. and Schnable, G. L., “COS/MOS is a 
High-Reliability Technology”, RCA Technical Publica- 
tion ST-61 12. 

3. Ezzard, G., “Radiation Effects on COS/MOS Devices”, 
RCA Application Note ICAN-6604 (covers CD4000 
series). 

4. Brucker, G. J., “COS/MOS Device Sensitivity in Outer- 
Space Radiation Environment”, Report No. X72002, 
Oct. 17, 1973, RCA Astro Electronics Division. 

5. Dennehy, W. J., et al., “Transient Radiation Response in 
Complementary-Symmetry MOS Integrated Circuits”, 
RCA Technical Publication ST4308. 

6. Poch, W. J., and Holmes-Siedle, A. G., “Permanent 
Radiation Effects in COS/MOS Integrated Circuits”, 
RCA Technical Publication ST4174 (covers CD4000 
series). 

7. Schambeck, W., “Radiation Resistance and Typical 
Applications of RCA COS/MOS Circuits in Spacecrafts”, 
Telemetry Journal, June/July 1970 (covers CD4000 
series). 

8. Schambeck, W., “Effects of Ionizing Radiation on 
Low -Threshold C-MOS Integrated Circuits”, DFVLR 
Institute for Satellite Electronics, Oberpfaffen-hofen, W. 
Germany, April 1972 (covers CD4000A series). 

9. Danchenko, V., “Radiation Damage in MOS Integrated 
Circuits, Part I”, Sept. 1971, Goddard Space Flight 
Center, Report X-7 11-71410 (covers CD4000A series). 

10. Poch, W. J., and Holmes-Siedle, A. G., “The Long-Term 
Effects of Radiation on Complementary MOS Logic 
Networks”, IEEE Transactions on Nuclear Science 
NS-17 (6), Dec. 1970 (covers CD4000 series). 

11. Smith, J. M., and Murray, L. A., “Radiation Resistant 
COS/MOS Devices”, RCA Technical Publication 
ST4723. 

12. King, E. E., Nelson, G. P,, and Hughes, H. L., “The 
Effects of Ionizing Radiation on Various COS/MOS 
Integrated Circuit Structures”, IEEE Transaction in 
Nuclear Science, No. 6, pg. 264, Dec. 1972, RCA 
Technical Publication ST-6161. 

13. Peel, John L., et al., “Radiation-Hardened Comple- 
mentary MOS Using Si02 Gate Insulators”, IEEE 
Transactions on Nuclear Science, No. 6, pg. 271, Dec. 
1972. 

14. Schlesier, K. M., et al., “COS/MOS Hardening Tech- 
niques”, IEEE Transactions on Nuclear Science, No. 6, 
pg. 275, Dec. 1972. 

15. Novell, J., “Radiation Test of RCA COS/MOS CD4000A 
Series Logic for IUE Orbit, Types CD4011AK/1 with 
and without shielding, and 1 x 256 RAM”, U. S. Gov’t. 
Spacecraft Data Management Branch, Code 734.1, June 
28, 1973. 


517 



Digital Integrated Circuits 


□GQBZ/D 

Solid State 
Division 


ICAN-6230 


Using the CD4047A in COS/MOS 
Timing Applications 

by J. Paradise 


Many applications exist today for COS/MOS multivi- 
brators— both oscillators and one-shots-in analog and digital 
circuits. The requirements for these applications vary widely 
in such parameters as voltage range, temperature stability, 
power dissipation, drive capability, and external-component 
cost. No design is optimum for all of the above considerations. 
However, the RCA-CD4047A Monostable/Astable Multivi- 
brator fulfills the needs of most applications in this timing 
area. It can function as either an oscillator or one-shot with 
many additional features, and will meet the power dissipation, 
stability, and speed requirements of most COS/MOS systems. 

This Note compares some simpler types of oscillator circuits 
with the CD4047A in both theoretical and actual performance, 
and provides application information on the CD4047A which 
should prove useful to COS/MOS circuit and system designers. 

COS/MOS DISCRETE RC OSCILLATOR 

The simplest type of RC-oscillator is shown in Fig. 1. It 
consists of two inverters (which may be taken from standard 



Fig. 1 — Simplest COS/MOS RC oscillator. 

RCA COS/MOS parts, i.e., CD4007A, CD4001A, CD4011A, 
etc.) and a single resistor and capacitor. The operating wave- 
forms for this circuit are shown in Fig. 2. 

The circuit operates as follows: depending on the output 
levels of inverters A and B, at any instant C will be charging or 
discharging through R. When the waveform at point (2) in the 
circuit passes through the transfer voltage of inverter A, this 
inverter will switch and cause inverter B to switch. Subse- 
quently, the waveform at point (2) would be exponentially 


® n_r 



(D 


L_n 


n_r 

92CS - 2 2663 


Fig. 2 — RC-oscillator operating waveforms. 


increasing or decreasing with discontinuities equal in magnitude 
to Vj)£) during the instant of switching. However, since 
point (2) is protected by a standard input-protection circuit 
common to COS/MOS devices, the waveform is clamped at one 
diode voltage drop above Vj)j) and below (Refer to wave- 
forms in Figs. 2 and A1 ). The calculations for the period of this 
multivibrator circuit are shown in Appendix A; the final 
equation for the period T is 


„ (Vtr)(V DD -Vtr) 

1 — KL in 

(V D D + V D ) 2 


0 ) 


where is the switching or transfer point of the inverter, 

and Vj) is the diode forward voltage drop. 

Equation (1) shows that the period of the multivibrator, T, 
is sensitive to changes in Vj)D, as illustrated by the graph of 
time period, T, vs transfer voltage as a function of in 
Fig. 3. In addition to the strong dependence of actual time 
period on the Vj)j) chosen, the graph also illustrates that, for 
a given Vpj), a full transfer voltage spread of 30 to 70 per cent 
of Vp)D (unit-to-unit worst -case variations) yields a change in 
time period of about 10 per cent from the nominal 50-per-cent 
transfer-voltage percentage values. 

The above analysis is valid only at low frequencies (i.e., less 
than 50 kHz). As the multivibrator frequency approaches this 
value, other considerations must be taken into account: 


518 


2-74 





TIME PERIOD x RC — SECONDS 


ICAN-6230 



92CS-22tll 

Fig. 3 — Discrete RC-oscillator time period as a function of transfer 
voltage. 


Appendix B; the equation for the period. T. for this circuit is 
shown in Eq. 2. 

R s 

When K = r- T is: 

K 

^ (V T R)(V D D-V T R) 

I T=-RCln — — - T 

(V D D + V D)“ 

( K )_ Kiypp^Vp) 

< (K +1) RC ,n tc IV DD + VtrI + 

jK l k1Vdd*v d ) 

^ (K+l) RC '"K [2 V DD - V TR ] +|V DD -V TR -V D 1 

In this form it is easy to see that when K approaches zero, the 
circuit and associated waveforms are equivalent to those of 
Fig. A-l . On the other hand, as K approaches infinity, the vari- 
ation in period as a function of is reduced to zero. This 
result is shown in Fig. 5, where period as a function of trans- 


l v TR-v D l 


> ( 2 ) 


1. The input protection circuit has a Vdd diode with a 
finite resistance and capacitance; the diode will discharge at 
the rate associated with this small time constant. 

2. In the negative direction, there is a diode as well as a 
series protection resistor (1 to 3 kilohms); the time constant of 
this diode is even longer than that of the Vj)£) diode. 

3. The propagation delay of the inverters used is added to 
the time period during each charge and discharge cycle. Since 
the delay is a function of Vpj), small changes in Vqq at high 
frequencies will cause the time period to vary. 

4. There is a finite output impedance associated with the 
inverter which is in series with the external timing resistor. 
Since this output impedance also changes with Vqq, at high 
frequencies where the external resistor becomes small, the 
multivibrator stability decreases with small variations in Vj)£). 

The negative features of the input protection circuit can be 
partially compensated for by the addition of a resistor, R§, in 
series with the input protection circuit, as shown in Fig. 4. 
Although the input inverter A is still clamped at one diode drop 
above Vj)j) or one diode drop below V§§, the waveform at 
point (4) is allowed to swing well above Vpj) and below V^g. 
The larger swing reduces the dependency of transfer-voltage 
variations upon stability; the variable characteristics of the 
input protection circuit and their effect upon stability are 
greatly reduced. An analysis of this circuit is presented in 




Fig. 5 — Discrete RC-oscillator time period as a function of transfer 
voltage. 

fer voltage is plotted for different value of V^d and K, and 
Fig. 6, which shows period as a function of K for different 
values of Variation in period with transfer voltage is 

also reduced as K increases. This variation decreases from 
10 per cent for K = 0 to about 5 per cent as K gets large. 

There are some obvious limitations in the value of Rg that 
can be used. Besides the disadvantages in this circuit if R is to 



Fig. 4 — RC-oscillator with the addition of R$. 


Fig. 6 — Discrete RC-oscillator time period as a function of constant, k. 


519 





ICAN-6230 


be made adjustable, the user must be careful with component 
layout, if Rg is made very large, to take advantage of the im- 
provement in stability. A time constant and phase shift is pro- 
duced by Rg and stray wiring and breadboard capacitance, 
see Fig. 7. This shift creates a switching delay in the circuit which 
changes the time period and, in addition, may cause spurious 
oscillations and glitches in the multivibrator circuit. A reason- 
able value for K would be anywhere from 2 to 10, with maxi- 
mum and minimum values for Rg determined by the above 
considerations. 



STRAY 


92CS-22677 

Fig. 7 — RC-oscillator circuit with stray capacitance. 

COS/MOS INTEGRATED RC OSCILLATORS 

The RCA-CD4047A is an integrated RC oscillator that 
eliminates most of the disadvantages of the discrete circuits 
previously discussed. The primary reason for this improved 
performance is the special input-protection circuit which 
allows the capacitor charging waveform to swing above Vpj) 
and below Vgg without the need for. an external resistor. This 
circuit, shown in Fig. 8, has the same time period and stability 
as the circuit in Fig. 4 for the case where the value of Rg is 
infinite. However, a resistor is eliminated, as well as the dis- 
advantages of a time constant caused by the resistor. 



92CS- 22676 

Fig. 8 — CD4047A oscillator section 


There are two additional reasons for expected improvement 
with the CD4047A. First, the transfer-voltage point of the 
input inverter, A, is tested between 33 and 67 per cent of Vj)j) 
instead of between 30 and 70 per cent; this narrower test range 
improves stability by reducing unit-to-unit variations. In ad- 
dition, large buffers are used for inverters D and E; this practice 
reduces the effect of changes of device output impedance with 
period stability. A derivation of period, T, for this circuit is 
presented in the Appendix C ; the final equation for T becomes : 

( V TR> ( v DD ~ V TR> 

C In ( V DD + V TR) ( 2 V DD - V TR) 


Figure 9 shows a graph of stability as a function of transfer 
voltage based on this equation. 

The graph of Fig. 9 shows a maximum variation of 5 per 
cent between minimum (2.197 RC) and maximum (2.307 RC) 
time periods. A value of 2.25 RC yields a ± 2.5 per-cent vari- 
ation. Typical values of period variations at high frequencies 
and temperature extremes are included in the published data 
for the CD4047A. 1 



30 35 40 45 50 55 60 65 70 

TRANSFER VOLTAGE (Vjr) — PER CENT OF V 0D 


Fig. 9 — CD4047 time period as a function of transfer voltage. 

An additional advantage of the CD4047A is a reduction in 
power dissipation as compared to the discrete multivibrators 
discussed previously. Inverter A in Fig. 8 is designed with high- 
impedance components that limit power dissipation during the 
time that the inverter operates in the middle of its transfer 
region. Four additional inverters are used to gradually shift from 
a very -high-impedance inverter at the input to a very -low- 
impedance driver in series with the external timing resistor. 
Calculations for power dissipation and a comparison of P^s 
for the CD4047A and a discrete oscillator are presented in 
Appendix D; the result is 

p diss =2cv2 f (4) 

This equation specifies the power dissipated in the external 
components only. At low frequencies, where most of the 
power will be dissipated in R, power can be minimized by 
using a small value of C, since the formula shows the power 
is a function of C and not R. 

Additional power is consumed in the CD4047A chip as a 
function of frequency. Fig. 10 shows curves for theoretical 
minimum power dissipation, actual CD4047A oscillator-power 
dissipation, and discrete oscillator-power dissipation as a 
function of frequency. 

CMOS DISCRETE ONE-SHOTS 

Fig. 1 1 illustrates one of several simple monostable circuits 
which can be employed in non-critical timing circuits. 2 The 


520 




_ ICAN-6230 



Fig. 10 - Comparison of P(jj ss for discrete oscillator and CD4047 with 
theory. 



9zcs-2zcr» 


Fig. 12 — Simple one-shot time period as a function of transfer voltage. 


COS/MOS INTEGRATED ONE-SHOTS 

The CD4047A, when used in the monostable mode, again 
has several advantages over discrete designs. A high degree of 
accuracy can be achieved with one time constant, and power 
dissipation is lower than with discrete designs. Fig. 13 shows 
that many functions can be achieved with the CD4047A, in- 
cluding leading and trailing-edge triggering, and retriggering. 

The pulse width, T^, is expressed below: its derivation is 
given in Appendix E. 


T\| RC In 


(V T r) (Vpp) - Vtr) 

(2 V DD) ( 2 V DD “ V TR) 


( 6 ) 



Fig. 14 is a graph of pulse width versus transfer voltage based 
on the above equation. 

The equations for monostable-mode power dissipation are 
also derived in Appendix E. For a repetitive output on the 
CD4047A, power dissipation can be expressed by the following 
equation: 


2. 875 CV DD 2 

p diss = x ( dut y c y cle ) (7) 

t m 


Fig. 11 — COS/MOS monostab/e circuit. 


USING THE CD4047A - SPECIAL CONSIDERATIONS 


circuit pulse width is dependent upon the transfer voltage of 
inverter B as time constant RC charges to Vqd from Vgg. The 
pulse width is defined as 


T = 


-RC In 


(Vpp - v TR ) 

( V DD ) 


(5) 


Fig. 12 shows the variation in pulse width as a function of 
transfer voltage for this device. 

There are several alternatives to the circuit shown in 
Fig. 12.2 These alternatives have the advantage of greater 
stability, but at the expense of two time constants required in 
circuit and, in some cases, the addition of a diode. 


A number of circuit considerations are explained below 
which will aid the user of the CP4047A. 

A clamping circuit is provided on the chip to reduce the 
recovery time (tr) that would normally exist in other mono- 
stable circuits; see Figs. 15 and 16. Fig. 17 shows a plot of 
monostable-pulse-width stability as a function of duty cycle 
for specific R and C external components. Note that there is 
no appreciable change in pulse width until the duty cycle 
approaches 100 per cent. A disadvantage to the clamping circuit is 
that it introduces additional capacitance at the RC common 
node (Fig. 16), which may be noticeable for short pulse widths 
in the monostable mode only. Some diffusion capacitance 
present at the base of the n-p-n transistor is used to quickly 


521 




ICAN-6230 



INPUT- VOLTAGE SWINGS 


Fig. 13 — CD4047A logic diagram. 





Fig. 14 — CD4047A one-sho t pulse width as a function o f transfer voltage. 



Fig. 15 — CD4047A one-shot RC waveform. 


^DIFFUSIONS 

| PIN 3 


I 1 


1 , 

R 

— wv ► 


92CS- 22667 

Fig. 16 — CD4047A damping circuit. 



Fig. 17 — CD4047A monostable accuracy as a function of duty cycle. 


522 







ICAN-6230 


charge C to Vqq after the one-shot cycle has terminated. This 
capacitance is multiplied by the beta of the transistor, and is in 
parallel with the external C during the time interval that the 
transistor ison(Vj)[) - Vgg < t < Vgg). Thus, when values of 
C less than 1000 picofarads are used, the actual width will be 
longer than that predicted by the formula. Fig. 18 is a graph of 
actual, typical pulse widths as a function of external C used 
under these conditions. Note that the minimum values of C 
used in the graph are the smallest that can be used in the 
CD4047A to assure proper operation of the circuit. 

The waveform in Fig. 1 5 shows that two positive transitions 
are encountered by the control circuitry in the CD4047A. 
These transitions are necessary to make the output flip-flop at 
pin 10 toggle properly to produce the single pulse needed in 
monostable operation. However, at pin 13, the waveform of 





Fig. 18 — CD4047A pulse width as a function of capacitance. 

Fig. 19 results; the pulse width of the spike is equivalent to 
the propagation delay of the circuit. This spike will normally 
prevent the user from using pin 13 in the monostable mode. In 
the astable mode, however, pin 13 can be used whenever a 
50-per-cent duty cycle and higher drive capability are not 


r » m 1 92CS * 22661 

Fig. 19 — CD4047 A one-shot output at pin 13. 

required. The advantage to the use of pin 13 under these 
conditions is that the frequency of the waveform at pin 13 is 
twice that of pin 1 0 for the same external timing components. 

When the CD4047A is used in the retrigger mode, the 
retrigger input is connected directly to the set input of FF4, 


as shown in Fig. 13. This connection means that the output at 
pin 10 will be high during the time that a high level is present 
on pin 12. Thus, if normal one-shot operation is required at 
any time that the circuit is in the retrigger mode, the input 
pulse should be shorter than the expected pulse at the output. 
Note that in the retrigger mode the output pulse width is not 
referenced to the last positive-going edge produced at the 
input because of the asynchronous nature of the circuit. The 
output actually terminates when two internal-oscillator leading 
edges have been received by FF4, after the high level present 
on pin 12 has been removed. The output width variation will 
then be between one and two time constants referenced to the 
trailing edge of the input at pin 1 2, see Fig. 20. 


CASE I 
CASE 2 


t pin i2 n n n n 



92CS-22674 


Fig. 20 — CD4047A retrigger-mode waveforms. 


A section on timing-component limitations is presented in 
the CD4047A data sheet. 1 It should be emphasized that it is 
desirable to use a small value of capacitance wherever possible. 
The circuit will work well even when the value of R approaches 
or exceeds 1 megohm. For very low frequencies, where a large 
value of capacitance is needed, the selection of the capacitor is 
very important. It must be nonpolarized because there is no 
reference ground at either of the two pins to which C is con- 
nected. The capacitor parallel resistance (i.e., leakage) must 
also be at least an order of magnitude higher than the external 
R used. This criterion generally eliminates electrolytic ca- 
pacitors and those made of materials which could produce 
greater leakage current than that permitted for proper circuit 
operation. 

Because of the internal circuit construction, there is no 
guarantee as to what dc level will be present on the output at 
pin 10 or 11 when power is first turned on. If this condition 
must be guaranteed, a system-power on pulse input to pin 9 
can be made to assure that pin 10 will initially be at a low logic 
level. The pulse can be generated from one of the circuits 
shown in Fig. 21 . 




Vss 


TO PIN 9 
OF CD4047 


J 


92CS - 2 2669 


Fig. 21 — CD4047A power-up reset circuits. 


523 




ICAN-6230 


Although the CD4047A data sheet calls for a minimum 
input pulse duration of 200 nanoseconds at 10 volts and 500 
nanoseconds at 5 volts, shorter pulses (due to transients, etc.) 
occur frequently in system applications where the CD4047A is 
used. Such narrow pulses may not be ignored by the CD4047A, 
but may instead cause Q to go high permanently or until a reset 
input occurs. The circuit shown in Fig. 22 eliminates this 
problem by essentially “lengthening” the trigger pulse by 
feeding back through and a current pulse when Q goes 
from 0 to a 1 . The particular values shown have been tried and 
found to work well, even for extremely short input pulses 
(less than 20 nanoseconds). 



Ca Ra 

‘ — 1( W 1 

20pF 10 Kn 92CS- 2 3404 

Fig. 22 — Input-pulse stretcher circuit. 


APPLICATIONS 
NOISE DISCRIMINATOR 

Fig. 23 illustrates an application of the CD4047A in a noise- 
discriminator circuit. By adjusting the external time constant, 
a pulse width narrower than that determined by the time 
constant will be rejected by the circuit. The output pulse will 


V,N©J 

0 ©“LJ 


0 out(D_ 



FREQUENCY DISCRIMINATOR 

The CD4047A can be used as a frequency-to-voltage con- 
verter, as shown in Fig. 25. A waveform of varying frequency is 
applied to the +TR input. The one-shot will produce a pulse of 
constant width for each positive transition on the input. The 



o — VW- 




—1— C = 0.0022 a-F 


92CS-22672 

Fig. 25 - Frequency-discriminator circuit. 


resultant pulse train is integrated to produce a waveform whose 
amplitude is proportional to the input frequency. The wave- 
forms of Fig. 26 were taken with the circuit in operation. 



CD4047 INTEGRATOR 

R = 22 k n R = IOOkft 

C = 470 pF C = 0.0022 fiF 92CS-22652 


Fig. 26 — Frequency-discriminator-circuit waveforms. 



Fig. 23 — Noise-discriminator circuit. 


follow the desired input, but the leading edge will be delayed 
by the selected time constant. Fig. 24 shows typical waveforms 
with the circuit in operation. 



LOW-PASS FILTER 

A simple circuit using the CD4047A as a low-pass filter is 
shown in Fig. 27. The time constant chosen for the multi- 
vibrator will determine the upper cutoff frequency for the 
filter. The circuit essentially compares the input frequency 



92CS-2267I 


Fig. 27 — Low-pass filter circuit. 


with its own reference, and produces an output which follows 
the input for frequencies less than f cu toff an d a low output 
for frequencies greater than f cu t 0 ff* 28 and 29 show 
waveforms with the low-pass filter circuit in operation. 

BANDPASS FILTER 

Two CD4047A low-pass filters can be employed to con- 
struct a bandpass filter, as illustrated by the circuit in Fig. 30. 


524 








ICAN-6230 


The pass band is determined by the time constants of the two 
filters. If the output of filter No. 2 is delayed by Cj, the 
CD4013A flip-flop will clock high only when the cutoff fre- 
quency of filter No. 2 has been exceeded; this point is illus- 
trated in the timing diagram in Fig. 30. The Q output of the 
CD4013A is gated with the output of filter No. 1 to produce 



500 /is/DIV 


T CD4047 =50/*s 
R = 22 k ft 
C = 0.001 


92CS-2265I 


Fig. 28 — Low-pass filter-circuit waveforms. 


the desired output. Typical operation of the circuit is shown in 
Fig. 31, where the input frequency is swept through the pass 
band. 



200 /is/DIV 

T FILTER I = 50^s TpiLTER 2 s| 00 M s 

R * 22 k R =47 k 

C = 1000 pF C = 1000 pF 

92CS - 22649 

Fig. 31 — Bandpass-filter-circuit waveforms. 



200 M s/DIV 


t CD 4047 =50 m s 
R = 22 k 
C =0.001 


92CS- 22650 


Fig. 29 — Low-pass-circuit waveforms. 





«... 

oi Juuuuuuuuuuinnn^ 
“jinnnrn ^nnnnni — 

DELAY I —I 

CD40I3 0 | | 


~L 


_njuuuL 


_r 


Fig. 30 - Bandpass filter circuit and waveforms. 


ENVELOPE DETECTOR 

The CD4047A can be used as an envelope detector by 
employing it in the retrigger mode, as shown in Fig. 32. The 
time constant is selected so that the circuit will retrigger at the 


V|N 

o- 


V 0 UT 

-O 


92CS- 22670 


Fig. 32 — Envelope-detector circuit. 

frequency of the input pulse burst. A dc level appears at the 
output for the duration of the input pulse train. Fig. 33 shows 
waveforms taken with the circuit in operation. 



500 fis/OIV 


T CD4047 1 120 /is 
R = 56 k 
C = 1000 pF 


92CS- 22648 


Fig. 33 — Envelope-detector-circuit waveforms. 


PULSE GENERATOR 

Several CD4047A units can be connected together to pro- 
duce a general-purpose laboratory pulse generator, as shown in 
Fig. 34. The circuit shown has variable-frequency and pulse- 
width control, as well as gating and delayed sync capability. 


525 









ICAN-6230 



Gating can be controlled from a high- or low-level input. 
Automatic 50-per-cent duty-cycle capability is included, as 
normal or inverted output. 

CD4047A No. 1 is connected as a gated, astable multi- 
vibrator, and, with the RG values shown, can produce over- 
lapping ranges of frequencies from 2 Hz to 1 MHz. For free- 
running operation, the Gate/Free-Run switch is closed, and 
the Gate Level switch is placed in the high-level position. 
Standby operation can be achieved with the Gate Level 
switch in the low-level position. When gating, the Gate/Free- 
Run switch is open, and the Gate Level switch is set to the 
appropriate position. The gate signal is applied to the Gate In 
jack. 

CD4047A No. 2 is triggered from the gated, astable multi- 
vibrator, and produces a narrow sync pulse which can trigger an 
oscilloscope or generator. The sync pulse is obtained from the 
Sync Out jack. 

If a 50-per-cent duty cycle is desired, the Duty Cycle switch 
is set in the 50-per-cent position, and the output is obtained 
from CD4047A No^ 1 . The Signal Polarity switch determines 
whether the Q and Q output is used. 

CD4047A No. 3 produces a variable, delayed (from 1.5 
microseconds to 250 milliseconds) output with respect to the 
sync pulse when the Delay switch is in the IN position. This 


one-shot is bypassed when the Delay switch is in the OUT 
position (the inherent delay is approximately 400 nanoseconds). 

CD4047A No. 4 is a monostable multivibrator which re- 
ceives trigger pulses from CD4047A No. 1 or No. 3. It can 
produce overlapping ranges of pulse widths from 1.5 micro- 
seconds to 200 milliseconds with the values shown. 

The signal output is buffered with the CD4041A to 
allow the pulse generator to drive any required load. The 
circuit shown has the advantages of being compact, battery- 
powered, and COS/MOS compatible. In addition, it is capable 
of being run from the same power supply as the device under 
test to assure that the input levels are the same as Vj)j) when 
the power-supply voltage is varied. 

MISCELLANEOUS APPLICATIONS 

The basic properties of good stability in the astable mode, 
and stable pulse delay and width control in the monostable 
mode, make the CD4047A a useful building block in many 
systems, such as PMOS clock generation, audio tone gener- 
ation, semiconductor memory systems, semiconductor memory 
exercisers, and general-purpose functional-testing systems. This 
Application Note will serve as a guideline in incorporating the 
CD4047A in a system design. 


526 









Appendix A — 

Calculation of the Period of an Astable Multivibrator Using a Single RC Time Constant 


I CAN-6230 



92CS-22657 

Fig. A-1 — RC oscillator waveform for the circuit of Fig. 1. 


In Fig. A-1 : 

1 1 : V TR = (Vd D + V d ) e'* 1 ^ RC 


l \ 


= -RC In 


V TR 

V DD + V D 


l 2 : V DD “ V TR = ( V DD + V D> e 


-t 2 /RC 


t 2 - RC In 


VpD ~ V TR 
V DD + V D 


And the period of an astable multivibrator using a single RC 
time constant is: 


T = 


j + t 2 = — RC In 


(V T r) (Vpp - Vtr) 
(V DD + V d )2 


Appendix B — 

Analysis of Circuit Shown in Fig. 4 



Fig. B-1 - RC waveform for the circuit of Fig. 4. 


In Fig. B-1 : 


tj: v tr = ( v dd + v D> e 
V TR 

t r 


-tj/RC 


ti = -RC In ; 


V DD + V D 
l 2 : V DD ~ V TR = ( V DD + V D> e _t 2/ RC 
V DD ~ V TR 


t 2 = — RC In 


V DD + V D 


527 


ICAN-6230 


tA 


v OD +v TR 


V D 

-o 


92CS- 22665 

Fig. B-2 - Initial conditions for solving period t A . 


Eq. (B-l) is solved for V- the final voltage across the 
capacitor is 


v-c, 


e- K l'A 


k 2 

+ 

K, 


(B-2) 


where Cj - Vj R = initial voltage across capacitor 


Kj = — — 

1 R s RC 


k 2 = 


Vp R ~ R S V DD 
R S R C 


Circuit initial conditions are shown in Fig. B-2. In the 
figure 


By inserting these values into Eq. (B-2) and setting the 
final voltage across the capacitor, V, to Vp, t^ becomes 


c dv V + Vpp ( V + Vpp ~ (Vpp + Vp) 

L dt " R R s 


(B-l) 



R S l V PP + V P] 

R S l V PP + V TR] + R l v TR ~ Vp] 



RS V-rD-Vnn - 

-VDO WV V - - | ( O v ss 


Insertion of these values into Eq. (B-4), with 
V = — Vj) yields 

R s RC r sI v pp + v p1 

* . R S + R . R sl- v PP v TRl + R l v PP - V TR ~ v p] 

and T = tj + *2 + *A + *B 


Fig. B-3 — Initial conditions for solving period tg. 


Circuit initial conditions as shown in Fig. B-3. In the 
figure 


dv Vj)D — V V D + V 
C dt ” R ~ R s 


(B-3) 


Solving Eq. (B-3) for V the final voltage across the 
capacitor, yields 


V = C 2 e 


-K ltB 


K -2 

R 1 


(B-4) 


The equations for t^, tg, and T can be simplified by 
expressing Rg as a multiple of R. Let 
R S 

K = — and combining the expressions for tj and t 2 . The 
R 

resulting expression for T is 

(V T r) (V dd - V tr ) 

T = -RC In r 

(Vpp + V D ) 2 



K [Vpp + v p] 

K [Vpp + V TR ] + [V TR - V D ] 


where C 2 = Vj R — Vj)j) = initial voltage across capacitor 
Kq , K 2 are same values as for above for t^. 


K \ K[V dd + V d ] _ 

K+l/ RC ' n K [2 V DD - V TR ] + (V DD _ V TR - V D ] 


528 



ICAN-6230 


Appendix C — 

Calculation for Period of Astable Multivibrator Using Integrated Techniques 



92CS - 22656 

Fig. C-1 — CD4047A RC oscillator waveform. 


In Fig. C-1 


1 1 ’ V TR = ( V DD + V VTR) e l ^ RC 


t j = RC In 


V TR 

V DD + V TR 


l 2 : V DD~ V TR = ( V DD + v TR) e 


t 2 = — RC In 


V DD- V TR 
2 V DD - V TR 


And the period of the astable multivibrator using integrated 
techniques is 

T = -RCln^™ )(V P D ~ VTR) 

(Vdd + V T r)(2 V dd — V TR ) 


Appendix 0 — 

Power Needed for Charge and Discharge of an External Capacitor During One Cycle 



c 

92CS-22655 

Fig. D-1 — Waveform for calculating power dissipation. 


= '— f 

(T/2) J q 

■“f (■ 

l 


CVdv 

dt 


5 V DD e -I/RC) 

(rc ) 0 ' 5 V »D ,e “ t/RCdt 


4.5C Vpp 2 
T RC 


RC/ 
e — 2t/RC dt 


- 2 25C V DD~ e -2t/RC 

T 


Assume for this calculation that Vj R = 50-per-cent Vpj), 
and that T = 2.2 RC. Since charge and discharge cycles are 

symmetrical, the calculation can be performed by analyzing Substituting T = 2.2 RC 
a discharge cycle only. See Fig. D-I. 


T/2 


V= 1.5 V^e-t/RC 


JT = - (i^) (I ' 5V DDj(^ t/RC ) 


P=-y (2.25)V dd 2 [e 


P = 2 CV 2 f 


-2.2_1] = 20 |v dd 2 


529 



ICAN-6230 


Appendix E — 

Equations for Pulse Width Tjy| of CD4047A in Monostable Mode 



Fig. E-t — CD4047A RC waveform, monostable mode. 


*1 • ^TR = 2 Vdd e 


tl = 


-RC In 


VTR 
2 V DD 


l 2 : V DD ~ V TR = (2 V DD ~ V TR> e t2/RC 


i 2 = 


— RC In 


Ypp-VlR 
2 Vpp - V TR 


And the equation for the pulse width, T^, of a CD4047A in 
the monostable mode is: 


Note that the waveform in Fig. E-l is not symmetrical because 
the timing capacitor is initially charged to Vpp. In the 
monostable mode, the circuit goes through one cycle only. 


T M = t l +t 2 = 


R cl (V tr > (Vpp ~ Vtr) 

n ( 2 VDD) ( 2 V DD “ V TR) 


Monostable Power Dissipation 

To calculate the power dissipation for the circuit in the 
monostable mode, refer to Fig. E-l . If it is assumed that 
Vjr = 50-per-cent Vpp, Fig. 14 shows that = 2.485 RC. 
tj is the same as in the astable calculation, i.e., t 2 = 1 .10 RC 
and P t 2 = CV 2 f for Vj R = 50-per-cent Vpp. Thus, tj in the 
monostable mode = 2.485 RC —1.10 RC = 1 .385 RC. 



Pt l = ~ J ( 2 v dd c ~' /RC )(^) (2 V dd e t/RC )it 

= — 4 V dd 2 f' 1 e -2t/RC dt 
T M RC J 


2V dd 2 e-2*/RC 
Substituting tj = 1.385 RC 
P tl = -^ 2 Vdd 2 [e-2-77 


<1 

o 


1] 


1.875 C Vdd 2 
t M 


where V = 2 Vpp e and 

d7'" ( _ Rc) (2VDD,e_t/RC 


p = p tl + p t2 = ( 1875+ O' 


C Vdd 2 
t M 


= 2.875 


C Vdd 2 
t M 


For a repetitive output from the CD4047A 
2.875 C Vdd 2 

p _ x duty cycle 

t M 


REFERENCES 

"CD4047A COS/MOS Low-Power Monostable/ Astable 
Multivibrator," RCA Data Bulletin, File No. 623 

"Astable and Monostable Oscillators Using RCA COS/MOS 
Digital Integrated Circuits," by J. A. Dean and J. P. Rupley, 
RCA Application Note ICAN-6267 


ACKNOWLEDGMENTS 

The assistance of R. Vaccarella in the designing of some of 
the application circuits shown and in obtaining laboratory 
measurements used in plotting the curves shown in this Note is 
acknowledged. 


530 




Solid State 
Division 


Digital Integrated Circuits 

Application Note 
ICAN-6267 


Astable and Monostable Oscillators 
Using RCA COS/MOS 

Digital integrated Circuits 

by J. A. Dean and J. P. Rupley 


COS/MOS integrated logic circuits are being widely used in 
digital and other applications because of their inherent 
advantages of high noise immunity, extremely low power 
dissipation, and tolerance to wide variations in power-supply 
voltages and operating-temperature ranges. In addition to 
these features, COS/MOS gates and inverters can provide cost 
and size reductions in multivibrator circuits because their high 
input impedance makes it possible to obtain large time con- 
stants without the use of large capacitors. This Note describes 
several techniques which may be used to compensate for the 
normal threshold variation of MOS devices in the design of 
stable multivibrator circuits for operation at frequencies up 
to 1 MHz. The circuits shown can be formed by use of 
COS/MOS inverters and NAND or NOR gates connected in an 
inverter configuration. NAND and NOR gates perform the 
inverter function when all of the gate inputs are tied together. 
This Note also describes various applications for COS/MOS 
multivibrator circuits, (i.e., voltage-controlled oscillators, 
voltage controlled-pulse-width circuits, phased-locked voltage 
controlled oscillators, frequency multipliers, and modulator/ 
demodulator (envelope detectors). (Note: COS/MOS Hex 
Buffers CD4009A and CD4049A and Quad Buffer CD4041 A 
are not recommended for use as multivibrators because of the 
very high power consumption in the linear mode for long 
time constants. In addition, the Hex Buffers have large im- 
balance between source and sink current capability which 
makes oscillator start-up more unpredictable. The COS/MOS 
General-Purpose Hex Inverter CD4069B is recommended for 
use in the multivibrator applications illustrated in this Note. 
The CD4069B is well adapted to MV applications, having 
balanced output drive capability of ±0.4 milliampere for 5 V 
operation at an output voltage level of ±0.4 volt. Specific data 
in this Note relate to the use of “A” series gates as shown; 
performance using the CD4069B may differ slightly from the 
data shown herein. 

ASTABLE CIRCUITS 

Fig. 1(a) shows an astable multivibrator circuit that uses two 
COS/MOS inverters, and Fig. 1(b) shows the related wave- 
forms. This simple circuit requires only two resistors and one 
capacitor, and operates in the following manner. When the 
waveform 1 at the output of inverter B is in a high or “one” 
state, capacitor C tc becomes charged positive. As a result, the 
input to inverter A is high and its output is low or “zero”. 
Resistor R tc is returned to the output of inverter A to 
provide a path to ground for discharge of capacitor C tc . 


As long as the output of A is low, the output of inverter B is 
high. As capacitor C tc discharges, however, the voltage 
generated [waveform 2 in Fig. 1(b)] approaches and passes 
through the transfer voltage point of inverter A. At the 
instant that this crossover occurs, the output of A becomes 
high; as a result, the output of B becomes low and the 
capacitor C tc is charged negative (or low). The resistor R^ c 
connected to the output of A then provides a charge path to 
a supply voltage. Capacitor C tc begins to charge to this 
voltage, and again the voltage approaches and passes through 
the transfer voltage point of inverter A. At that instant, the 
circuit again changes state (the output of A becomes low and 
that of B high) and the cycle repeats. 

Because of the input-diode protection circuits included in the 
COS/MOS IC, shown in Fig. 2, the generated drive waveform 
VdD 



Fig. 1 - Circuit diagram and voltage waveforms for astable 

multivibrator circuit that uses two COS/MOS inverters. 


11-73 


531 





ICAN-6267 


is clamped between Vqd and ^SS- Consequently, the time 
to complete one cycle is approximately 1.4 times the RC 
time constant because one time constant is used to control 
the switching of both states of the multivibrator circuit. 
Resistor Rx (Fig. 1) limits the current through D1 (Fig.2) 
to a safe level. Switching occurs when the charge or dis- 
charge reaches the transfer voltage level, or when the time, 
period reaches 70.7 per cent of its discharge. As shown in 
waveform 2 of Fig. 1(b), the transfer voltage point Vt r is the 
same for ti and t2. The time period T for one cycle can be 
computed as follows: 



92CS- 22871 

Fig. 2 - Diode protection circuit. 


If the time constant is assumed to be 1 x 10'^ second and the 
transfer voltage V tr is allowed to vary from 33 to 67 per cent 
of V[)j),the period T varies from 1 .4 microseconds at a value 
of V tr equal to half of Vj)D to 1 -5 microseconds at either 
the 33 or 67 per cent value of VdD- Therefore, the maximum 
variation in the time period T is only 9 per cent with a 
±33-per-cent variation in transfer voltage from unit to unit. 

The oscillator can be made independent of supply-voltage 
variations by use of a large resistance in series with the input 
lead to inverter A, shown in Fig.3(a). This resistor Rs should be 
at least twice as large as the resistor R tc of the time constant 
to allow the voltage waveform generated at the junction of 
Rs> R tc> and C tc to rise to Vqd + v tr . The waveform is 
still clamped at the input between Vj)D and Vgg, as shown 
hy the waveforms in Fig. 3(b). The use of resistor R s 


provides several advantages in the circuit. First, because the 
RC time constant controls the frequency, the over-all 
maximum variations in the time period are reduced to less 
than 5 per cent with variations in transfer voltage, as 
determined by the following equation: 

r Vtr (VDD-Vtr) 1 

T = -RC [ ln ( v DD + v te ) +1 " 2V DD - V tr J (2) 

The resistor Rg also makes the frequency independent of 
supply-voltage variations. Table I shows data measured on 
typical units with and without the resistor 


vdd 



92CS- 22870 





® L_n_n_ 

(b) 


Fig. 3 - Addition of resistor in series with input to one 
COS/MOS inverter to make oscillator circuit independent of 
supply-voltage variations: (a) circuit diagram; (b) voltage 
waveforms. 

Fig. 4 shows a typical transfer characteristic as a function of 
temperature. It can be seen that there is very little change in 
the characteristic from low to high temperature. Because the 
oscillator can also tolerate changes in the transfer charac- 
teristic without frequency instability, it requires no thermal 
compensation. The frequency at -55°C is the same as at 
+125°C. Table II shows data measured on typical units at 
temperature extremes. 


532 



I CAN-6267 


Table I - Frequency variations of astable multivibrator with and without series resistor. 



Fig. 4 - Transfer characteristic as a function of temperature. 


The astable multivibrator shown in Fig.l can be gated on 
the off by use of a NOR gate as the first inverter, as shown 
in Fig.5. 


® rnmmj 


Table II - Frequency variations of astable multivibrator 
at temperature extremes. 


Unit No. 

Period - (ms) j 

V DD 

= 6V 

V DD 

= 10V 

V DD 

= 14V 

-55°C 

+125°C 

-55°C 

+125°C 

-55°C 

+125°C 

2 

1.04 

1.04 

1.02 

1.01 

1.03 

1.02 

6 

1.06 

1.07 

1.06 

1.04 

1.04 

1.03 

11 

1.03 

1.03 

1.04 

1.02 

1.04 

1.01 

13 

1.02 

1.02 

1.02 

1.02 

1.03 

1.01 

20 

1.04 

1.03 

1.04 

1.03 

1.04 

1.02 


R tc - 0.4 megohm, C tc =1000pF, R s =0.8 megohm 


• LITLITLril 


Fig. 6 - Waveforms showning effects of transfer voltage on 
multivibrator frequency. 

occurs at the 50-per-cent point. However, the duty cycle can 
be controlled if part of the resistance in the RC time 
constant is shunted out with a diode, as shown in Fig. 7. 
Because adjustment of this diode shunt to obtain a specific 
pulse duty factor causes the frequency of the circuit to vary, 
a frequency control R 3 is added to compensate for this 
variation. It may also be necessary to. re verse the diode to 
obtain the desired duty factor. The frequency of any of the 
circuits shown can be made variable by use of a potenti- 
ometer for resistor R tc . 


533 












I CAN-6267 



Fig. 7 - Astable multivibrator in which a duty-cycle control 
is added. 


MONOSTABLE CIRCUITS 

Basic Configuration. Fig. 8(a) shows a basic “one-shot” 
circuit that uses a single RC time constant. This circuit 
operates well provided it is adjusted to the particular 
COS/MOS unit used. If no adjustment is made, however, the 
period T can vary from unit to unit by as much as 40 per 
cent to +60 per cent if the transfer voltage varies by ±33 
per cent, as shown by the waveforms in Fig. 8(b). 



0 

0 

0 

© 


JT 


UZT 



H L— variation in 

I TIME PERIOD 


(b) 


Fig. 8 - Basic one-shot multivibrator circuit: (a) circuit 
diagram; (b) waveforms. 


Compensated Monostable Circuit. Fig. 9 shows a compen- 
sated monostable multivibrator type of circuit that can be 
triggered with a negative-going pulse (Vqd to ground). In the 
quiescent state, the input to inverter A is high and the output 
low; therefore, the output of inverter B is high. When a 
negative-going pulse or spike is introduced into the circuit, as 



snown in the waveforms of Fig. 10, capacitor Cj becomes 
negatively charged to ground and the output of inverter A 
becomes high. Capacitor C 2 then charges to Vqd through 
the diode Dj and inverter A, and the output of inverter B 
becomes low. As capacitor Cj discharges negatively, it 
charges through resistor Rj to Vdd (waveform 2). The 
output of inverter A remains high until the voltage waveform 
generated by the charge of Cj passes through the transfer 
voltage of inverter A; at that instant its output becomes low. 
Diode Dj temporarily prevents the discharge of capacitor C 2 , 
which was charged when inverter A was high (waveform 3). 
Capacitor C 2 then commences to discharge to ground 
through resistor R 2 (waveform 4). The output of inverter B 
remains low until the waveform generated by the discharge 
of C 2 passes through the transfer voltage point of inverter B; 
at that point the output returns to its high state (waveform 

5)- 


^ HIGH j ^ 


HIGH 1 


CD 

LOW L-—- 

HIGH 1 

® LOW—J 

I^^TRANSFER VOLTAGE POINT- INVERTER A 

~i 

HIGH j 

! TRANSFER VOLTAGE POINT- INVERTER B 

© 

LOW • 

1 


Fig. 10 - Voltage waveforms for monostable multivibrator 
circuit when a negative-going trigger pulse is applied. 


The advantage of using two gates connected as inverters fab- 
ricated on the same chip is that they have sinfilar transfer 
voltages. When two equal RC time constants are used 
(RjCj equals R 2 C 2 ), the effects of variations in transfer 
voltage from device to device are effectively cancelled out, 
as shown in Fig.ll. By use of Eq.(l) derived for the as- 
table oscillator, it can be shown that the maximum varia- 
tion in the time period T is less than 9 per cent. The total 
time for one period Tj is approximately 1.4 times the 
RlCj time constant. 

Unlike the astable circuit, which shows no variation in 
frequency over the temperature range from-55°C to +125°C, 


534 



ICAN-6267 


© j\ 




Fig. 11 - Waveforms showing the cancelling effects of 
transfer-voltage variations of the two COS/MOS inverters 
when two equal time constants are used. 

the monostable multivibrator shows some change in time 
period. The variation is less than 10 per cent. Table III shows 
data measured on five units over the temperature range. At 
25°C, the variation in the time period T from unit to unit is 
quite small, usually less than 5 per cent at a Vj)£) of 10 volts. 


92CS- 22876 


© _n_ 


| ^^^ fc^Vtr‘67% OF V DD 



-V fr -33%OF V DD 
OUTPUT 


V, r *67% OF V DD 
^Vtr-33% OF Voq 


The output from inverter B can be held in the low or zero 
state as long as the R 2 C 2 time constant is recharged by 
another triggering pulse before the discharge waveform it 
generates passes through the transfer voltage of inverter B. 


(b) 

Fig. 12 - Monostable multivibrator that is triggered by a 
negative-going input pulse: (a) circuit diagram; (b) 
waveforms. 


Table III - Frequency variations of monostable multi- 
vibrator at three temperatures. 


Unit No. 

Period© V DD = 10V - (ms) 

-55°C 

+25°C 

+125°C 

2 

1.06 

1.08 

1.00 

6 

1.015 

1.03 

0.99 

11 

1.00 

1.02 

0.98 

13 

1.01 

1.03 

0.97 

20 

1.02 

1.02 

0.99 


Rj = R 2 = 1 megohm, Cj = C 2 = O.OOImF 


Diode D 2 in Fig. 9 is internal to the COS/MOS circuit. As 
discussed for the astable oscillator, it is part of the input 
protection circuit shown in Fig. 2, and serves to clamp the 
input at V£)j). 

Figs. 12 and 13 show two variations of the monostable 
circuit, together with their associated waveforms. The circuit 
of Fig. 12 triggers on the negative-going excursions of the 
input pulse, in the same manner as the circuit of Fig. 9. The 
output pulse is positive-going and is taken from the first 
inverter. This circuit does not need an external diode. The 
circuit of Fig. 13 triggers on the positive-going excursion of 
the input pulse, and then locks back on itself until the RC 
time constants complete their discharge. The circuits of Figs. 
12 and 13 cannot be retriggered until they return to their 
quiescent states. 



(b) 

Fig. 13 - Monostable multivibrator that is triggered by a 
positive-going input pulse: (a) circuit diagram; (b) 
waveforms. 


535 




ICAN-6267 


Low-Power Monostable Circuit. The monostable circuits 
discussed thus far dissipate some power because one or both 
of the inverters are on during the charging or discharging of 
the RC time constants. This power . dissipation will be 
extremely low provided the “one-shot” pulse width is short 
compared to the over-all cycle time. Fig. 14 shows the 
current waveform associated with the circuit of Fig. 9. This 



Fig. 14 - Current waveforms for the diode-compensated 
multivibrator shown in Fig. 9. 


waveform is quite wide at the base, and some current flows 
for approximately twice the time period. Fig. 1 5(a) shows a 
circuit using the CD4007A which dissipates much less 
power than the other circuits shown, but does not have 
the same stability. This circuit operates as shown by the 
waveforms in Fig. 15(b). In the quiescent state, the p-channel 
transistor of the first inverter is biased off, while the 
n-channel transistor (which derives its control from the 
output of the second inverter) is biased on. Therefore, the 
output at C is low, and that at D is high. When a 
negative-going pulse is introduced into the circuit through 
capacitor Cj, the RjCj time constant becomes negatively 
charged, and the p-channel device is turned on. Capacitor C 2 
then charges to the output at D becomes low, and 

the n-channel device of the first inverter is turned off. 
Capacitor Cj immediately begins to charge to Vj)j) through 
Rj (waveform B). The p-channel transistor remains on, 
keeping capacitor C 2 charged to until the waveform 

generated passes through its threshold voltage level and turns 
it off. The n-channel transistor of the first inverter is still off 
because the output of the second inverter (waveform D) is 
still low. When the p-channel device of the first inverter turns 
off, capacitor C 2 begins to discharge through resistor R 2 
(waveform C) to ground. As it discharges, it passes through 
the threshold voltage of the second p-channel transistor so 
that it begins to turn on. The voltage waveform at D then 
begins to rise, and the n-channel device of the first inverter 
turns on and provides a second discharge path for the 
capacitor C 2 . As a result, the output waveform changes state 
from low to high quite rapidly to complete the cycle. 


The major advantage of the circuit of Fig. 15 is its low power 
dissipation. Because the circuit depends on the p-channel 
transistor threshold, the time period T varies from unit to 
unit or with temperature variations. Some compensation can 






THRESHOLD 

VOLTAGE 


I mA. 

© 


A. 


CURRENT 


lb) 

Fig. 15 - Low-power monostable multivibrator : (a) circuit 
diagram; (b) waveforms. 


be provided if the R 2 C 2 ^ me constant is niade approxi- 
mately 3 times larger than the Rj Cj time constant, as 
shown in Table IV. 

Table IV - Frequency variations of monostable multi- 
vibrator with temperature when R2^2 time constant is 
increased. 


Unit No. 

Period with V DD = 10V - Ous) 

•55°C 

+25°C 

+125°C 

553 

1090 

1120 

1160 

554 

1060 

1090 

1120 

810 

1030. 

1030 

1020 

900 

1000 

1020 

990 

939 

1080 

1100 

1050 


Rj =0.35 megohm, Cj = 0.001/n.F 

R 2 = 1 megohm, C 2 = 0.001/xF 

R 2 C 2 is approximately 3 times the time constant RjCj 

R 3 = 4700 ohms 


536 




ICAIM-6267 


For minimum current in the circuit of Fig. 15, capacitor C 2 
can be removed so that only stray capacitance is present at 
the input of the second inverter. A comparison of time- 
period variations under this condition is shown in Table V. 
Again, the variations from unit to unit are caused by 
differences in p-channel transistor threshold. 


Table V • Frequency variations of monostable multivibrator 
with temperature when C 2 consists of stray capacitance only. 


Unit No. 

Period 

with V DD = 10V - (ms) 

•55°C 

+25°C 

♦125°C 

SS3 

870 

940 

1020 

554 

900 

970 

1050 

810 

900 

1000 

1080 

900 

810 

880 

960 

939 

780 

1 850 

920 


Rj =0.62 megohm, Cj = 0.001 mF 
R 2 = 1 megohm, C 2 = strays 


Applications 

Fig. 16 shows a circuit similar to the circuit in Fig. 3a. 
Ct c is variable (by adjustment of C x ) and Rt c is variable (by 
adjustment of Va)- The value of Rtc varies from lk£2 to 
10kf2. These limits are determined by the parallel combina- 
tion of R1 (10k£2) and the n-channel device resistance. This 
varies from lk£2 (Ron) t0 % lO^ft (RoFF)- 

When Va = Vss> the n-channel device is “OFF” and 
R tc - ROFF/ /Rl ~ R1 = 10kf2 

because RqFF ^ Rl. 


When Va = Vdd> the n-channel device is fully “ON., and 

Rtc = Ron / /Rl ~ Ron = ikft 


because RqN ^ Rl- 



NOTE: 


CD4007A 



OUTPUT 


92CS- 22878 


INVERTERS AND n- CHANNEL DEVICE ARE AVAILABLE IN 
A SINGLE COS/MOS PACKARF ; 

CD4007A* 

TYPICAL VALUES: 

R, = 10 kft C x = O.OOI - 0.004 /aF 
R s = 100 k ft 0 < V A < v 0D 

K USE PROPER SUFFIX TO DENOTE PACKAGE 
REQUIRED - SEE APPENDIX 


Fig. 16— Voltage-controlled oscillator. 


The oscillator center frequency is varied by adjustment 
of C x . Table VI shows a comparison of the period of the 
output waveform as a function of V^D an£ l V A- 


Table VI - Period of Output as a function of Va and Vqq ' 
V.C.O. of Fig. 16. 


Period Ip sec > < 

Va 

Vqd *5V 

V 0 D * 10V 

Vdd - 15V 

0 

120 

54 

48 

5 

115 

45 

41 

10 

— 

32 

30 

15 

~ 

— 

24 


Voltage-Controlled Pulse-Width Circuit 

Fig. 17a shows a further modification of the circuit of 
Fig. 3a which modulates the pulse width (by varying Va) 
only if R x is sufficiently high. As an example; if C = 
0.0022/iF, then R x ~ 35kf2. Lower values of R x cause the 
frequency to be affected. If R x < 10k£2, there is a value of 
Va which will cause the oscillator to cut off. Table VII lists 
values of pulse width (B in Fig. 1 7b) for various values of Va 
and VqD- Pig- 17b shows the output waveform for the 
circuit described. 






(a) 



I CD4007A 
R tc • 10 kn 
R $ • IOO nn 
R x • 35 nn 

C te * 0.0005 - 0.0025 /iF 


92CS-22882 



(b) 

Fig. 17- (a) V.C. pulse-width circuit; (b) output waveform. 


Table VII- Pulse Width as a Function of Va and Vqd- 


Va 

Pulse Width (B) psec J 

Vdd = 5V 
Period -41. 5 

v D d = iov 

Period-35 

Vdd = 15V 
Period-33 

0 

23 

19.3 

17 

5 

20 

17.7 

16.2 

10 

— 

16.2 

15.5 

15 

— 

— 

14.3 

C tc = 0.001 5pF 


Phase Locked VCO 

The voltage controlled oscillator can be operated as a 
phase locked oscillator by the application of a frequency 
controlled voltage to the gate of the n-channel device. Fig. 18 
shows the block diagram an FM discriminator using the phase 
locked VCO. Block A is the same circuit as Fig. 16. The 
output of the phase comparator is fed to the gate of the 
n-channel device (Va). If the two inputs to the phase 
comparator are different, the change of Va causes the 
output frequency of the VCO to change. This change is 
divided by 2^ and fed back to the phase comparator. 



Fig. 18 — VCO used in phase-locked loop. 


537 









ICAN-6267 


Frequency Multipliers 

Fig. 19a shows a frequency doubler. A 2N multiplier can 
be realized by cascading this circuit with N-l other identical 
circuits. The leading edge of the input signal is differentiated 
by R1 and Cl, applied to the input No. 1 of the NAND gate, 
and produces a pulse at the output. The trailing edge of the 
input pulse, after having been inverted, is differentiated, 
applied to the input No. 2 of the NAND gate, and produces 
the second output pulse from the NAND gate. The 
waveforms for 5 points in the circuit are shown in Fig. 19b. 





Fig. 19 - (a) Frequency doubler schematic; (b) waveforms. 


Modulation/Demodulation (Envelope Detection). 

Pulse modulation may be accomplished by use of the 
circuit shown in Fig. 20a. This circuit is a variation of Fig. 3. 
The oscillator is gated ON or OFF by the signal input No. 1 
to the NAND gate. The waveforms are shown in Fig. 20b. 


Demodulation or envelope detection of pulse modulated 
waves is performed by the circuit shown in Fig. 21a. The 
carrier burst is inverted (by Inverter A), and its first negative 
transition at point 2, turns on the diode (D) to provide a 
charging path for Ct c through the n-channel resistance to 
ground. On the positive transition of the signal (at point 2), 
the diode is cut off and Ctc discharges through Rtc- The 
discharge time constant (Rtc Ctc) is much greater than the 
time of the burst duration. Point 3, therefore, never reaches 
the switch point of inverter B until the burst has ended. The 
waveforms for 4 points in the circuit are shown in Fig. 21b. 



92CS- 22881 


Fig. 21 - fa) Demodulator circuit; (b) waveforms. 



Fig. 20 - fa) Modulator circuit; fb) waveforms. 


538 




Solid State 
Division 


Digital Integrated Circuits 

Application Note 
ICAN-6289 


A COS/MOS PCM Telemetry and 

Remote Data Acquisition Design 


by A. Young and D. Block 


Introduction 


Format 


GENERAL CONCEPTS 


The data explosion has brought with it a tremendous demand 
for acquisition stations capable of providing information to a 
central location for recording and processing. A particular 
challenge to designers is remote stations for geologic, oceano- 
graphic, and space applications where high reliability of data 
must be combined with low power dissipation to conserve power 
supplies. 

Pulse code modulation (PCM) and COS/MOS are an excellent 
combination for these applications since COS/MOS devices have 
inherently low standby and operational power requirements. 
The wide range of supply voltages (3 to 15 volts) from which 
COS/MOS circuits can operate reduces power-supply regulation 
requirements and, in addition, permits emergency power 
sourcing from convenient alternate supplies. PCM telemetry 
systems designed to work in severe electrical-noise environments 
can also benefit from the inherently high noise immunity of 
COS/MOS devices (typically 45 percent of the supply voltage). 
Finally, both analog and digital data can be switched through 
COS/MOS devices; this feature allows convenient multiplexing 
and interfacing of the telemetry logic with the external world. 

The wide range of circuits from simple gates to complex 
multiplexers and arithmetic units available as standard parts in 
the COS/MOS CD4000 family allows the realization of the 
functional elements of PCM telemetry systems with a minimum 
number of components. The ease of system design resulting 
from the availability of MSI functions and the tolerant nature of 
the COS/MOS devices can result in reduced design time and re- 
liable system operation. For critical applications, COS/MOS 
parts are also available in Hi-Rel versions processed to MIL-STD- 
883 or MIL-STD-385 10. 

This note contains descriptive background material on tele- 
metry systems plus examples of typical systems for both 
immediate and remote data conversion and transmission. Parts 
from the CD4000 family are used to show how various sections 
of the system may be realized in the general case. The exact 
configuration of any specific system would, of course, depend 
on the unique requirements of the application. 


The order in which data channels are sampled is of funda- 
mental importance to the operation of the systems. This order- 
ing of data is called the “format.” The smallest unit of digital 
data is a “bit” (either a logic 1 or logic 0) and the smallest 
number of bits handled as a single entity is called a “word.” The 
word length or number of bits in each word is determined by the 
accuracy with which analog information is to be converted to an 
equivalent digital word; the greater the accuracy the more bits 
required. Two types of words are used in a telemetry system: 
control words containing synchronization or parity bits and data 
words containing the actual information to be transmitted. 
Words are grouped together into frames. A frame contains one 
control word and an integral number of data words. The format, 
then, refers to the sequence of words within a frame. Fig. 1 
shows a typical format of N words grouped into a frame. 


SYNCHRONIZING BITS 


FIXED FOR EACH 
FRAME 


1 1 1 1 1 1 II OIOO 10 1 1 


CONTROL DATA 

WORD WORD 


VARIABLE DATA WORDS 
A 


"\ 


100 1 01 10 


1001 1011 


DATA 

WORD 

2 


DATA 

WORD 

N 


FRAME 

, 92CS- 23356 

Fig. 1— Basic data format. 

Information Transmission Rates 

To accurately reconstruct at the receiver end of a telemetry 
system events occurring at the transmitting end, data must be 
sampled at a rate at least as fast as the fastest changing bit in the 
data word. Once this rate is determined, the bit rate to be trans- 
mitted can be found from the following expression: 

Bit Rate = (Word Length) (Frame Length) (Sampling Rate) ( 1 ) 


6-74 


539 







I CAN -6289 


Thus, for a sampling rate (SR) of 100 samples per second (SPS), 
a frame length of 10 words, and a word length of eight bits, the 
bit rate (BR) is 8 kilobits per second (kBPS). 

A disadvantage of the format in Fig. 1 is that it requires the 
sampling rate to be the same for each input. However, many 
applications have inputs which change at different rates, and for 
maximum efficiency a range of sampling rates is desirable. There 
are two techniques which may be used to accomplish sampling 
rate variation: subcommutation and supercommutation. 

Woid 

Slot 

1 2 3 4 5 6 7 8 1 2 

1 Sync VA 'A 02 I 03 1 04 VA'2 05 1 06 I Sync X/w'A f 


BR G.4 kBPS 

SR ■ 100 SPS Word Slot 18 hit woitls) 




Subframe 

Sync 


92CS - 23357 


Fig. 2— (a) Supercommutation of channel D1 in word slots 2 and 6; 
(b) subcommutation of word slots 3 and 5; (c) shorthand 
representation of (b). 

In supercommutation, as shown in Fig. 2(a), data channels 
are repeatedly sampled within the same frame to obtain 
sampling rates that are multiples of the fundamental rate. For 
the format parameters shown, D1 is sampled at 200 samples per 
second, twice the fundamental rate. The process of super- 
commutation is equivalent to dividing the frame-length term of 
Eq. (1) by the number of repetitions of a given channel. Proper 
supercommutation requires that the word slots be evenly spaced 
in a frame. 

Subcommutation, Fig. 3(b), is an alternate sampling of data 
channels from frame to frame to obtain sampling rates that are 
less than the fundamental rate. In Fig. 2(b), channel D2a is 
sampled every fourth frame, as are channels D2b, D2c, and the 
subframe sync channel. Channels D4a and D4b are sampled 
every other frame. Fig. 2(c) is a shorthand notation of this 
format. The process of subcommutation is equivalent to multi- 
plying the frame-length term of Eq.(l)by the subcommutation 
length. 

The entire data cycle (the smallest number of words that 
repeat periodically) is called a “subframe” and includes the main 
frame and subsequent frames. Subcommutation can be applied 
to more than one main frame word, but the number of sub- 
commutations must have an integral relationship to all other 
subcommutation lengths. For example, subcommutation 
lengths of 2, 4 and 16 in the same format are acceptable, but 
lengths of 2, 8 and 10 are not because 10 is not an integral 
multiple of 8. The maintenance of integral relationships in sub- 
commutation assures the synchronization of subcommutated 
channels required for decommutation. 


A DESIGN EXAMPLE 


Format 

Manipulation of the bit-rate, frame-length, and sub- 
frame-length parameters is required to obtain an optimum 
format from sampling rate requirements. Consider, for example, 
the requirements for transmitting 8 channels of analog in- 
formation, identified as A1 through A8 in Fig. 3(a), and one 

1 2 3456789 10 

[~Sync | A1 | A2 | A3 | A4 | A5 | A6 [ A7 | A8 | D1 | 
BR = 8x10x200 - 16 kBPS for 8-bit words 
A = Analog Data Channels 
D = Digital Data Channels 

Word (at 



(Numbers in parentheses are sampling rates) 
BR = 8x100x8 - 6.4 kBPS for 8 bit words 


(b) 92CS- 23358 

Fig. 3— (a) Format configuration 1; (b) format configuration 2. 

channel of digital information (Dl) where the required sampling 
rates are: 

(a) 200 samples per second (SPS) for one analog channel 

(b) 1 00 SPS for two analog and one digital channel 

(c) 50 SPS for two analog channels 

(d) 25 SPS for three analog channels 

One solution would be to sample all channels at 200 SPS. This 
sampling rate meets the requirement of the most active channel 
at the cost of over-sampling the others. The resultant ten-word 
frame shown in Fig. 3(a) would require a bit rate of 1 6 kBPS for 
an eight-bit word length. This format is inefficient and results in 
having to record and process redundant data. 

An alternate format, shown in Fig. 3(b), consists of eight 
100-SPS main frame words with supercommutation and sub- 
commutation used to generate alternate sampling rates. Super- 
commutation of word slots 2 and 6 produces a 200-SPS channel. 
Subcommutation of word slot 5 twice and slot 3 four times 
produces 50- and 25-SPS channels, respectively. The bit rate 
required by this format is 6.4 kBPS or roughly one-third of that 
required by the previous format. The reduction is accomplished 
with only a small increase in programming hardware. 

System Hardware 

A block diagram of the functions needed for the telemetry 
system of the design example above is shown in Fig. 4. The 
system includes both analog and digital multiplexers, an 
analog-to-digital converter and digital data-signal conditioner, a 
programmer, and an output formatter, synchronizer and serial- 
izer. The following sections discuss the implementation of these 
functions with standard COS/MOS CD4000-family parts. 


540 



ICAN-6289 



92CS- 24033 


Fig. 4— PCM telemetry system. 


Programmer 

The Programmer provides basic timing and system synchron- 
ization by reducing the bit-rate clock timing to words, frames, 
and subframes. In general, counters and decoders are required to 
generate the format matrix column and row dimensions. The 
COS/MOS IC family includes several devices that aid in the 
design of format counters and decoders; one such device is the 
CD4018A, Presettable Divide-by-N Counter. One or more 
CD4018A’s can provide a large selection of frame and subframe 


lengths. The CD4017A (Decade Counter plus Ten Decoded 
Outputs) or the CD4022A (Divide-by-Eight Counter with Eight 
Decoded Outputs) may be used instead to generate 8 or 10 
decoded states. The internal decoding of these devices greatly 
reduces the number of IC’s required in the Programmer. The 
CD4024A, CD4040A, and CD4020A, 7, 1 2, and 14-stage binary 
counters, respectively, can be used to generate longer binary 
frame/subframe lengths. Decoding of these counters can be per- 
formed by standard COS/MOS gates. The Programmer of Fig. 5 
has been designed with six COS/MOS IC’s. 



A/D CONVERTER 
CLOCK 
( ADCL) 



|_C0_40OJ_A I 


92CM-23360 


Fig. 5— Programmer timing generation. 


541 













I CAN -6289 


Handling Analog Inputs 

Analog input channels to the PCM system of Fig. 4 are 
switched to an A/D converter, and the resultant digital word 
transferred to a parallel-to-serial converter for serial readout. 
Synchronization of the A/D operation is explained below. 
Analog switching can be done with CD4066A transmission 
gates, as shown in Fig. 6. Switching of the gates is controlled by 
the word and frame counters properly decoded to generate the 
format of Fig. 3(b). 



I ! 


92 CM - 2403 1 

Fig. 6— Analog multiplexer. 


The accurate conversion of analog inputs to digitally coded 
words is a major function of PCM systems. The logic required to 
control conversions using the successive approximation tech- 
nique can be implemented with standard COS/MOS circuits. 
Also, the analog portion of the A/D converter can be simplified 
by the use of COS/MOS devices, depending upon the accuracy 
and speed required. 


A COS/MOS A/D converter design using the successive 
approximation technique is shown in Fig. 7. A timing sequence 
to encode an analog input of 1 .480 volts is given in Fig. 8. The 
converter works as follows. Operation is initiated by the pro- 
grammer when the next word-slot is assigned to an analog input. 
At that time (SO) the A/D holding register is set to 1000000 
(half scale). This action generates a reference voltage (Vr) of 2.5 
volts which is applied to comparator A1 . The comparator output 
is zero if Vr is greater than AMUX (AMUX is the sampled input 
voltage from the multiplexer), hence the D inputs to the register 
elements are zero. At time SI the first flip-flop is clocked to zero 
and the second flip-flop is set to the one state. The resulting 
reference voltage (1 .25 volts) is less than AMUX this time, and 
the comparator output goes to the one state. At time S2, the 
second flip-flop is clocked to one , and the third flip-flop is set to 
the one state. This procedure continues until all the bit weights 
have been considered for inclusion in the encoded word. For an 
8-bit system with a 5-volt reference, the lowest discrete level of 
quantization is 19.6 millivolts, and the maximum theoretical 
accuracy is 0.4 percent. However, for the system shown in Fig. 7 
where COS/MOS flip-flops drive a 200-kilohm resistor ladder 
directly, an accuracy of 1.5 to 2 percent can be expected with 
conversion rates of approximately 10 kBPS. This encoder can 
handle the data requirements of most operational and sur- 
veillance applications as well as some experimental applications. 
The system can be made to operate more accurately if the 
impedance of the most significant bit (MSB) switches is reduced. 
This can be done by using CD4041 A low-impedance buffer units 
between the flip-flop outputs and the resistor ladder on the first 
two flip-flops. The CD4041 A’s have output impedances of less 
than 200 ohms at 5 volts, either sourcing or sinking current, and 
permit construction of an 8-bit converter with a relative 
accuracy of one percent or less. 

An alternate method of constructing the A/D converter so 
that analog signals both above and below ground can be handled 
is shown in Fig. 9. Here the CD4054A’s are used as level shifters 
to convert theO- to +5-volt levels from the holding register to -5- 
to +5-volt signals to the resistor ladder. By connecting one end of 
the ladder to -5 volts, Vr is allowed to range between -5 volts 
and +5 volts. By judicious choice of power supplies, analog volt- 
ages between ± 7.5 volts could be accommodated using this 
scheme. (Another scheme for A/D conversion is given in refer- 
ence 2.) The entire telemetry system could have been run with 
Vdd = 5 V and Vgg = -5 V; level translators would not then be 
necessary. However, to minimize overall dissipation (dynamic 
power is proportional to V^) the system was designed to operate 
with Vqq = 5 V and Vgg = 0 V. 

A/D converters are subject to numerous error sources, many 
of which are rather subtle. Temperature variation is one of the 
major causes of error. Changes as small as 10°C can cause an 
output variation equivalent to a quantizing level. Other sources 
of error which must be considered in a practical design include 
such parameters as sampling-rate variations, aperture time, inter- 
polation errors, source impedance, and multiplexer leakage. 
Trade-offs between cost, size and power must also be made in 
determining the optimum system for a given application. 

A timing diagram showing bit-timing assignments in relation 
to the A/D conversion cycle is shown in Fig. 8. 


542 




I CAN -6289 



Handling Digital Inputs 

In the most general case, the digital-word input to the PCM 
system could have logic levels degraded as the result of noise, 
offsets, or other causes, or it could consist of simple analog 
voltages to be quantized to single-bit resolution. In the latter 
case, the concern is only that the input voltage is above or below 
a given threshold. In the former case, comparison of the in- 


put-voltage level against a reference would be used to re-establish 
solid logic one and zero-voltage levels. This process is referred to 
as “signal conditioning.” Thus, Fig. 7 shows digital inputs being 
put through comparator A2 for conditioning and being stored in 
the A/D holding register. In the case of digital data, the ladder 
network hanging on the register is superfluous. Digital data is 
simply stored in this register for convenience (to avoid having to 
create a separate register and controls) and to keep timing and 
synchronization constant. 


543 












ICAN-6289 



92CS-24029 

Fig. 8— A/D timing for encoding an analog input of 1.480 volts. 



Fig. 9— Alternate A/D analog section. 













I CAN -6289 








Fig. 10— Bit timing assignment. 



Fig. 1 1— Digital multiplexing. 


The digital input word is first multiplexed into a serial data 
stream using the CD405 1 A, as shown in Fig. 1 1 . At time SO, the 
first flip-flop of the holding register is set to the 1 state, and will 
be conditionally reset depending on the output of comparator 


A2 at the end of time SO. (Refer to the description of operation 
of - the A/D converter for a more detailed explanation of 
this cycle.) The sequence is repeated for each bit until the entire 
word has been entered into the holding register . 


545 




I CAN -6289 


Data Output 

At the appropriate time determined by the format, the 
output serializer gathers data from one of three sources: a data 
word from the A/D holding register, or control words from the 
main frame-sync word generator or the subframe-sync word 
generator. The 8 -bit parallel word is loaded into a CD4021A 
shift register, as shown in Fig. 12, at the end of bit period T7, 


and then clocked out at the bit rate. To preserve the symmetry 
of the last bit period, a flip-flop is added to the end of the 
register. Selection of data to the register can be performed by a 
double rank of CD4019A’s. Sync-bit patterns are normally fixed 
for a given system, and the bit lines are hand-wired to Vdq or 
V 53 in correspondence with the ones and zeros of the chosen 
sync pattern. 

The output data can feed a computer directly or can mod- 
ulate an rf carrier for telemetering to a distant data sink.2 



MFSB * MAIN FRAME SYNC BIT 
SFSB = SUBFRAME SYNC BIT 


Fig. 12— Sync and subframe sync word generator, output data formatter, and serializer. 


546 





ICAN-6289 


System Integration 

A diagram of the entire PCM telemetry system of Fig. 4 is 
shown in Fig. 1 3 ; system timing is shown in Fig. 1 0. 

Remote Data Acquisition 

Many industrial-control and data-management systems are 
not efficiently served by fixed-format PCM systems. Their re- 
quirements are better satisified by slaved-data acquisition 
subsystems in which data and control is provided on request, a 
method that substantially reduces redundant data and trans- 
mission rates and that provides control capability at remote 
locations. The PCM telemetry system previously described is 
adaptable to this form of operation. The implementation of the 


logic of remote slaved-data acquisition systems with COS/MOS 
devices is desirable because the power consumption of the 
system is reduced significantly as the switching activity of the 
circuit decreases. 

A slaved Programmer must include a channel address-register, 
data-request recognition logic, and output transfer-con- 
trol logic. The format is defined by an external programming 
source and is not constrained by the acquisition system except 
for maximum channel capacity; format words-per-frame and 
frames-per-subframe counters are not necessary. The interface 
can range from a single wire to several parallel buses; Figure 14 
shows a block diagram of a typical interface scheme. There are 
five control lines in the system: CLOCK, DATA REQUEST, 
REQUEST ACCEPTED, BUSY and DATA READY. A single, 
bi-directional line is used to send the desired channel address to 
the slaved programmer and to return the requested data. 



T T 

TO Tl 

BIT TIMING 


nr 

Wl W2 

WORD TIMING 
CLOCK/PROGRAMMER 


n i i — r 

FI F2 F3 F4 
FRAME TIMING 


92CL-2336B 


Fig. 13— Diagram of PCM telemetry system of Fig. 4. 


547 








I CAN -6289 


The block diagram in Fig. 1 5 shows the main functional units 
of the interface scheme of Fig. 14. A request is initiated by 


DATA REC 


DATA RE, 



92CS - ^ 3i69 

Fig. 14— Staved system. 

applying a logic 1 to the DATA REQUEST line. The control 
logic services requests on a first-in-first-out basis, and ignores any 
requests initiated while it is in the BUSY state. When a request is 
initiated at a valid time, a REQUEST ACCEPTED pulse is gener- 
ated, the BUSY line is set to 1 , and the input to the channel-ad- 
dress register is enabled for loading. After the channel-address 


information is received, the requested data is digitized, the 
DATA READY line is set to 1 and the output data register is 
clocked onto the ADDRESS/DATA line. The control logic then 
resets itself, and the system is ready to acquire a new data word. 

The implementation of a 16-channel analog system using 
COS/MOS standard parts is shown in Fig. 16; the associated 
timing diagram is shown in Fig. 1 7. A DATA REQUEST sets the 
data-request flip-flop (REQUEST ACCEPTED) and enables the 
Clock and Address lines to the CD401 5 A channel-address regist- 
er. When the CD4017A address bit-counter indicates that the 
address has been received, the DATA REQUEST flip-flop is 
reset, all inputs to the channel-address register are disabled, and 
one of the 16 input channels is switched to the converter 
through a CD4051 A. The BUSY flip-flop, which was set by the 
REQUEST ACCEPTED signal, disables any further inputs until 
the cycle is completed. 

A/D conversion can be performed as described above or in 
reference 2. At the end of the A/D conversion period, the results 
of the conversion are loaded into a CD4021 A shift register, and 
the DATA READY flip-flop is set. A CD4016A transmission 
gate is turned on by this signal, and the shift-register output to 
the ADDRESS/DATA line is enabled. A separate flip-flop is used 
to synchronize the output with the master clock, assuring that a 
full clock period is available for each bit. Output data is clocked 
onto the ADDRESS/DATA line and the clock pulses counted in 
a CD4017A counter to determine the end of the transfer time. 
At the end of this time period, the BUSY and DATA READY 
signals are cleared, and the control flip-flops and counters arc 
reset for the next request. 



Fig. 15— Staved programmer. 


548 





















1CAN-6289 


Conclusions able flexibility to achieve the goals of his application. 


The options available to the designers of data acquisition 
systems to meet operational requirements are as numerous as the 
applications for such designs. Features such as extended accur- 
acy, sample-and-hold, selectable input levels, high data-input 
impedance, control outputs, limit checking, serial data acquisi- 
tion, calibration-signal output, and digital data processing can be 
added to the basic system described here. The COS/MOS 
CD4000 integrated-circuit family provides features particularly 
suited to telemetry or related data-systems design, and the large 
number of standard parts available gives the designer consider- 


References 

1 . “Design of Fixed and Programmable Counters Using the 
RCA CD4018A Presettable Divide-By-“N” Counter,” J. 
Litus, Jr. RCA Application Note ICAN-6498. 

2. A technique for generating and subsequently decoding 
biphase FSK is described in: “A Typical Data-Gathering and 
Processing System Using CD4000A-Series COS/MOS Parts”; 
D. Block, RCA Application Note ICAN-62 1 0. 


550 




Solid State 
Division 


Digital Integrated Circuits 

Application Note 
ICAN-6304 


Power Supplies for COS/MOS 


D. Blandford 
A. Bishop 

Two of the major advantages of COS/MOS logic systems are 
their low power dissipation and ability to operate over a wide 
range of supply voltages. These features permit the use of 
simple, small, low-cost power supplies. Examples of various 
COS/MOS power-supply circuits and their relative costs are 
given in the following Note along with the factors important in 
their design. These examples are intended as a guide rather 
than the optimum design for a particular system. 

DESIGN EXAMPLES 

Ten examples of power-supply circuits for use in COS/MOS 
logic systems are described below. The systems are employed 
in applications ranging from general-purpose, low-frequency 
types to those operating at high noise immunity and high 
frequency. The component values for each power-supply 
circuit are given for three system sizes, 20, 50, and 100 
COS/MOS devices. It is assumed that each system is composed 
60 per cent of gate circuits and 40 per cent of MSI circuits, 
although, as explained below in the section concerning design 
considerations, these proportions are, in general, not 
important. 


Low-Frequency Systems 

The main requirement in a low-frequency (50-kHz) system is 
low cost. A Vdd °f 5 volts yields a low supply current of 60 
microamperes per device and a reasonable noise immunity of 
1.5 volts in each logic state. This type of power supply, Fig. 1, 



SYSTEM ^SUPPLY NO-LOAD VOLTAGE R 

SIZE (mA) (VOLTS) (OHMS) 


20 1.2 5.8 2K 

50 3.0 6.1 910 


100 6.0 


6.2 470 


92CS-25I20 


Fig. 1 — Power supply for a low-frequency system. 


is used in general-purpose applications, such as digital 
instruments, remote monitoring equipment, and computer 
peripherals. 

If higher noise immunity is required, for example, in an 
industrial-control application, a higher value of VdD would be 
needed. At 12 volts, the noise immunity is 3.6 volts in each 
logic state. Fig. 2 shows the circuit used in this type of 
application. 



20 2.9 I K 

50 7.3 390 

100 14.5 200 


92CS-25I2I 


Fig. 2 — Power supply yielding higher noise immunity than the circuit 
of Fig. 1. 

If an application calls for the highest obtainable noise 
immunity, a Vdd of 14.5 volts could be used. The minimum 
noise immunity in this case is 4.35 volts in each logic state. 
Operation at 14.5 volts causes an increase in power 
consumption and requires that the supply be regulated to 
ensure that the supply rail does not exceed the maximum 
rating of 1 5 volts. Fig. 3 shows the circuit for applications of 
this type. 


Mixed Systems of 2-MHz and 50-kHz Circuits 

10 per cent at 2 MHz, 90 per cent at 50 kHz. A nominal 
VDD of 10 volts is selected to enable most COS/MOS circuits 
to operate at toggle rates greater than 2 MHz, Fig. 4. 

50 per cent at 2 MHz, 50 per cent at 50 kHz. The simple 
zener-diode circuit shown in Fig. 5 is all that is required to 
provide the nominal 10-volt supply, the power rating of the 
zener diode depends on the number of devices in the system. 


9-74 

551 





I CAN-63Q4 



20 3.6 

50 9 

100 18 92CS-25I22 


Fig. 3 — Power supply yielding highest obtainable noise immunity. 



SYSTEM ^SUPPLY R 

SIZE (mfl) (OHMS) 

20 12 220 

50 30 91 

100 60 47 


92CS- 25123 


Fig. 4 — Power supply for mixed system consisting of 10 per cent 
2-MHz and 90 per cent 50-kHz COS /M OS circuits. 



SIZE (mA) WATTS (OHMS) 


20 50 

50 125 

100 250 


1.5 82, 1/4 WATT 

1.5 33, I WATT 

5 15, 2 WATT 


92CS-25I24 


Fig. 5 — Power supply for mixed system consisting of 50 per cent 
2-MHz and 50 per cent 50-kHz COS /M OS circuits. 


COS/MOS System Powered by 5-Volt TTL Supply 

COS/MOS circuits can be added to or mixed with TTL 
circuits in a system. The COS/MOS circuits can operate 
directly from the 5-volt TTL power supply. At 50 kHz the 
supply current required by the COS/MOS circuit is only 60 
microamperes per device, so that for 100 COS/MOS devices, 
the supply current required is only 6 milliamperes. This 
current is less than that required by a single TTL quad-gate 
device, so that the 100 device COS/MOS system can be added 
to an existing TTL power supply without the need to modify 
the supply. 


Battery-Powered Systems 

COS/MOS circuits, with their low power consumption, are 
ideally suited for application in portable systems. The wide 
supply-voltage range permits operation from inexpensive, 
light-weight dry batteries, which may undergo a large change 
in voltage capacity from start to end of life. For example, a 
system containing twenty COS/MOS circuits operating at 10 
kHz from three 1.5-volt zinc-carbon dry cells consumes only 
220 microamperes. The logic system would operate for more 
than a year before requiring a battery change. 

Retention of data in a semiconductor memory when the 
main power supply is interrupted or turned off can easily be 
accomplished by using COS/MOS memory circuits and a 
standby battery. The battery used could be either a recharge- 
able nickel-cadmium type, as shown in the memory standby 
system of Fig. 6, or a dry battery. The memory system shown 


IN400I 



Fig. 6 — Memory standby system. 


is a 4K by 8 bit system that uses the CD4061AD, 256-bit 
RAM. The operating supply voltage is 10 volts, and at a 
1 -microsecond cycle time, the supply current required is 50 
milliamperes. The system power supply trickle-charges the 
standby battery during normal operation; for the system 
shown, recharge time is 35 hours. When the main power 
supply is turned off, the memory is powered by the standby 
battery. In the system shown, the 32k-bit memory would be 
powered for approximately one week. 

In portable applications requiring operation from a single 
battery cell, a dc-to-dc converter, Fig. 7, can be used to 
generate a higher voltage to power the COS/MOS circuits and, 
possibly, a liquid-crystal display. 


552 



I CAN-6304 



DESIGN CONSIDERATIONS 

The primary technical considerations in designing a power 
supply for a COS/MOS system are the required operating 
frequency, noise immunity, and power dissipation of the 
circuits in the system. 

Operating Frequency 

Toggle frequency and propagation delay improve as the 
supply voltage of a COS/MOS circuit is increased, as shown in 
Figs. 8 and 9. This improvement occurs because the output 
resistance of the MOS transistors used in the COS/MOS 
circuits decreases with increased Vdd while the output mode 
capacitance remains virtually unchanged, thus reducing the 
output time constant. The designer should ensure that the 
worst-case supply voltage is sufficiently high to yield the 
required switching speed. 1 



Fig. 8 — Typical clock frequency versus supply voltage for the 
CD4013A. 


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AMBIENT TEMPERATURE (T A )=25°C 
LOAD CAPACITANCE (C.) - 15 pF 

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SUPPLY VOLTS (V 0D > 92CS ., 7S48R1 

Fig. 9 — Minimum propagation delay time versus supply voltage. 

Noise Immunity 

The switching point of a COS/MOS circuit is typically half 
the supply voltage, Vdd, so that the noise immunity is 
typically 45 per cent of Vdd ln each logic state. Thus, an 
increase in Vdd will cause a proportionate increase in noise 
immunity. 2 The worst-case noise immunity is 30 per cent of 
VDD, as shown in Fig. 10. For example, if the required noise 



92CS-25I27 

Fig. 10 — Worst-case noise immunity versus supply voltage. 

immunity is 1.5 volt in each logic state, then Vdd should be 5 
volts or more. Maximum noise immunity is obtained by 
operating with a 15-volt supply, and is dependent upon 
maintaining good power-supply rail regulation during peak 
switching-current conditions. For example, a COS/MOS gate 
draws 10 milliamperes peak for approximately 50 nanoseconds 
during a switching mode for a 15 -volt supply. 

It is good practice to keep the power-bus dynamic 
impedance low throughout the COS/MOS system. In addition 
to good ground and supply -bus distribution, 0.01 -to 0.1 -micro- 
farad ceramic capacitors should be distributed throughout the 
system and connected from Vdd t0 Vss- As a general rule, a 
0.01 -microfarad capacitor should be used for every four-gate 
package, and a 0.1 microfarad capacitor for every four MSI 
packages. 


553 




ICAN-6304 


Power Dissipation 

The two previous sections explain the advantages of 
operating a COS/MOS system at high values of Vdd- However, 
use of high supply voltages is accompanied by high power 
consumption. The total power consumed has two components, 
quiescent or dc power consumption, which increases approx- 
imately linearly with Vdd> an£ l switching or ac power 
consumption, which increases as Vdd 2 . Fig- H illustrates the 
typical dissipation of a COS/MOS device. 



92CS-25099 

Fig. 11 — Typical dissipation of a CD4011A with a 15-picofarad load at 
10 kHz versus supply voltage. 

The expected power consumption of a given COS/MOS logic 
system can be calculated by summing the combinations of dc 
and ac power consumption of individual devices for expected 
values of supply voltage, operating frequency, and load 
capacitance. Generally, for a system larger than about ten 
devices, it should be sufficient to consider the typical values of 
power consumption. 

A useful guide for calculating system power consumption is 
shown in Fig. 12. This graph shows the average power 



FREQUENCY — Hz 

92CS-25I00 

Fig. 12 - Average power dissipation of a CD4000Aseries device versus 
frequency . 


consumption per device (e.g., quad NAND, counter, shift- 
register) versus frequency for various supply voltages at a 
practical loading of 50 picofarads. For example, assume that 
the power consumption for a mixture of 100 CD4000A 
circuits at a Vdd °f 5 volts and an operating frequency of 50 
kHz is desired. From Fig. 12, the dissipation per device is 300 
microwatts, so that the total system dissipation is 30 milli- 
watts for a supply current of 6 millamperes (see practical 
circuit, Fig. 1). In this example, the dc power is not significant 
and would typically total less than 1 milliwatt. 

If a more accurate value of the system power consumption is 
required, the contributions from each device may be 
calculated and summed to give the total. To do this, the value 
of quiescent dissipation given in the data sheet for the device is 
used together with the value of ac dissipation. The latter value 
is taken from the data-sheet graph of dissipation versus 
frequency at 15-picofarads load. The value obtained is valid 
for three loads or less; for more than three loads, Fig. 13 is 



Fig. 13 — Power dissipation per load of 5 picofarads as a function of 
frequency. 

used to determine the power dissipation contributed by the 
extra loads. For example, assume that the power consumption 
of a CD4011AE NAND gate at a Vdd of 5 volts and a 
frequency of 1 kHz with seven loads is desired. From the data 
sheet, the quiescent power dissipation Pq is 25 nanowatts. The 
dynamic dissipation Pd for a 15-picofarad load is given in the 
data sheet as 700 nanowatts. From Fig. 13 the power 
dissipation Pxl f° r the four extra loads is 500 nanowatts, so 
that the total power dissipation Pj, where Pp = Pq + Pd + 
PXL> is 1225 nanowatts or approximately 1.2 microwatts. 

Certain circuits require additional consideration because of 
their higher than normal power consumption. Such cases 
include gate circuits having slow input rise and fall times, as 
shown in Fig. 14. Examples of this type of circuit are RC 
monostable or astable circuits, and gate circuits with inputs at 
the end of long transmission lines. Circuits driving large 
capacitive loads, such as long transmission lines or the clock 
inputs of non-complementary MOS shift registers, are also 
representative of circuits with above-normal power consump- 
tion. Higher power consumption can also occur at the 
interface between COS/MOS circuits and transistor drivers, 
other logic families, and digital displays. 


554 





ICAN-6304 



INPUT RISE AND FALL TIME <» f ,tf ) 

92CS-20490RI 

Fig. 14 — Power dissipation as a function of transition time for a 
CD4049A. 


Regulation 

The regulation of a COS/MOS power supply should be 
designed to maintain Vdd at a value equal to or greater than 
the value needed to obtain the required switching speed and 
noise immunity and less than either the maximum Vdd rating 
of 15 volts or the maximum Vdd required to yield a specific, 
expected, over-all power-dissipation rating, whichever is lower. 
The regulator circuit must also suppress any voltage transients 
that might cause the supply to exceed 15 volts. 

REFERENCES 

1. For more information on switching speed see the 
CD4000A-family data sheets, which contain graphs of 
switching speed as a function of VdD- 

2. A precise definition of noise immunity is given in the RCA 
Solid-State DATABOOK Series SSD-203, “COS/MOS 
Digital Integrated Circuits”. 


555 


[MM] 

Digital Integrated Circuits 

Solid State 

Division 

Application Note 

ICAN-6498 


Design of Fixed and 
Programmable Counters Using the 
RCA CD4018A COS MOS 
Presettable Divide -by-"N ’’Counter 


byj. LitusJr. 

The RCA CD4018* COS/MOS (Complementary - 
Symmetry Metal-Oxide-Semiconductor) presettable divide- 
by-“N” counter is designed for use in digital equipment 
where low power dissipation, low package count, and high 
noise immunity are primary design requirements. The 
counter is particularly useful in such systems applications as 
channel-preset counters in digital frequency synthesizers and 

* Supplied in plastic dual-in-line package as the CD4018AE, 
in ceramic dual-in-line package as the CD4018AD and in 
ceramic flat-pack as the CD4018AK. 


program-counter control. TheCD4018Acan also be used as a 
5-stage parallel input/output holding register. In this 
application the parallel entry can be controlled by the 
preset-enable line to perform a 5-stage “latch” operation. 
This Note describes the use of theCD4018Ain single-decade 
and multi-decade fixed and programmable divide-by-“N” 
counters. System considerations such as switch simplifica- 
tions, components minimization, and speed are also 
discussed. 

The logic diagram for theCD4018Ais shown in Fig. 1. 
Fig. 2 shows the counting sequence and timing diagram for 
this device connected as a decade counter. 



Fig. 1 - Logic diagram for CD4018A. 









I CAN-6498 


Count 

Ql 

q 2 

Q 3 

q 4 

Q5 

0 

1 

1 

1 

1 

1 

1 

0 

1 

1 

1 

1 

2 

0 

0 

1 

1 

1 

3 

0 

0 

0 

1 

1 

4 

0 

0 

0 

0 

1 

5 

0 

0 

0 

0 

0 

6 

1 

0 

0 

0 

0 

7 

1 

1 

0 

0 

0 

8 

1 

1 

1 

0 

0 

9 

1 

1 

1 

1 

0 


(a) 


FIXED SINGLE-STAGE DIVIDE-BY-"N" COUNTERS 

Divide-by-10, 8, 6, 4, or 2 counter configurations can be 
implemented by feeding the Q5, Q4, Q3, Q2, or Q1 signals, 
respectively, back to the Data input. Divide-by-9, 7, 5, or 3 
counter configurations can be implemented by the use of 
NOR- or NAND- gate packages to gate the proper feedback 
connection to the Data input line. Fig. 3 shows the feedback 
connections for divide-by-9, 7, 5, and 3 functions using the 
CD4011A NAND gate as the feedback circuit. 


DIVIDE BY 10 
DIVIDE BY 8 
DIVIDE BY 6 
DIVIDE BY 4 
DIVIDE BY 2 


Q4 

q 2 


CONNECTED 
BACK TO 
"DATA” 


NO EXTERNAL 
COMPONENTS 
REQUIRED 


Ql 

02 

03 

04 

05 




(“DATA” INPUT TIED TO Q s FOR DECADE COUNTER CONFIGURATION) 
CLOCK 
RESET 
PRESET 

Jom 2 


DON’T CARE UNTIL "PRESET” GOES HIGH 


(b) 


DIVIDE BY 9 
DIVIDE BY 10 
DIVIDE BY 8 
DIVIDE BY 6 
DIVIDE BY 4 
DIVIDE BY 2 


04 

q 3 

S 2 


CONNECTED 
BACK TO 
"DATA" 


NO EXTERNAL 
COMPONENTS 
REQUIRED 


DIVIDE BY 9 

1/2 CD40IIA 



CONNECTED BACK TO "DATA" 
(SKIPS “ALL- 0’s“0UTPUT 
STATE) 


DIVIDE BY 7 

1/2 CD40IIA 



CONNECTED BACK TO "DATA" 
(SKIPS "ALL- O’s" OUTPUT 
STATE ) 


DIVIDE BY 5 

1/2 CD40IIA 



CONNECTED BACK TO "DATA" 
(SKIPS "ALL- O’s" OUTPUT 
STATE ) 


Fig. 2 - (a) counting sequence for decade-counter operation; 
(b) timing diagram for decade-counter operation. 


DIVIDE BY 3 

1/2 CD40IIA 



CONNECTED BACK TO "DATA" 
(SKIPS "ALL- 0’s“0UTPUT 
STATE ) 


92CS-I7 3 20 


The CD4018A consists of five flip-flops that can be con- 
nected as a five-, four-, three-, or two-stage Johnson Counter 
with buffered Q outputs from each stage. Gating is included 
for presetting the counter. “Clock”, “Reset”, “Data”, 
“Preset-Enable”, and five “Jam” inputs are also provided. 
The counter is advanced one count at the positive-going 
transition of the clock. A “high” Reset signal clears the 
counter to an “all-zero” (Q outputs are all “ones”) condition, 
and a “high” Preset Enable signal allows information on 
the Jam inputs to preset the counter. 


Fig. 3 - External connections for divide by 10, 9, 8, 7, 6, 5, 
4, 3, and 2 operation. 


Fig. 4 shows the divide-by-seven configuration in detail. 
The logic diagram and pertinent waveforms are shown in 
Figs. 4a and b. Fig. 4c shows the counting sequences for a 
divide-by-eight and a divide-by-seven configuration. Division 


557 




I CAN-6498 


Jj J2 J3 J4 J5 PE 
; L CD 40 I 8 

Q| Q2 Q3 Q4 Q 5 


J 


of the clock frequency by seven is accomplished by altering 
the counting sequence so as to skip the “all zeros” state of a 
divide-by-eight counter. The divide-by-seven counting 
sequence proceeds as in a normal 4-stage Johnson counter 
until count 3 (0001) at which point Q3=0 and Q4=l . At this 
point theCD401 1 Agates Q3 and Q4 to put a 0 on the Data 
input to the first stage. Thus, count 4 will be 1000 instead of 
0000 as in the unaltered divide-by-eight sequence. The 
remainder of the counting sequence proceeds in the normal 
4-stage manner. 



X 


CLOCK FREQ * 7 


(a) 



Count 

°i 

q 2 

Q3 

q 4 

0 

1 

1 

mm 

B 

1 

0 

1 

n 

B 


0 

0 

mm 

H 

1 ; B 

0 

0 

0 

1 

'|B^B 

0 

0 

0 

0 

B 

1 

0 

0 

0 

:B!^Bj 

mm 

1 

0 

0 

mm 

U 

1 

1 

0 


Count 

El 

q 2 

q 3 

El 

0 

1 

1 

n 

n 

1 

0 

1 

B 

n 


0 

0 

WM 

n 


0 

0 

0 

1 


1 

0 

0 

0 

5 

n 

1 

0 

0 

6 

Hi 

1 

1 

0 


(c) 


Fig. 4 - CD4018A in a fixed divide-by-7 counter configuration: 
(a) logic diagram; (b) timing waveforms; (c) counting 
sequences for a +8 and a -r 7 Johnson Counter. 


PROGRAMMABLE MULTI-DECADE DIVIDE-BY-"N" 
COUNTERS 

TheCD4018Ais especially useful in applications requir- 
ing low-power, programmable, divide-by-“N” counting. Two 
such applications are channel preset counters in digital 
frequency synthesizers and program counter control. 

Fig. 5 illustrates the use of three CD4018 units in a 
programmable divide by “N” counter, where “N” may be 
any number from 2 to 999 (counter output is equal to clock 
frequency divided by N). Extension to higher “N” ranges is 
readily accomplished by the use of additional CD4018 units. 
The counter is preset to the value of “N” via the three 
selector switches. The switches are arranged so that switch 
position 9 is equivalent to a “0” count in the counter, 
position 8 is equivalent to a “1” count, position 7 to a “2” 
count, etc. The counter counts up from the preset value (the 
N value) to its maximum count (999) and recycles, starting 
again from the preset value. Fig. 5b shows the counting 
sequence; oscillograph photographs of the waveform .at 
various points in the circuit (of Fig. 5a) are shown in Fig. 5c. 
Fig. 5d shows the N-counter output for various values of N. 

The Johnson-Counter configuration utilized in the 
CD4018A design permits significantly simpler “program- 
switch” (“N”-Select) implementation than is required in 
systems that use a BCD decade counter arrangement. The 
program switch is composed of three standard single-wafer 
switches, one for each CD4018A(one per decade). This 
compares with a four-wafer (4-pole) switch per decade for a 
BCD decade-counter arrangement. Also, the count decoding 
is much simpler in that only two outputs perCD4018Amust 
be decoded as compared to four for a BCD arrangement. The 
Johnson-type counter can also operate at higher speeds and 
provides spike-free decoded outputs. 

The configuration shown in Fig. 5 permits frequency 
division by 2 as a result of performing the Preset function 
during half a clock cycle. In this mode the maximum 
allowable frequency of operation is reduced, however. If this 
reduction in frequency is not acceptable, the logic diagram 
shown in Fig. 6 can be employed. In this circuit the Preset 
function is allowed a full clock cycle but the range of 
frequency division is reduced to 3 to 999. The counting 
sequence and pertinent timing waveforms for this circuit are 
shown in Figs. 6b, c, and d, respectively. Typical maximum 
operating frequency is 4 megahertz, for the counter in Fig. 5 
and 6 megahertz for the counter in Fig. 6. 


558 
























I CAN-6498 



FIRST DECADE SECOND DECADE THIRD DECADE 

(UNITS) (TENS) (HUNDREDS) 



•These digits, representative of count "9" in each decade, are decoded to give the preset strobe 



(c) (d) 


Fig. 5 — Three-decade, programmable, divide-by-"N" counter with frequency division from 2 to 999: (a) logic diagram; 
( b ) counting sequence; (c) timing waveforms at various points in the circuit (d) -r/V output for various values of N. 


559 







I CAN -6498 


TOV-SELECTOR SWITCHES 

UNITS I TENS HUNDREDS 



(a) LOGIC DIAGRAM 

FIRST DECADE SECOND DECADE THIRD DECADE 

(UNITS) (TENS) (HUNDREDS) 



THE SWITCH SETT INGS: THE "9" COUNTS FROM THE SECOND AND THIRD DECADE 
(SHOWN AS ITTol ) ARE GATED WITH THE "7" COUNT (SHOWN AS l T lo } ) FROM 
THE FIRST DECADE TO ACTIVATE THE "PRESET ENABLE", ONCE PER COUNTER 
CYCLE. 

(b) 



tN OUTPUT AND B 
PRESET STROBE 

( N IS SET FOR 009) 



(c) 


CLOCK-[tp"A", FIG. 60 ] 


009 


JAM- IN FOR 019 

SWITCHES 

PROGRAMMED - 050 
FOR "N“ EQUALS: 

[TP "B",FlG. 6 a] 090 

099 


(d) 


Fig. 6 — Three-decade, programmable, divide-by-"N" counter with frequency division from 3 to 999: (a) logic diagram; 
(b) counting sequence; ( c ) timing waveforms at various points in the circuit' (d) divide-by-N output for various values of N. 


560 








I CAN-6498 


PROGRAM-SWITCH ("N"-SELECT) OPTIONS 

Fig. 7a is a detailed drawing of a standard Centralab 
12-position wafer switch and the associated resistor network 
as used in Fig. 5a. The resistors connected to Vdd are 
required to prevent floating inputs on the “JAM” lines. In 
applications that require lower power dissipations or where 
component count or space considerations become important, 
the resistor network can be eliminated by the redesign of the 
switch. Two such options are shown in Figs. 7b and 7c. 

As previously mentioned in the discussion of Fig. 5, the 
range of N can be extended by adding more CD4018A units. 
In addition to this type of expansion each stage in the 
programmable divide-by-N counter can be designed to count 
to any base or radix. For example, the single stage 
divide-by-seven counter of Fig. 4 may be used as each stage 
in a multi-stage programmable counter. 


'V 



REAR VIEWS 




Fig. 7 - Switch configurations; (a) single wafer (standard) per 
decade; (b) two wafers ( modified standard) per decade; (c) 
single wafer (nonstandard) per decade. 


SUMMARY 

The RCA-CD4018A is a versatile counter. Because of the 
Johnson-Counter design employed, This device permits the 
design of simple decoding and preset switching circuits. The 
system can also operate at higher speeds and with much less 
power dissipation than a comparable BCD decade counter 
arrangement. Also the CD4018A, a COS/MOS device, 
possesses all the inherent advantages of this technology. 

This versatile device can be used in fixed or 
programmable divide-by-“N” counters where “N” can vary 
from two to ten for a single CD401 8A and greater than ten 
for multiple CD4018A stages. From an economical 
viewpoint, its versatility and low power requirement at high 
speeds make the RCA-CD4018A the logical choice for 
counter applications in control and frequency synthesization 
equipments. 


561 




DUCBZlI 

Solid State 
Division 


Digital Integrated Circuits 

Application Note 
ICAN-6576 


Power -Supply Considerations 
for COS/MOS Devices 


by H.L. Pujol 


RCA COS/MOS Digital Integrated Circuits operate at 
extremely low power dissipation levels. They function 
reliably with high noise immunity over a wide operating- 
voltage range. The RCA-CD4000A COS/MOS product line 
is designed to operate from 3 to 15 volts, which enables 
system designers to operate RCA COS/MOS devices from 
unregulated, poorly-filtered supplies, or from a wide variety 
of single- or multiple-cell battery sources. 


This Note describes the salient features of COS/MOS 
devices which permit operation from such a wide range 
of power sources and provides the system designer with 
the necessary information to permit him to design the 
most economical power source for his COS/MOS system. 
This Note is applicable to both COS/MOS product lines 
mentioned above. 


CHARACTERISTICS OF A BASIC COS/MOS 
LOGIC INVERTER 
Quiescent Device Dissipation. 

The basic logic inverter (or gate) formed by use of 
only a p- and an n-type device in series is shown 
schematically in Fig. 2. When the input lead is grounded 
or otherwise connected to 0 volts (logical “0”), the 
n-device is cut-off, and the p-device is biased on. As a 
result, there is a low-impedance path from the output to 
Vj)D> and an open circuit to ground. The resultant 
output voltage is essentially Vj)j), or a logic “1”. 

Similarly, when the input voltage is a logic “1”, or 
V DD , then the n-channel device becomes a low imped- 
ance, while the p-channel device becomes an open circuit. 
The resultant output becomes essentially zero volts (logic 
“ 0 ”). 


n-SUBSTRATE p-WELL 



Fig. 1— Cross-section of COS/MOS transistor. 


V DD 


0 

V| N 

1 

Fig. 2- Basic COS/MOS inverter (schematic). 



562 


3-71 






ICAN-6576 


Note that one of the devices is always cut-off at 
either logic extreme, and that no current flows into the 
insulating gates. As a result, the inverter quiescent power 
dissipation is. negligible (equal to the product of Vqj) 
times the leakage current). 

A cross section of the COS/MOS inverter as it is 
formed in an integrated circuit on an n-type substrate is 
illustrated in Fig. 1. The source-drain diffusions and the 
p-well diffusion form parasitic diodes (in addition to the 
desired transistors) at the basic inverter nodes, as shown 
in Fig. 3. These parasitic elements are back-biased (across 
the power supply) and contribute, in part, to the device 
leakage current and thus to the quiescent power 
dissipation. 


V DD 


INPUT 

o— 


“ T -Jn-SUBSTRATE 
p+| I 



p-WELL 


Fig. 3— Basic inverter showing parasitic diodes. 


RCA’s product line of COS/MOS devices consists of 
circuits of varying complexity (i.e., from the dual 4-input 
logic gate that contain 16 MOS devices, to the more 
complex 64-bit static shift registers that contain over 
1000 devices). These devices occupy different amounts of 
silicon area and are composed of varying numbers of 
circuits formed from inverters. Consequently, each device 
in the family exhibits a particular magnitude of leakage 
current, depending upon the total effect of device count 
and parasitic diode area. For example, some logic gates 
are specified to operate with a typical power dissipation 
of 5 nW (Vdj)= 10V), but 7-stage counters or registers 
are specified to operate with a typical power dissipation 
of 5 /iW (Vqq = 10V). Published data includes both 
typical device quiescent-current levels and maximum levels 
(V DD = 5V and Vq£)= 10V). The maximum values are 
rarely encountered in RCA devices. 


Device - Switching Characteristics. 

The input/output characteristics for the COS/MOS 
inverter are shown in Fig. 4. As mentioned earlier the 
signal extremes at the input and output are approxi- 
mately zero volts (logic “0”) and Vpj) (logic “1”). The 
switching point is shown to be typically 45 to 55% of 
the magnitude of the power-supply voltage (regardless of 
the magnitude of the power-supply voltage) over the 
entire range from 3 to 15 volts. Note the negligible change 
in operating point from — 55°C to +125°C. 

These excellent switching characteristics permit COS / 
MOS devices to be operated reliably over a wide range of 
voltages, a property not found in other logic forms. 

AC Dissipation Characteristics. 

During the transition from a logic “0” to a logic “1”, 
both devices are momentarily on. This condition results 
in a pulse of instantaneous current being drawn from the 
power supply. The magnitude and duration of this 
current depends upon the following factors: 

(a) the impedance of the particular devices being used 
in the inverter circuit 

(b) the magnitude of the power-supply voltage 

(c) the magnitude of the individual device threshold 
voltages 

(d) the input driver rise and fall times 



Fig. 4— Typical COS/MOS transfer characteristics as a 
function of temperature. 


563 



ICAN-6576 


An additional component of current must also be 
drawn from the power supply to charge and discharge the 
internal parasitic node capacitances and the load capaci- 
tances seen at the output. 

The device power dissipation which results from the 
above current components is a frequency-dependent para- 
meter. The more often the circuit switches, the greater is 
the resultant power dissipation. The heavier the capacitive 
loading, the greater is the resultant power dissipation. The 
power dissipation is not duty -cycle dependent. For all 
intents and purposes it may be considered frequency 
(repetition-rate) dependent. 

Because the RCA COS/MOS product line ranges 
widely in circuit complexity from device to device, the ac 
device dissipations vary widely from device to device. The 
effect of capacitive loading on the individual devices also 
varies. Figs. 5 and 6 show a family of curves for a 
typical gate device and a typical MSI device. These 
curves, from the published data for the individual devices, 
illustrate how device power dissipation varies as a 
function of frequency, supply voltage and capacitive 
loading. 

AC Performance Characteristics. 

During switching, the node capacitances, within a 
given circuit, and the load capacitances external to the 
circuit, are charged and discharged through the p- or 
n-type device conducting channel. As the magnitude of 
Vj)D increases, the impedance of the conducting channel 
decreases accordingly. This lower impedance results in a 
shorter RC time constant (this non-linear property of 
MOS devices is due to current saturation at large values of 
drain-to-source voltage). The result is that the maximum 
switching frequency of a COS/MOS device increases with 
increasing supply voltage. (See Fig. 7a). 



Fig. 5— Basic gate power dissipation characteristics. 



INPUT CLOCK FREQUENCY (f CL ) — kHz 

92CS-I7829 


Fig. 6- MSI device power dissipation characteristics. 


Fig. 7b shows curves of propagation delay as a function 
of supply voltage for a typical gate device. However, the 
the trade-off for low supply voltage (i.e., lower output current 
to drive a load) is lower speed of operation. 

The power dissipated during switching (if the load is 
assumed to be capacitive) is equal to: 

2 

C 0 V£)D/ [power is equal to energy per unit time] 
where C 0 is the output and load capacitance, Vdd is the 
supply voltage, and / is the operating frequency in hertz. A 
measure of this power dissipation as function of frequency can 
be obtained from the model shown in Figs. 8a and 8b which 
assumes step inputs and zero mode capacitance. 

The average power for the square-wave input voltage 
shown (repetition rate f 0 = l/t 0 ) is calculated as follows: 


P 


1 




o 


lN<‘>V 0 dt 


+— 

t„ 


j Ip(‘)(V DD -V 0 )dt 

jo 

2 


564 




ICAN-6576 


5 

2 

1 

*8 6 
E 

_l 

o 

^ 5 

£ 

lU 

O 4 

Ui 

ce. 

u. 

AMBIENT TEMPERATURE (T A )»25*< 
LOAD CAPACITANCE (C, ) - 15 pF 



“ 











: 













































_ 


- 

L 































































































































































- 

_ 




-- 


- 
















_ 

_ 









_ 

_ 



- 






- 


























“ 

- 
































































































































D4 

0 

2 

AC 

, ( 





A 









- 

- 






- 










-C 

:D402 





: 

: 


1 3 

0 

1 2 
z 

2 

Z3 | 

2 1 

X 

4 

2 

- 

- 






- 











- ' 





CD402IA 

E 





- 

















































































































































































































































































































































































































































































































































L 














0 5 10 15 20 


SUPPLY VOLTS (V DD ) 

92CS- 17774 



Fig. 7— Operating frequency and propagation delay as a 
function of power-supply voltage (a) Maximum 
guaranteed operating frequency as a function of 
power-supply voltage ( b ) Propagation delay as a 
function of power-supply voltage for the basic 
gate. 


dV_ 


For P with I N (t) = Ip(t) = (step inputs only), 


/• DD 

‘o J o 


(V D D- V 0 )d(V D D -V 0 ) 


DD 


,,,iLe. D . c v 2 dW 

l o 


Thus, for a step input, the average power dissipated is 
directly related to the energy required to change and dis- 
charge the circuit capacitance to the supply voltage, VdD- It 
should be noted that this power is independent of the device 
parameters. Although this equation was derived using an input 
voltage with a rise time of zero, it has also been shown to be a 
good approximation for circuits where the input voltage rise 
and fall times are small with respect to the repetition rate. 

Calculating System Power 

The foregoing material presented fundamental reasons why 
COS/MOS devices exhibit extremely low quiescent power. 
Also presented were reasons why ac power dissipation in- 
creases with operating frequency and why it varies from 
device to device. 

For these reasons certain guidelines have been developed 
to assist the designer in estimating system power. Total sys- 
tem power is equal to the sum of quiescent power and 
dynamic power. Therefore, the two-step approach outlined 
below can be used: 

1 . Add up all typical package quiescent power dissipations 
(as shown in the RCA COS/MOS published data). 
Because quiescent power dissipation is equal to the 
product of quiescent device current times supply volt- 
age, this parameter may also be obtained by adding all 
typical quiescent device currents, and multiplying the 
sum by the supply voltage, Vdd- Quiescent device 
current is shown in the published data for supply volt- 
ages of 5 volts and 10 volts only. 

In cases where the supply voltage is other than that 
shown in the published data, the quiescent device cur- 
rent can be interpolated because this current varies 
approximately linearly with voltage. 



Fig. 8— Mode! for the evaluation of power dissipation 
(a) Waveforms (b) Circuit. 


565 




ICAN-6576 


2. Add up all dynamic power dissipations using 
typical curves of dissipation per package as a 
function of frequency shown in the published 
data. In a fast-switching system, most of the 
power dissipation is dynamic, therefore, quiescent 
power dissipation may be neglected. 

The example below illustrates how these rules are 
used to calculate total system power dissipation. 
The system illustrated consists of ten 2-input NOR 
gates, eleven inverters, one D-type flip-flop, and 
one 7-stage binary counter. The system operates 
with a supply voltage of 10V at a frequency of 
100 kHz, and has a load capacitance of 15 pF. 
(See Table 1 ) 


Table I 


Types 

PQuiescent 

MW 

PDynamic 

mW 

Gates 

0.03 

2 

Inverters 

0.01 

2 

D-type F/F 

0.05 

0.2 

Counter 

5 

0.6 

Pj = Pq + Pq = 4.8mW (neglecting Pq) 


This example assumes that all devices are switching at 
the clock-rate (100 kHz). Not all of the logic circuits will 
be switching states at this rate, thus, the total power 
dissipation will be significantly lower than that stated in 
the example. 

Power-Supply Regulation Requirements. 

The preceding discussion demonstrated that COS/MOS 
devices exhibit reliable switching properties over a wide 
range of power-supply voltages. This fact implies that an 
unregulated supply may be used with the provision that 

(1) maximum voltage limits are not exceeded or 

(2) system speed is no greater than the speed which 
can be supported by the COS/MOS devices operating at 
the lowest value of the Vqid expected from the unregu- 
lated supply. 

To establish the extent of the regulation required, the 
system designer must first determine the maximum 
operating frequency required. Usually, the maximum 
frequency of the system is limited by the slowest 
responding devices in a logic chain. By reference to the 
curve of frequency as a function of Vjyp and Cl given 
in the published data for that device, a minimum Vqd 
voltage (required for proper operation) can be deter- 
mined. Any value above this (minimum) will 

provide acceptable performance in the system. By selec- 
tion of a nominal Vqq half way between Vqjj (mini- 


mum) and the 15-volt maximum rating for COS/MOS 
devices, the designer can estimate the percentage regula- 
tion required for his system to perform adequately. 

For example, the published data of the RCA 
CD4024A 7-stage binary counter shows a curve (shown in 
Fig. 9) of frequency as a function of operating voltage 
for that device. For operation of this counter at 5 MHz, 
with a loading capacitance of 15pF, the minimum operat- 
es V DD permitted for reliable operation is 10 volts, as 
shown on the curve. 

Because the maximum Vjyp is 15 volts, a half-way 
voltage of 12.5 volts should be the nominal value used. 
In this case, the maximum percentage regulation is 20%. 
If the designer desires a nominal V D £) closer to Vj)£) 
minimum, then better regulation is required, (for example 
in battery-operated equipment where a standard cell is 
available). 

Filtering Requirements 

Power-supply filtering requirements for COS/MOS 
systems are minimal. Two factors account for this 
situation: (1) the low quiescent power dissipations 
involved, and (2) the fact that the peak value of the 
ripple does not go below a minimum Vj)£> (which 
supports the required switching frequency), so that the 
COS/MOS logic performs satisfactorily. 



Fig. 9— Maximum frequency as a function of power- 
supply voltage for the CD4024A types. 


This performance has been demonstrated in the 
laboratory (see Fig. 10). The amount of ripple on the 
power supply is quite high, yet the device functions 
properly. 

Typical Supplies 

The following circuits indicate some examples of 
adequate supplies for COS/MOS systems. 


566 




ICAN-6576 



Fig. 10— Peak-to-peak ripple voltage as a function of 
frequency. 

Battery Standby System 

D| 

+o — H t 

0z± 

VDC 

BATTERY 

-O •“ 


Fig. 1 1— Battery standby for COS/MOS systems. 

This system is advantageous in cases where the dc 
supply becomes open or short-circuited. 

With a low battery voltage the COS/MOS system will 
continue to function without interruption. In order to 
drive this system the battery voltage and dc supply 
voltage should relate as follows: 

v battery = v min. + °- 7v > (°- 7v ~ one diode dro P) 
v max. > V DC su PP!y > v min. + >- 4V 

In the event the supply drops below Vj^ , the 
battery will forward bias diode D2 to form a closed- 
circuit and the COS/MOS system will continue to 
function properly through the battery. 

High DC Source 

For applications (especially in aircraft equipment) 
where the supply voltage exceeds the RCA COS/MOS 
maximum rating of Vpj), the circuit of Fig. 12 can be 
used to reduce the high supply voltage to the normal 
COS/MOS voltage range. This configuration uses a Zener 
diode, a resistor R and a capacitor C. 

The low current demand of the COS/MOS system 
permits an inexpensive but effective Zener diode 
regulator. 

Some of the design considerations are as follows: 



Fig. 12- Circuit for interface of COS/MOS systems to 
high-voltage supply. 

1. Selection of Zener Diode and Resistor R 

The amount of current that must be maintained 
through the diode (Id) is a function of the difference 
between the worst-case average current required by the 
COS/MOS systems and the current required by the 
Zener diode for regulation based on its particular 
breakdown characteristics. 

The diode current (Id) and the worst-case average sys- 
tem current (I avg ) determine the value of the resistor 
(R) for a particular Zener regulating voltage. 

2. Selection of Capacitance C 

Before the proper capacitance can be selected the 
following system requirements must be decided upon: 

a. Peak charge requirement. This requirement is a func- 
tion of the peak current and its pulse width. It must 
be measured for the particular system speed and 
load capacitance. 

b. Permissible VdD minimum: As mentioned in pre- 
vious sections, this minimum voltage will determine 
the maximum operating speed of the COS/MOS 
system. 

The size of the capacitor (C) may then be determined 
from the following formula: 

Q = Ipt (charge = peak current x pulse width) 
SUMMARY 

This Note shows that RCA COS/MOS devices offer many 
advantages in the area of simplified power-supply require- 
ments. The wide operating voltage range (3 to 15 volts) 
from a single supply, low power dissipation, and high 
noise immunity permit system designers to use less ex- 
pensive, unregulated, power supplies. This wide voltage range 
makes COS/MOS logic circuits ideal for battery-operated 
equipment because a better selection of cells is feasible. 
Another advantage is the direct compatibility of COS/MOS 
devices with bipolar devices which eliminates expensive and 
power -consuming interface circuits. (See Ref. 1.) 

COS/MOS transistors show great potential for use in 
large arrays because of the low power dissipation and 
effective use of chip area. The relatively small area 
consumed by COS/MOS circuits, as well as the elimina- 
tion of area and power-consuming resistors, results in high 
circuit-density per unit-silicon-area. 

The performance features mentioned in this Note, as well 
as the reduced costs inherent in IC technology make COS / 
MOS circuits extremely attractive in many digital systems. 

1 . “Interfacing COS/MOS WITH OTHER LOGIC Families”, 

ICAN6602 by A. Havasy and M. Kutzin. 


COS/MOS 

SYSTEM 


567 






Solid State 
Division 


Digital Integrated Circuits 

Application Note 
ICAN-6600 


Arithmetic Arrays using 
Standard COS/MOS Building Blocks 


By A. Havasy 


This Note describes me design of a COS/MOS arithmetic 
unit. The RCA COS/MOS product line includes a standard 
line of devices designed to operate from voltage supplies of 5 
to 15V and a low voltage “A” series designed to operate 
from voltage supplies of 3 to 1 5 V. These devices are available 
in any of the package types or temperature ranges shown in 
Table I. 

TABLE I 



Package 

Operating Temperature 
Range (°C) 

Type 

Suffix 


Dual-in-line 

ceramic 

5-15V 3-1 5V ("A") 

D D 

-55 to + 125 

Plastic 

E E 

-40 to + 85 

Flat Pack 

K 

-55 to + 125 


When ordering COS/MOS devices, the appropriate suffix 
should be affixed to the number of the device required, (i.e., 
if a low voltage, plastic package, four bit full adder is desired, 
order CD4008AE). This Note is applicable to both COS/MOS 
product lines, and all package types mentioned above. 

Arithmetic Unit 

This arithmetic unit is capable of adding, subtracting, 
multiplying, and dividing. It is also able to perform the 
logical functions of “OR”, “AND” and the “Exclusive OR” 
of two 4-bit words. Three 4-bit registers are provided that 
permit either of two words to perform a desired operation 
with a third word. The system is configured with standard, 
commercially available, COS/MOS devices which include 
registers, AND-OR select gates, a full adder, as well as NOR 
and NAND gates. A block diagram of the 4-bit arithmetic 


unit is shown in Fig. 1 . The required package count and the 
function performed by each package are shown in Table II. 

A brief description of each COS/MOS device used in the 
arithmetic system follows: 

Four-Bit Full Adder - CD4008 or CD4008A 

The CD4008 or CD4008A consists of four full-adder 
stages with fast look-ahead carry provision from stage to 
stage. Circuits are included to provide a fast parallel-carry-out 
bit, which permit high-speed operation in arithmetic sections 
that use several CD4008’s or CD4008A’s. 

The CD4008 or CD4008A inputs include the four sets of 
bits to be added (Aj to A 4 and Bj to B), and the carry-in bit 
from a previous section. CD4008 or CD4008A outputs 
include the four sum bits, SI to S4, and the high-speed 
parallel-carry-out, which may be used as the input to a 
succeeding CD4008 or CD4008A section. 

The logic diagram for thjs device is shown in Fig. 2. The 
electrical characteristics and more detailed information (for 
the CD4008 or CD4008A) are given in the RCA Data 
Bulletin File No. 405 or 479, respectively. 

Quad AND-OR Select Gate - CD4019 or CD4019A 

The CD4019 or CD4019A consists of four AND-OR 
select gate configurations, each of which have two 2 -input 
AND gates driving a single 2-input OR gate. Selection is 
performed by control bits K a and K^. In addition to the 
selection of either channel A or channel B information, the 
control bits can be applied in combination to accomplish a 
third selection of data. The logic diagram for the CD4019 or 
CD4019A is shown in Fig. 3. The electrical characteristics 
and additional application diagrams for the CD4019A are 
given in the RCA Data Bulletin, File No. 439 or 479, 
respectively. Applications of this device to shifting and logic 
selection operations are discussed later in this Note. 

Dual D-Type Flip-Flop - CD4013 or CD4013A 

The RCA CD4013 or CD4013A consists of two identical, 
independent data-type flip-flops on a single monolithic 
silicon chip. Each flip-flop has independent data, reset, set, 
and clock inputs and complementary buffered outputs. 


568 


3-71 






ICAN-6600 



Fig. 1- Four-bit arithmetic unit, block diagram 


These devices can be used in shift register applications, and in 
counter and toggle type flip-flop applications, by connection 
of the Q output back to the data input. The logic level 
present at the D input is transferred to the Q output during 
the positive-going transition of the clock pulse. Resetting or 
setting is accomplished by the application of a high logic 
level to the reset line or set line, respectively. Fig. 4 shows 
the logic diagram for one flip-flop section of the CD4013 or 
CD4013A. The electrical characteristics and additional 
information for this flip-flop are given in the RCA Data 
Bulletin, File No. 41 1 or 479, respectively. 

Quad 2 - Input NAND Gates - CD4011 or CD4011A 

The RCA CD4011 or CD4011A consists of four, 
identical, independent 2-input positive-logic NAND gates. 
Fig. 5 shows the logic diagram and Boolean equations for this 
device. The electrical characteristics and additional informa- 
tion for these logic gates are given in the RCA Data Bulletin, 
File No. 420 or 479, respectively. 


Quad 2 — Input NOR Gates — CD4001 or CD4001A 

The RCA CD4001 or CD4001A consists of four, 
identical, independent 2-input positive-logic NOR gates. Fig. 
6 shows the logic diagram and Boolean equations for this 
device. The electrical characteristics and additional informa- 
tion for these logic gates are given in the RCA Data Bulletin, 
File No. 345 or 479, respectively. 

Arithmetic Unit Operation 

The A register uses a CD4019 or CD4019A quad 
AND-OR select gate to present either the true or the 
complemented data to the logic circuits and the adder. Thus, 
the data in the A register can be either added or subtracted 
from the B or C registers. 

The CD4019 or CD4019A at the input of the B register 
has two control lines which permit data to be shifted right or 
left, or which permit new data to be accepted from the bus 
lines. Fig. 7 shows the interconnection diagram of two 
CD4019’sor CD4019A’s that perform the shift-right shift-left 
and arithmetic/logic shift functions. 


569 

















I CAN -6600 


TABLE II PACKAGE COUNT FOR THE ARITHMETIC UNIT 




HIGH SPEEl 

)| (CARRY- IV^ 

PAR. CARRY 

OUT) 



L 

SUM 

-SO** 

3 

_ !io s 2 

2 

pOQS, 




- 




“Tca 

SUM 

b 3(J 

A 







B 2Lr- 

- 


— 

SUM 




in 

B i o~ - 

a, pZ_. 



SUM 

m i 

C. p 9 1 ► 


_r 

(CARRY 

T 

T 

IN) 

ERMINAL No. I6 = Vdd 
ERMINAL No. 8 = V ss 



Fig. 2- Four-bit full adder, logic diagram. 


The arithmetic shift mode is used only on the highest 
order bits and insures that the sign bit does not change 
during the shifting. On the lowest order bits the left shift 
input for the B register (BRS1) is tied to the Bg output of the 
next higher set of bits. 

The C register is identical to the B register but does not 
provide for arithmetic mode shifting. Separate shift-right and 
shift-left controls are provided for the B and C registers. 
(BSL and BSR is provided for the B register, and CSL and 
CSR for the C register). Another CD4019 or CD4019A is 
used to select either the B or the C register information for 
the logic and arithmetic operations. 



92SS-M16R1 


Fig. 3- CD4019 or CD4019A - Logic diagram. 


The logic block diagram for the AND/OR/Exclusive-OR 
logic selector is shown in detail in Fig. 8. One and 
one-quarter CD4001’s or CD4001A’s and one-quarter 
CD4019/CD4019A are used per bit, (or five CD4001 or 
CD4001 A and the CD4019 or CD4019A per four-bit word). 
The control inputs are labeled K(*) (K-AND) and K(®) 
(K-Exclusive OR). An example of logic selection is as 
follows: 

Assume that Bi is an output from the B register and A] 
is a true output from the A register via the True/Complement 
Switch. (Refer to Fig. 1) When K(*) is “high” and K(©) is 
“low”, the logic generated is AB. When K(*) is low and 

K(®) is high, the logic generated is A ® B = AB + AB. When 
both K(-) and K(ffi) are “high”, the logic is AB + (A ® B) = 
AB + AB + AB = A +B. 

The adder is a single CD4008 or CD4008A previously 
described. The carry input of this adder will be tied to the 
carry output of the adder on the next-lower-order CD4008 
or CD4008A. The carry input of the lowesttorder bits will be 
a logic “0” for addition and a logic “1” for the 2’s comple- 
ment subtraction. 

The output buffer is also a CD4019 or CD4019A. In this 
application the device is used to select either the arithmetic 
or the logic outputs and to provide more output drive. 

The output overflow circuit (shown in Fig. 9) will go 
“high” if the adder result exceeds the total bit capacity of 
the arithmetic unit. This overflow occurs only when two 
numbers that have the same sign bit are added and, the result 
is a sum which has the opposite sign. 


570 





I CAN -6600 



TERMINAL 14 > Vqd 
TERMINAL 7 = CND 

TRUTH TABLE 




Fig. 4— CD4013 or CD4013A - Logic diagram and truth 
table (one of two identical flip-flops). 



Fig. 5— CD401 1 or CD401 1A - Logic diagram and equations. Fig. 6- CD4001 or CD4001A - Logic diagram and equations. 


A larger arithmetic unit of any desired word length can 

be made by cascading additional circuits. The interconnection inverted clock signal (which are common to all eight sub- 

of eight systems to form a 32-bit arithmetic unit is shown in systems) are not shown. Table III shows the functions and the 

Fig. 10. The three inhibit signals, common control signals, and symbols. 


571 








I CAN-6600 


ARITHMETIC _ 
SHIFT 


RS, 8R, NU NU 

A O JL 



SHIFT LEFT- 
SHIFT RIGHT - 


A3 A 2 A, Aq CD40|9AD 
(SHIFT RIGHT) CD40I9AD 

B 3 B 2 B| b 0 

(SHIFT LEFT) 

SHIFT RIGHT/SHIFT LEFT 

d 3 d 2 °l °0 



TO B REGISTER 


FROM A 



TABLE III FUNCTIONS AND SYMBOLS 


RSI * RIGHT SERIAL INPUT 
LSI - LEFT SERIAL INPUT 
BR n * OUTPUT OF n th BIT 
OF "B" REGISTER 
NU = NOT USED 


Fig. 7- Shift-Right/Shift-Left - Arithmetic/Logic shift 
Interconnection diagram. 


L 

L jLifxJ^ litl^ Jjd&lij 

J~ | 1 CD400IA j 1 CD400IA | j CD400IA 1 

J! jL i: i 

[ y 


CD400IA | 

1 

A|©B| 

A,"B, A 2 ©B2 

a 2 -b 2 a 3 ©b 3 a 3 -b 3 a 4 ©b 4 A 4 .B 4 

! j 

Kt 1 ffj 

4 

? Hr 


OUT I OUT 2 


OUT 3 OUT 4 


TRUTH TABLE 


K[*J 

K[©j 

OUT 

0 

0 

0 

1 

0 

A-B 

0 

1 

A© B 

1 

1 

A + B 


Fig. 8- AND/OR/EXCLUSIVE-OR Selector. 


SYMBOLS 


FUNCTIONS 


V DD 

GND 

CL 

IN 0 

IN-, 

in 2 

in 3 

Enable A 
Enable B 
Enable C 
A 

A 

SEL B 

SELC 

Arith- 

metic 

shift 

Logic 
shift 
B Bus 
B shift 
BSR 
BSL 
BSR I 

BSLI 

C Bus 
C shift 
CSR 
CSL 
CSR I 

CSLI 


Input for positive power supply 
Ground 
Inverted clock 
Lowest order bus input 
Second lowest order bus input 
Third lowest order bus input 
Highest order bus input 
Enables the A register 
Enables the B register 
Enables the C register 

Selects the true of the A register data for half-output 
function 

Selects complement of A register data for half-output 
function 

Selects B register data for output function with A 
register data 

Selects C register data for output function with A 
register data 

Allows B register to shift in the arithmetic mode 

Allow C register to shift in the logical mode 

Allows B register to accept data from bus inputs 

Allows B register to shift right or left 

Allows B register to shift right 

Allows B register to shift left 

I nput to lowest order bit of the B register when 

shifting right 

Input to highest order bit of B register when shifting 
left 

Allows C register to accept data from bus inputs 
Allows C register to shift right or left 
Allows C register to shift right 
Allows C register to shift left 

Input to lowest order bit of C register when shifting 
right 

Input to highest order bit of C register when shifting 
left 


Arith- 

metic 

Logic 

C IN 

C OUT 


Allows logical sums to appear at S outputs 

Allows logic functions to appear at S outputs 
Carry in to lowest order bit of adder 
Carry out from highest order bit of adder 


572 






ICAIM-6600 


TABLE III (CONTINUED) 

SYMBOLS FUNCTIONS 

Overflow Indicates if addition exceeds limit of adder 

K(*) Generates logical AND of logic circuits 

K(©) Generates logical EXCLUSIVE-OR of logic circuits 

Sg Lowest order sum output 

S-| Second lowest order sum output 

52 Third lowest order sum output 

53 Highest order sum output (sign bit) 


Performance Data 

In a 32-bit arithmetic unit constructed in the laboratory 
the delay time, (under worst-case logic conditions) for the 
inverted clock to be inverted, for data to be written into the 
register, and for that data to get to the adder and generate a 
carry-out from a 4-bit system was found to be 782 
nanoseconds. The delay time (under worst-case logic condi- 
tions) for a carry-in to generate a carry-out was found to be 
87 nanoseconds. The delay time under worst-case logic 
conditions for a carry-in to generate a sum at the adder and 
for this sum to appear at the outputs was found to be 623 


nanoseconds. These numbers result in an addition time of 
1927 [782 + (6 x 87) + 623] nanoseconds for two 32-bit 
words and 1579 [782 + (2 x 87) + 623] nanoseconds for two 
16-bit words. 

Since the construction of this adder, improved processing 
techniques permit faster operation. The delay from the clock 
to the carry out can be expected to be less than 500 ns; the 
delay from the carry -in to the carry-out can be expected to 
be less than 50 ns; and the delay from the carry in to the sum 
out can be expected to be less than 400 ns. Thus, the 
maximum addition time for a 32-bit arithmetic unit would 
be approximately 1200 ns; for a 16-bit unit, 1000 ns 
(maximum) would be required. 

Calculations indicate a typical power dissipation of 100 
/ iW and 2350 juW for the 4-bit arithmetic unit. These calcula- 
tions are based on typical and maximum device quiescent 
power dissipations at a 10-volt supply and +25°C tempera- 
ture. 

Summary 

A complete 32-bit full adder/arithmetic logic system that 
uses standard COS/MOS devices (commercially available in 
quantity) is shown. This system offers many adantages to the 
systems designer: low power dissipation, high noise im- 
munity and reliability. 



Fig. 10 — Major interconnections to form 32-bit arithmetic 
unit from 4-bit subsystems. 


573 



□UQB/5D 

Solid State 
Division 


Digital Integrated Circuits 

Application Note 
ICAN-6601 


Transmission and Multiplexing of 
Analog or Digital Signals Utilizing 
the CD4016A Quad Bilateral Switch 

by J. Litus, Jr., S. Niemiec, and J. Paradise 


RCA type CD4016A Quad Bilateral Switch is an 
extremely flexible device. It has many advantages unique to a 
COS/MOS* switch configuration and can be used for the 
transmission of analog or digital signals with low distortion. 
The CD4016A is the ideal semiconductor switch for use in a 
multitude of switching applications. This note describes some 
of the features and several applications of COS/MOS tran- 
sistor bilateral signal switches (transmission gates). 


OPERATION OF THE COS/MOS SWITCH 

Fig. 7 shows the transfer characteristics of a single 
p— channel MOSFET switch (with a high value of load 
resistance Rl) in the “ON” condition. If it is assumed that 
this application calls for an input signal voltage (Vj) in the 
range of -5 to +5 V., and that the output signal voltage Vo 
follows the input signal voltage linearly within this voltage 
range, the switch will be “ON” for the following conditions: 


FEATURES OF THE CD4016A 

The functional diagram of. the CD4016A is shown in 
Fig. 1. The CD4016A consists of four independent bilateral 
signal switches on a single silicon monolithic chip. Each 
switch consists of an n— channel and a p— channel device. The 
source of the p— channel device is connected to the drain of 
the n— channel device and vice-versa. Only one control signal 
VC is required per switch. Vc directly controjs the 
n— channel unit; the p-channel unit is controlled by Vc (an 
inverter is included on the chip). Both channels are biased 
“ON” or “OFF” simultaneously by the control signal V(\ 
Fig. 2 shows the schematic diagram of the CD4016A. 

Unlike the bipolar switch, the COS/MOS switch has no 
voltage offset. It is a bi-directional switch. The COS/MOS 
switch does not require an excessively large control voltage 
(compared with the incoming signal level), as does the single 
channel MOS switch. The control voltage required by the 
COS/MOS switch is of approximately the same amplitude as 
the input signal. The incoming signal can be a maximum 
of |VdD - Vss! = 15 V., or a minimum of |Vdd _ v SSl = 3 V. 

Figs. 3 and 4 show the typical “ON” transfer character- 
istics of the COS/MOS switches. Figs. 5 and 6 show the 
output voltage as a function of time for an input sine wave 
and square wave voltage respectively. 


Threshold voltage (Vth) = +5 V. 

Gate voltage (Vq) = -10 V. 

Substrate voltage (V su b) = +5 V 
Input signal voltage (VQ > -5 V. 

When the switch is “ON”, the input signal voltage is 
transmitted to the output terminal (subject to the above 
conditions). However, if the input signal voltage falls below 



- CONTROL A 


-INPUT 
SIGNAL 0 

- OUTPUT 

- OUTPUT 
SIGNAL C 

- INPUT 


*Complementary-Symmetry Metal-Oxide-Semico nductor 


Fig. 1— Functional diagram (top view). 


574 


8-71 









ICAN-6601 


-5 V., (i.e., Vth)> switch operates as a source follower. 
To avoid this condition, the magnitude of the p-channel gate 
voltage must be increased by the sum of the threshold 
voltage and the peak input voltage, | Vj(max) + Vjh| • 

The problems encountered in the single channel 


MOSFET switch can be eliminated by the use of a parallel 
complementary MOSFET arrangement, shown in Fig. 8a. 
The voltage transfer characteristics (Vo as a function of Vi) 
are shown in Figs. 8b (single p-channel device), 8c (single 
n-channel device), and 8d (composite for both devices in 



NOTE: All switch P-channel substrates are internally connected to terminal No. 14. 
All switch N-channel substrates are internally connected to terminal No. 7. 

NORMAL OPERATION: 

Control Line Biasing 

Switch "ON": V C "1 " = V DD SIGNAL-LEVEL RANGE: 

Switch "OFF": Vc"0" = V S s V S s4.Vjs^V D D 


Fig. 2— Schematic diagram. 



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illillil 


sssssH 

ov “ 


- 4-2 0 2 4 6 


INPUT SIGNAL VOLTS (V| S ) 


Fig. 3- Typ. "ON" characteristics for 1 of 4 switches with 
VqD = +10V, Vss=OV (CD4016A). 


Fig. 4— Typ. "ON" characteristics for 1 of 4 switches with 
Vqd = +5V, Vss = -5V (CD4016A). 


575 




ICAN-6601 


parallel). The load resistance, Rl is assumed to be large 
compared with the MOSFET “ON” resistance (Ron)* The 
composite characteristics are obtained by the graphic 
addition of the individual characteristics. The “ON” 
characteristics show that at least one device is “ON” at any 
given instant, because one gate is controlled by Vc and the 
other by the complement, Vc* 



SCALE: X = 0.2 ms/DIV Y-2.0V/DIV 
V D D - V C « +7.5V, V S s = -7.5V, R L - 10KD 
C L - 15 pF 

flS-lkHz V| S ■ 5V p-p 
DISTORTION - 0.2% 


(a) 



SCALE: X- 0.2 ms/DIV Y« 2.0 V/DIV 
V D D * Vc - +2.5V, V S s - -2.5V, R L - 10KJ2 
C L > 15 pF 

f|S “ 1 kHz V|s “ 5V p-p 
DISTORTION = 3% 


(b) 


Fig. 5- a ) Typ. Sine wave response of \ SqD = +7.5V, V$S = 
-7.5V; b) Typ. sine wave response of V[)D = +2.5V, 
V S S = 2.5V. 



SCALE: X • 100 ns/DIV 
Y = 5.0 V/DIV 


(a) 



SCALE: X= 100 ns/DIV 
Y = 2 V/DIV 


(b) 


The gate control voltage required (± 5 V in this case) 
need only be equal to the absolute value of the peak input 
signal voltage. The maximum input signal voltage range is 
limited by Vdd ( +5 V) and V$S (-5 V). The gate control 
voltages would then be +5 V and -5 V respectively. 
There is a minimum threshold voltage (Vjh) required to 
turn “ON” the switch. This condition must always be met 
for proper operation — see published data. Ref. 1 . 


LEGEND: 



Fig. 7— Single p-channel MOS/FET switch characteristics 



Fig. 6— a) Typ. square wave response at Vqd ~ Vq= +15V, 
Vss = Grid- b) Typ. Square wave response at Vqd 
= Vq = +5V, Vss “ G n d- 


Fig. 8- a) COS/MOS FET switch (transmission gate); b) 
p-channel characteristics; c) n-channel character- 
istics; d) composite characteristics. 


576 






1CAN-6601 


SWITCH AND LOGIC APPLICATIONS 
Switch Functions 

The CD4016A Quad Bilateral Switch can be used to 
perform the four common switch functions shown in Fig. 9 
(i.e., SPST, SPDT, DPST, and DPDT). 


a) SPST 



b) SPDT 



V-= v^o—0° S2 

v is 

■ov c _TL 


V|S ^_>o-o V0SA 

O— o4o— I O 

V ISB V OSB 

-° Vc _n_ 


d) DPDT 



V ISAC 




3 V 0SB 


VlSBO — t 


Fig. 9— Basic switch functions using the CD4016A. 
Logic Functions 

Fig. 10a illustrates the use of the CD4016A to gate 
digital (or analog) signals. When the CD4016A is used as a 
digital “OR” gate, a logic “1” should be present at points a 
and b. Two control voltages A and B are required as shown. 
When a logic “1” is not being transmitted (A = B = “0”), a 
logic “0” appears at the output. There are two methods to 
achieve this result: (1) a resistor tied from the output 
terminal to a logic “O”, or (2) the remaining two 
transmission gates of the CD4016A can be connected (as 
shown in Fig. 10a) to a logic “0” and be gated by the 
complement of the control functions A and B (i.e., A and B). 
Use of the resistor tied to a logic “O” will provide the 
designer with two “OR” gates from a single CD4016A. Use 
of the two transmission gates (in place of the resistor) 
provides lower power dissipation. 


Analog signals may be used in place of the logic “1” 
signals at the signal input terminals (Vis) to the transmission 
gates and these analog signals may be passed to the output if 
a particular logic function is satisfied. A general logic 
function may be implemented by the use of transmission 
gates as shown in Fig. lOd. The function illustrated is F = AB 
+ CD. The implementation of some logic functions may be 
simpler and the propagation delay time may be shorter when 
transmission gates are used. The input signals (a, b and c in 
Fig. lOd) may be analog signals or digital signals. The 
transmission gates may be used in a wired “OR” configura- 
tion, which simplifies many logic designs. 

Transmission gates may also be used in flip-flop or 
memory cell circuits. Fig. 1 1 shows transmission gates being 
used in conjunction with NOR gates and inverters to 



(a) (b) 



(c) (d) 

Fig. 10— Logic functions using the CD4016A: a) "OR" gate; 
b) "AND" gate; c) "NOT" (inverter) gate; d) 
implementation of F = AB + CD using die 
CD4016A. 

implement a master-slave type D flip-flop. These flip-flops 
are available commercially. (See Ref. 2.) All COS/MOS logic 
elements (gates, flip-flops, complex MSI and LSI functions) 
are comprised of the basic COS/MOS Transmission gate 
(parallel connection of p- and n- channel units) plus the basic 
COS/MOS inverter (series connection of p- and n- channel 
units). (See Ref. 2.) 


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Multiplexing/Demultiplexing 

A four channel PAM (Pulse Amplitude Modulation) 
Multiplex/Demultiplex system utilizing the CD4016A is 
shown in Fig. 12a. Commutator, MUX, and DMUX are the 
building blocks used to implement the system. Each input 
signal is sampled sequentially and applied to a single 
transmission line, but in a different time slot. The signals are 
detected and reconstructed at the outputs. These outputs 
will be proportional to the inputs, with no loss of 
information, as long as the conditions of Nyquist’s sampling 
theorem are met: Sampling rate must be greater than twice 
the maximum frequency component of the input signal. 

An RCA type CD4018A- “Divide-by-N” counter and 
associated decoding circuitry are used to provide the 
sequential signals to the control inputs of the CD4016A 
switches. The analog information is present at the outputs of 
the CD4016A only during the “ON” time of each switch. 
The clock frequency required for the counter is as follows: 

fcl>2fmN c 

where f m is the bandwidth of the input signal and N c is the 
number of channels being sampled. For example, the circuit 
shown in Fig. 12a has a maximum input signal bandwidth of 
10 kHz. Therefore, 

f c l > 2 (10kHz) (4) = 80kHz. 


The clock pulse is also applied to the transmission line to 
provide synchronization pulses for output decoding. A 
narrow clock pulse is used to prevent significant interaction 
between the clock and the sampled information. These clock 
pulses are removed from the output waveforms by taking 
advantage of the threshold voltage of a second counter 
(CD4018A). The magnitude of the analog signals is kept at a 
lower level than the switching voltage [Vjl (max)] of the 
CD4018A or the CD4009A (Inverter A). [Vjl (max) = 30% 
of Therefore, only the clock pulses trigger the second 

counter. Inverter A opens the transmission line during the 
clock interval. Signals can be transmitted at all other times. 
In this example, the clock is transmitted on the same line as 
the analog information, although this procedure need not be 
followed. Separate transmission of the clock signal removes 
any restrictions on the signal amplitude provided the signal 
swing is maintained within the range of the Vdd and Vss 
supply levels. 

The output decoding is identical to the input decoding. 
The low-pass filters have a bandwidth equal to the bandwidth 
of the system and are used to filter the high frequency 
components generated by the sampling process, and to 
reconstruct the signals. Figs. 12b, c, and d show the 
waveforms of the signals at various points in the circuit. 

Measurements and observations of a laboratory proto- 
type of the PAM system discussed above, are presented 
below. Note: In the “all COS/MOS system”, the switch 



* = INVALID CONDITION 


CL* 

D 

R 

Li_ 

0 

Q 

_y 

0 

0 

0 

0 

1 


1 

0 

0 

1 

0 


X 

0 

0 

Q 

Q 

X 


~ 

0 

0 

1 

* 

* 

0 


1 

~0~ 

* 

X 

1 

I 




NO 

CHANGE 


**TG = TRANSMISSION GATE 


INPUT TO OUTPUT IS: 
o) A BIDIRECTIONAL LOW IMPEDANCE 
WHEN CONTROL INPUT 1 IS "LOW” 
AND CONTROL INPUT 2 IS “HIGH” 



b) AN OPEIiCIRCUIT WHEN CONTROL 

INPUT 1 IS “HIGH” AND CONTROL INPUT 2 IS "LOW” 


a = LEVEL CHANGE 
* = DON’T CARE CASE 


Fig. 1 1— Type "D" flip-flop logic diagram and truth table. 


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control signals are compatible with commonly used control 
system logic levels. Analog input signals whose magnitude is 
equal in amplitude to these control signals, can be used. The 
analog signals may be of either polarity, positive or negative. 


Conditions: 

Signal Input voltage frequency: 100 Hz to 10 kHz 
Peak to Peak input: 400 mV 1 

RC Low pass filter cut-off frequency: — -- = 1.33kHz 

2;rKL 


(R = 1 2 kf2, C = 0.01/uF) 

Results: 

“ON” channel attenuation: 13dB